Datasheet AD5207BRU50-REEL7, AD5207BRU100-REEL7, AD5207BRU10-REEL7 Datasheet (Analog Devices)

2-Channel, 256-Position

RDAC1 REGISTER

R

RDAC2 REGISTER

R

POWER-

ON

RESET

LOGIC

SERIAL INPUT REGISTER

AD5207

8

SDO

DGND

SDI

CS

V

SS

SHDN

V

DD

A1 W1 B1 A2 W2 B2

CLK

a

FEATURES
256-Position, 2-Channel
Potentiometer Replacement
10 k, 50 k, 100 k
Power Shut-Down, Less than 5 A

2.7 V to 5.5 V Single Supply
2.7 V Dual Supply
3-Wire SPI-Compatible Serial Data Input
Midscale Preset During Power-On

APPLICATIONS
Mechanical Potentiometer Replacement
Stereo Channel Audio Level Control
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Automotive Electronics Adjustment

GENERAL DESCRIPTION

The AD5207 provides dual channel, 256-position, digitally
controlled variable resistor (VR) devices that perform the same
electronic adjustment function as a potentiometer or variable
resistor. Each channel of the AD5207 contains a fixed resistor with
a wiper contact that taps the fixed resistor value at a point
determined by a digital code loaded into the SPI-compatible
serial-input register. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the VR latch. The variable resistor
offers a completely programmable value of resistance, between
the A Terminal and the wiper or the B Terminal and the wiper.
The fixed A-to-B terminal resistance of 10 kΩ, 50 kΩ or 100 kΩ
has a ±1% channel-to-channel matching tolerance with a nomi­nal temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional switched
resistor designs and avoids any make-before-break or break­before-make operation.

Each VR has its own VR latch, which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register, which is loaded from a standard
3-wire serial-input digital interface. Ten bits, to make up the
data word, are required and clocked into the serial input register.

Digital Potentiometer

AD5207

FUNCTIONAL BLOCK DIAGRAM

The first two bits are address bits. The following eight bits are
the data bits that represent the 256 steps of the resistance value.
The reason for two address bits instead of one is to be compatible
with similar products such as AD8402 so that drop-in replacement
is possible. The address bit determines the corresponding VR
latch to be loaded with the data bits during the returned positive
edge of CS strobe. A serial data output pin at the opposite end
of the serial register allows simple daisy chaining in multiple
VR applications without additional external decoding logic.

An internal reset block will force the wiper to the midscale posi­tion during every power-up condition. The SHDN pin forces an
open circuit on the A Terminal and at the same time shorts the
wiper to the B Terminal, achieving a microwatt power shutdown
state. When SHDN is returned to logic high, the previous latch
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface remains active during shutdown;
code changes can be made to produce new wiper positions when
the device is resumed from shutdown.

The AD5207 is available in 1.1 mm thin TSSOP-14 package,
which is suitable for PCMCIA applications. All parts are guaran­teed to operate over the extended industrial temperature range
of –40°C to +125°C.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD5207–SPECIFICATIONS

(V

ELECTRICAL CHARACTERISTICS 10 k, 50 k, 100 k VERSION

= 5 V, V

DD

VB = 0, –40C < TA < +125C unless otherwise noted.)

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS
RHEOSTAT MODE
Specifications Apply to All VRs

Resistor Differential Nonlinearity
Resistor Nonlinearity

2

Nominal Resistor Tolerance
Resistance Temperature Coefficient R
Wiper Resistance R
Nominal Resistance Match ∆R/R

DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Specifications Apply to All VRs

Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity

4

4

Voltage Divider Temperature ∆V

Coefficient
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance
Shutdown Current

5

6

AX, B

6

W

X

X

7

Shutdown Wiper Resistance R
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

6

POWER SUPPLIES

Power Single-Supply Range V
Power Dual-Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation

8

Power Supply Sensitivity, V
Power Supply Sensitivity, V

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ 600 kHz
Bandwidth –3 dB BW_50 kΩ R
Bandwidth –3 dB BW_100 kΩ R
Total Harmonic Distortion THD
V

Settling Time t

W

Resistor Noise Voltage e
Crosstalk

10

3

DD

SS

2

R-DNL RWB, VA = NC –1 +1 LSB
R-INL RWB, VA = NC –1.5 +1.5 LSB
∆R –30 +30 %

/∆TV

AB

W

O

= VDD, Wiper = No Connect 500 ppm/°C

AB

IW = 1 V/R, VDD = 5 V 50 100 Ω
Ch 1 to 2, VAB = VDD, TA = 25°C 0.2 1 %

INL –1.5 +1.5 LSB
DNL VDD = 5 V, VSS = 0 V –1 +1 LSB

/∆T Code = 80

W

WFSE

WZSE

VA,

B, W

C

A,B

C

W

I

A_SD

W_SD

CM

IH

IL

IH

IL

OH

OL

IL

C

IL

DD RANGE

DD/SS RANGE

DD

SS

P

DISS

Code = FF
Code = 00

|VDD| + |VSS| ≤5.5 V V
f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
VA = VDD, VB = 0 V, SHDN = 0 5 µA
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 200 Ω
VA = VB = VDD/2 1 nA

VDD = 5 V, VSS = 0 V 2.4 V
VDD = 5 V, VSS = 0 V 0.8 V
VDD = 3 V, VSS = 0 V 2.1 V
VDD = 3 V, VSS = 0 V 0.6 V
RL = 1 kΩ to V
IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V ±10 µA

VSS = 0 V 2.7 5.5 V

VIH = VDD or VIL = GND, VSS = 0 V 40 µA
VIH = VDD or VIL = GND VSS = –2.5 V 40 µA
VIH = 5 V or VIL = 0 V, VDD = 5 V 0.2 mW

PSS ∆VDD = 5 V ± 10%, VSS = 0 V, Code = 80
PSS ∆VSS = –2.5 V ± 10%, VDD = 2.5 V, Code = 80

6, 9

AB

AB

VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 0.003 %
RAB = 10 kΩ/50 kΩ/100 kΩ, ± 1 LSB Error Band 2/9/18 µs
RWB = 5 kΩ, f = 1 kHz, RS = 0 9 nV√Hz
VA = 5 V, VB = 0 V –65 dB

S

N_WB

C

T

W

H

H

H

H

H

DD

–1.5 LSB

SS

VDD – 0.1 V

±2.2 ±2.7 V

H

H

= 50 kΩ 125 kHz
= 100 kΩ 71 kHz

= 0, VA = 5 V,

SS

15 ppm/°C

+1.5 LSB

V

DD

V
45 pF
70 pF

10 pF

0.01 %/%

0.03 %/%

–2–

REV. 0

AD5207

Parameter Symbol Conditions Min Typ

1

Max Unit

INTERFACE TIMING
CHARACTERISTICS
Applies to All Parts

Input Clock Pulsewidth tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay

CS Setup Time t
CS High Pulsewidth t

CLK Fall to CS Fall Hold Time t
CLK Fall to CS Rise Hold Time t
CS Rise to Clock Rise Setup t

NOTES

1

Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = 5 V,
VSS = 0 V.

3

VAB = VDD, Wiper (VW) = No connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.

5

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the AX terminals. All AX terminals are open-circuited in shut-down mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V, VSS = 0 V.

10

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

11

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of

1.5 V. Switching characteristics are measured using VDD = 5 V.

12

Propagation delay depends on value of VDD, RL, and CL; see applications text.

The AD5207 contains 474 transistors. Die Size: 67 mil × 69 mil, 4623 sq. mil.
Specifications subject to change without notice.

6, 11

CL

DS

12

DH

t

PD

CSS

CSW

CSH0

CSH1

CS1

Clock Level High or Low 10 ns

5ns
5ns

RL = 1 kΩ to 5 V, CL < 20 pF 1 25 ns

10 ns
10 ns
0ns
0ns
10 ns

= VDD and VB = 0 V. DNL

A

SDI

CLK

CS

V

OUT

SDI

(DATA IN)

SDO

(DATA OUT)

CLK

CS

V

OUT

1

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0

1

0

1

0

RDAC REGISTER LOAD

Figure 1a. Timing Diagram

1

Ax OR Dx Ax OR Dx

0

1

A'x OR D'x

0

1

0

1

t

CSS

0

V

DD

0V

t

CSH0

t

DS

t

DH

A'x OR D'x

t

CH

t

CL

t

PD_MAX

t

CS1

t

CSH1

t

CSW

t

S

ⴞ1LSB ERROR BAND

ⴞ1LSB

REV. 0

Figure 1b. Detail Timing Diagram

–3–

AD5207

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted)

1

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +7 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0, –3 V

SS

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

V

DD

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

A

2

I

(A, B, W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

MAX

Digital Inputs and Output Voltage to GND . . 0 V, V

DD

DD

+ 0.3 V

Operating Temperature Range . . . . . . . . . . –40°C to +125°C

Maximum Junction Temperature (T

Max) . . . . . . . . . . 150°C

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Thermal Resistance

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Max current is bounded by the maximum current handling of the switches,
maximum power dissipation of the package, and maximum applied voltage
across any two of the A, B, and W Terminals at a given resistance. Please refer to
TPC 22 for detail.

3

Package Power Dissipation = (TJ Max–TA)/θJA.

3

θ

TSSOP-14 . . . . . . . . . . . . . 206°C/W

JA,

PIN CONFIGURATION

V

W2

DGND

SHDN

SS

B2

A2

CS

1

2

3

AD5207

4

TOP VIEW

(Not to Scale)

5

6

7

14

B1

13

A1

12

W1

11

V

DD

10

CLK

9

SDO

8

SDI

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1V

SS

Negative Power Supply, specified for opera-

tion from 0 V to –2.7 V.
2 B2 Terminal B of RDAC#2.
3 A2 Terminal A of RDAC#2.
4 W2 Wiper, RDAC#2, addr = 1

2

5 DGND Digital Ground.
6 SHDN Active Low Input. Terminal A open-circuit

and Terminal B shorted to Wiper. Shut-

down controls both RDACs #1 and #2.
7 CS Chip Select Input, Active Low. When CS

returns high, data in the serial input register

is decoded, based on the address bit, and

loaded into the corresponding RDAC register.
8 SDI Serial Data Input. MSB is loaded first.
9 SDO Serial Data Output. Open Drain transistor

requires pull-up resistor.
10 CLK Serial Clock Input. Positive Edge Triggered.
11 V

DD

Positive Power Supply. Specified for opera-

tion at 2.7 V to 5.5 V.
12 W1 Wiper, RDAC #1, addr = 0

.

2

13 A1 Terminal A of RDAC #1.
14 B1 Terminal B of RDAC #1.

Table I. Serial-Data Word Format

ADDR DATA
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

9

2

NOTES
ADDR(RDAC1) = 00; ADDR(RDAC2 = 01).
Data loads B9 first into SDI pin.

MSB LSB

8

2

7

2

0

2

ORDERING GUIDE

Temperature Package Package Qty Per Branding

Model k Range Description Option Container Information*

AD5207BRU10-REEL7 10 –40°C to +125°C TSSOP-14 RU-14 1,000 B10
AD5207BRU50-REEL7 50 –40°C to +125°C TSSOP-14 RU-14 1,000 B50
AD5207BRU100-REEL7 100 –40°C to +125°C TSSOP-14 RU-14 1,000 B100

*Three lines of information appear on the device. Line 1 lists the part number; Line 2 includes branding information and the ADI logo, and Line 3 contains the

date code YYWW.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

WARNING!

the AD5207 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

ESD SENSITIVE DEVICE

REV. 0

Typical Performance Characteristics–AD5207

CODE – Decimal

INL – LSB

224

–0.2

–0.1

0.0

0.1

0.3

1921601289664320 256

–0.3

0.2

–0.4

0.4

VDD = 5.5V, VSS = 0V

TEMPERATURE – C

I

DD

SUPPLY CURRENT – A

20

–40

V

IL

= V

SS

V

IH

= V

DD

18

16

14

12

10

8

6

4

2

0

–20 0 20 40 60 80 100

VDD = 5.5V

VDD = 2.7V

0.20

0.15

0.10

0.05

0.00

RDNL – LSB

0.05

0.10

0.15

0.20

0.20

0.15

0.10

0.05

0.00

RINL – LSB

–0.05

–0.10

–0.15

–0.20

VDD = 5.5V, VSS = 0V

CODE – Decimal

1921601289664320 256

TPC 1. 10 kΩ RDNL vs. Code

VDD = 5.5V, VSS = 0V

CODE – Decimal

1921601289664320 256

TPC 2. 10 kΩ RINL vs. Code

224

224

TPC 4. 10 kΩ INL vs. Code

1.0

IDD @ VDD/VSS = 5V/0V

0.1

– mA

SS

/I

DD

I

0.001

0.01

ISS @ VDD/VSS = 2.5V

IDD @ VDD/VSS = 2.5V

IDD @ VDD/VSS = 3V/0V

VIH – V

TPC 5. Supply Current vs. Logic Input Voltage

5.04.03.02.01.00.0

0.3

0.2

0.1

0.0

DNL – LSB

–0.1

–0.2

REV. 0

–0.3

TPC 3. 10 kΩ DNL vs. Code

CODE – Decimal

VDD = 5.5V, VSS = 0V

224

1921601289664320 256

TPC 6. Supply Current vs. Temperature

–5–

AD5207

45

VDD = 5.5V

40

35

30

25

20

15

SHUTDOWN CURRENT – nA

10

A_SD

I

5

0

–200 20406080100

–40

TEMPERATURE – C

TPC 7. Shutdown Current vs. Temperature

160

140

120

100

– 

80

ON

R

60

40

20

VDD = 3V

VDD = 5V

120

1000

900

800

700

600

– A

500

SS

/I

DD

I

400

300

200

100

I

SS

I

DD

I

@ VDD/VSS = 5V/0V

DD

I

@ VDD/VSS = 3V/0V

DD

0

10k

100k 1M 10M

FREQUENCY – Hz

@ VDD/V

@ VDD/V

CODE 55

= 2.5V

SS

= 2.5V

SS

H

TPC 10. 10 kΩ Supply Current vs. Clock Frequency

80

60

– dB

40

PSRR

20

+PSRR @ V

–PSRR @ V

DD

+PSRR @ V

= 3V DC 10% p-p AC

DD

CODE = 80H, VA = VDD, VB = 0V

= 5V DC 10% p-p AC

= 3V DC 10% p-p AC

DD

0

06

V

SUPPLY

– V

TPC 8. Wiper ON Resistance vs. V

1000

900

800

700

600

– A

/I
I

SS

DD

500

400

300

200

100

I

@ VDD/VSS = 3V/0V

DD

0

10k

100k 1M 10M

FREQUENCY – Hz

I

SS

I

@ VDD/V

DD

I

@ VDD/VSS = 5V/0V

DD

@ VDD/V

SUPPLY

CODE FF

= 2.5V

SS

= 2.5V

SS

54321

H

TPC 9. 10 kΩ Supply Current vs. Clock Frequency

0

100 1k 10k 1M100k

TPC 11. Power Supply Rejection Ratio vs. Frequency

0

–6

–12

–18

–24

–30

GAIN – dB

–36

–42

–48

VDD = +2.7V

= –2.7V

V

SS

–54

V

= 100mV rms

A

= 25C

T

A

–60

1k 10k 100k 1M

TPC 12. 10 kΩ Gain vs. Frequency vs. Code

FREQUENCY – Hz

DATA = 80

DATA = 40

DATA = 20

DATA = 10

DATA = 08

DATA = 04

DATA = 02

DATA = 01

V

A

FREQUENCY – Hz

H

H

H

H

H

H

H

H

OP42

–6–

REV. 0

AD5207

FREQUENCY – Hz

–5.99

GAIN – dB

10k 100k100 1k

–6.00

–6.01

–6.02

–6.03

–6.04

–6.05

–6.06

–6.07

–6.08

–6.09

100k

VDD = +2.7V
V

SS

= –2.7V

V

A

= 100mV rms

DATA = 80

H

TA = 25C

V

A

OP42

V

B

= 0V

10k

50k

0

DATA = 80

–6

–12

–18

–24

–30

GAIN – dB

–36

–42

–48

VDD = +2.7V
V

= –2.7V

SS

–54

V

= 100mV rms

A

= 25C

T

A

–60

1k 10k 100k 1M

V

A

H

DATA = 40

H

DATA = 20

H

DATA = 10

H

DATA = 08

H

DATA = 04

H

DATA = 02

H

DATA = 01

H

OP42

FREQUENCY – Hz

TPC 13. 50 kΩ Gain vs. Frequency vs. Code

0

DATA = 80

–6

–12

–18

–24

–30

GAIN – dB

–36

–42

–48

VDD = +2.7V
V

= –2.7V

SS

–54

V

= 100mV rms

A

T

= 25C

A

–60

1k 10k 100k 1M

V

A

H

DATA = 40

H

DATA = 20

H

DATA = 10

H

DATA = 08

H

DATA = 04

H

DATA = 02

H

DATA = 01

H

OP42

FREQUENCY – Hz

TPC 16. Normalized Gain Flatness vs. Frequency

(10mV/DIV)

W

V

REV. 0

TPC 14. 100 kΩ Gain vs. Frequency vs. Code

6

4

2

0

–2

–4

GAIN – dB

–6

–8

VDD = 2.7V

= 0V

V

–10

SS

V

= 100mV rms

A

–12

DATA = 80
TA = 25C

–14

1k 10k 100k 1M

2.7V

6

H

1.5V

100k

OP42

FREQUENCY – Hz

TPC 15. –3 dB Bandwidth

10k

50k

–7–

TPC 17. One Position Step Change at Half Scale

(50mV/DIV)V

OUT

V

(5mV/DIV)

IN

TPC 18. Large Signal Settling Time

AD5207

2500

2000

1500

(10mV/DIV)

W

V

TPC 19. Digital Feedthrough vs. Time

120

100

80

60

40

20

0

–20

POTENTIOMETER MODE TEMPCO – ppm/C

40

0

32 64 96 128 160 192 224 256

CODE – Decimal

TPC 20.∆VWB/∆T Potentiometer Mode
Temperature Coefficient

1000

500

0

RHEOSTAT MODE TEMPCO – ppm/C

500

32 64 96 128 160 192 224 256

0

CODE – Decimal

TPC 21.∆RWB/∆T Rheostat Mode Temperature Coefficient

100.0

I

192

WB_MAX

224

256

10.0

– mA

MAX

1.0

THEORETICAL I

0.1
032

64

96

CODE – Decimal

TPC 22. I

RAB = 10k

RAB = 50k

128

vs. Code

MAX

160

–8–

REV. 0

AD5207

OPERATION

The AD5207 provides a dual channel, 256-position digitally
controlled variable resistor (VR) device. The terms VR, RDAC,
and digital potentiometer are sometimes used interchangeably.
Changing the programmable VR settings is accomplished by
clocking in a 10-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is two address Bits, A1
and A0. With A1 and A2 are first and second bits respectively,
followed by eight data bits B7–B0 with MSB first. Table I pro­vides the serial register data word format. See Table III for the
AD5207 address assignments to decode the location of VR latch
receiving the serial register data in Bits B7 through B0. VR settings
can be changed one at a time in random sequence. The AD5207
presets to a midscale during power-on condition. AD5207 contains
a power shutdown SHDN pin. When activated in logic low.
Terminals A on both RDACs will be open-circuited while the
wiper terminals W

are shorted to BX. As a result, a minimum

X

amount of leakage current will be consumed in both RDACs,
and the power dissipation is negligible. During the shutdown
mode, the VR latch settings are maintained. Thus the previ­ous resistance values remain when the devices are resumed
from the shutdown.

DIGITAL INTERFACING

The AD5207 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), chip select (CS),
and serial data input (SDI). The positive edge-sensitive CLK
input requires clean transitions to avoid clocking incorrect data
into the serial input register. Standard logic families work well.
If mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig­ure 2 shows more detail of the internal digital circuitry. When CS
is low, the clock loads data into the serial register on each posi­tive clock edge; see Table II.

The serial-data-output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. The pull-up
resistor termination voltage may be larger than the V

supply

DD

of the AD5207 SDO output device, e.g., the AD5207 could
operate at V

= 3.3 V and the pull-up for interface to the next

DD

device could be set at 5 V. This allows for daisy chaining several
RDACs from a single processor serial-data line. The clock period
may need to be increased when using a pull-up resistor to the
SDI pin of the following devices in series. Capacitive loading at
the daisy chain node SDO–SDI between devices may add time
delay to subsequent devices. User should be aware of this poten­tial problem in order to successfully achieve data transfer. See
Figure 3. When configuring devices for daisy-chaining, the CS
should be kept low until all the bits of every package are clocked
into their respective serial registers, ensuring that the address bit
and data bits are in the proper decoding location. This requires
20 bits of address and data complying with the data word in
Table I if two AD5207 RDACs are daisy chained. During shut­down SHDN, the SDO output pin is forced to OFF (logic high
state) to disable power dissipation in the pull-up resistor. See
Figure 4 for equivalent SDO output circuit schematic.

+V

R

P

2k

AD5207

SDOSDI

CLKCS

C

AD5207

SDOSDI

CLKCS

Figure 3. Daisy-Chain Configuration Using SDO

CS

CLK

SDO

SDI

AD5207

A0

SER
REG

D7
D6
D5
D4
D3
D2
D1
D0

RDAC

LATCH

#1

EN

ADDR

DEC

RDAC

LATCH

#2

POWER-ON RESET

Figure 2. Block Diagram

SHDN

V

A1

W1

B1

A2

W2

B2

V

Table II. Input Logic Control Truth Table

DD

CLK CS SHDN Register Activity

L L H No SR effect, enables SDO pin.
P L H Shift one bit in from the SDI pin. MSB

first. The tenth previously entered bit
is shifted out of the SDO pin.

X P H Load SR data into RDAC latch based

on A0 decode (Table III).
X H H No Operation.
X H L Open circuits all resistor A Terminals,

connects W to B, turns off SDO out-

put transistor.

NOTE
P = positive edge, X = don’t care, SR = shift register.

SS

Table III. Address Decode Table

A1 A0 Latch Loaded

0 0 RDAC #1
0 1 RDAC #2

REV. 0

–9–

AD5207

SHDN

The data setup and data hold times in the specification table
determine the data valid time requirements. The last ten bits of
the data word entered into the serial register are held when CS
returns high and any extra bits are ignored. At the same time, when
CS goes high, it gates the address decoder enabling one of two
positive edge-triggered AD5207 RDAC latches; see Figure 5 detail.

CS

SDI

CLK

SERIAL

REGISTER

D

Q

CK

RS

INTERNAL

RS

SDO

Figure 4. Detail SDO Output Schematic of the AD5207

The target RDAC latch is loaded with the last eight bits of the
data word to complete one RDAC update. For AD5207, it
cannot update both channels simultaneously and therefore, two
separate 10-bit data words must be clocked in to change both
VR settings.

CS

CLK

SDI

AD5207

ADDR

DECODE

SERIAL

REGISTER

RDAC 1

RDAC 2

Figure 5. Equivalent Input Control Logic

All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figures 6 and 7. Applies
to digital input pins CS, SDI, SDO, SHDN, and CLK. Digital
input level for Logic 1 can be anywhere from 2.4 V to 5 V
regardless of whether it is in single or dual supplies.

DIGITAL PIN

340

V

SS

LOGIC

Figure 6. ESD Protection of Digital Pins

A,B,W

V

SS

SHDN

D7
D6
D5
D4
D3
D2
D1
D0

RDAC

LATCH

AND

DECODER

R

S

R

S

R

S

R

S

Ax

Wx

Bx

Figure 8. Equivalent RDAC Circuit

PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation

The nominal resistance of the RDAC between Terminals A and
B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ. The last
few digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 50 kΩ = 50; and 100 kΩ = 100. The
nominal resistance (R

) of the VR has 256 contact points

AB

accessed by the wiper terminal, plus the B Terminal contact.
The 8-bit data in the RDAC latch is decoded to select one of
the 256 possible settings. Assume a 10 kΩ part is used, the
wiper’s first connection starts at the B Terminal for data 00

.

H

Since there is a 45 Ω wiper contact resistance, such connection
yields a minimum of 45 Ω resistance between Terminals W and
B. The second connection is the first tap point corresponds to
84 Ω (R

= RAB/256 + RW = 39 Ω + 45 Ω) for data 01H. The

WB

third connection is the next tap point representing 123 Ω (39 ×
2 + 45) for data 02

and so on. Each LSB value increase moves

H

the wiper up the resistor ladder until the last tap point is reached at
10006 Ω (R

– 1 LSB + RW). Figure 8 shows a simplified dia-

AB

gram of the equivalent RDAC circuit.

The general equation determining the programmable output
resistance between W and B is:

RD

()

WB AB W

D

256

RR

=×+

where D is the data contained in the 8-bit RDAC latch, and R

(1)

AB

is the nominal end-to-end resistance.

For example, R
tied to W. The following output resistance R

=10 kΩ, A Terminal can be open-circuit or

AB

will be set for

WB

the following RDAC latch codes.

Figure 7. ESD Protection of Resistor Terminals

–10–

REV. 0

AD5207

Table IV.

DR

WB

(DEC) () Output State

255 10006 Full-Scale (R

– 1 LSB + RW)

AB

128 5045 Midscale
1841 LSB
0 45 Zero-Scale (Wiper Contact Resistance)

Note that in the zero-scale condition a finite wiper resistance of
45 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum current of no more
than 5 mA. Otherwise, degradation or possibly destruction of
the internal switch contacts can occur.

Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and Terminal A also produces a
digitally controlled resistance R

. When these terminals are used,

WA

the B Terminal should be let open or tied to the wiper terminal.
Setting the resistance value for R

starts at a maximum value

WA

of resistance and decreases as the data loaded in the latch is
increased in value. The general equation for this operation is:

D

256

RD

()

WA AB W

For example, when R

–

=×+

256

RR

= 10 kΩ, B terminal is either open or

AB

tied to W, the following output resistance, R

, will be set for

WA

(2)

the following RDAC latch codes.

position of the potentiometer divider. Since AD5207 is capable
for dual supplies, the general equation defining the output volt­age with respect to ground for any given input voltage applied to
terminals AB is:

VD

WA B

D

V

=+

()

256

256

256

D

−

V

(3)

Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent on the ratio of

and RWB and not the absolute values; therefore, the drift

R

WA

reduces to 15 ppm/°C. There is no voltage polarity constraint
between Terminals A, B, and W as long as the terminal voltage
stays within V

SS

< V

TERM

< VDD.

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Config­ured as a potentiometer divider the –3 dB bandwidth of the
AD5207BRU10 (10 kΩ resistor) measures 600 kHz at half
scale. TPC 16 provides the large signal BODE plot characteris­tics of the three available resistor versions 10 kΩ and 50 kΩ.
The gain flatness versus frequency graph, TPC 16, predicts
filter applications performance. A parasitic simulation model has
been developed and is shown in Figure 9. Listing I provides a
macro model net list for the 10 kΩ RDAC:

Table V.

DR

WA

(DEC) () Output State

255 84 Full-Scale (R

/256 + RW)

AB

128 5045 Midscale
1 10006 1 LSB
0 10045 Zero-Scale

The typical distribution of R

from channel to channel matches

AB

within ±1%. Device-to-device matching is process-lot depen­dent and is possible to have ±30% variation. The change in R

AB

with temperature has a 500 ppm/°C temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation

The digital potentiometer easily generates an output voltage
proportional to the input voltage. Let’s ignore the effect of
the wiper resistance for the moment. For example, when con­necting A Terminal to 5 V and B Terminal to ground, it produces
a programmable output voltage at the wiper starting at zero
volts up to 1 LSB less than 5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256

RDAC

A

C

10k

A

C

W

70pF

W

B

C

B

CB = 45pFCA = 45pF

Figure 9. RDAC Circuit Simulation Model for RDAC = 10 k

Listing I. Macro Model Net List for RDAC

.PARAM D=255, RDAC=10E3

*

.SUBCKT DPOT (A,W)

*

CA A 0 45E-12
RAW A W {(1-D/256)*RDAC+50}
CW W 0 70E-12
RBW W B {D/256*RDAC+50}
CB B 0 45E-12

*

.ENDS DPOT

Ω

REV. 0

–11–

AD5207

W

B

VSS TO V

DD

DUT

I

SW

CODE = 

H

R

SW

=

0.1V
I

SW

0.1V

+

–

TEST CIRCUITS

Figures 10 to 18 define the test conditions used in product
Specification table.

DUT

V+ = V

DD

1 LSB = V+/2

A

V+

W

B

N

V

MS

Figure 10. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)

NO CONNECT

DUT

A

B

W

I

W

V

MS

Figure 11. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)

DUT

V

MS2

A

W

B

V

W

IW = VDD/R

V

MS1

NOMINAL

5V

OFFSET

GND

V

IN

A DUT

OFFSET BIAS

OP279

W

B

V

OUT

Figure 15. Noninverting Gain Test Circuit

+15V

W

OP42

–15V

V

OUT

OFFSET

GND

A

V

DUT

IN

B

2.5V

Figure 16. Gain vs. Frequency Test Circuit

RW = [V

Figure 12. Wiper Resistance Test Circuit

V

A

V

DD

V+

A

W

B

V

MS

V+ = V

PSRR (dB) = 20 LOG

PSS (%/%) =

Figure 13. Power Supply Sensitivity Test Circuit

DD

MS1

10%

– V

MS2

VMS%
V

DD

]/I

W

Figure 17. Incremental ON Resistance Test Circuit

NC

V

DD

DUT

V

MS

V

DD

%

V

GND

SS

NC

NC = NO CONNECT

I

CM

A

W

B

V

CM

Figure 18. Common-Mode Leakage Current Test Circuit

(PSS, PSSR)

OFFSET

GND

V

IN

A DUT

B

W

OFFSET BIAS

OP279

5V

V

OUT

Figure 14. Inverting Gain Test Circuit

–12–

REV. 0

AD5207

DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE

Number Resolution Power
of VRs Terminal Interface Nominal (Number Supply

Part per Voltage Data Resistance of Wiper Current
Number Package Range Control (k⍀) Positions) (IDD) Packages Comments

AD5201 1 ± 3 V, +5.5 V 3-Wire 10, 50 33 40 µA µSOIC-10 Full AC Specs, Dual Supply,

Pwr-On-Reset, Low Cost

AD5220 1 5.5 V Up/Down 10, 50, 100 128 40 µA PDIP, SO-8, µSOIC-8 No Rollover, Pwr-On-Reset

AD7376 1 ± 15 V, +28 V 3-Wire 10, 50, 100, 1000 128 100 µA PDIP-14, SOL-16, Single +28 V or Dual ±15 V

TSSOP-14 Supply Operation

AD5200 1 ± 3 V, +5.5 V 3-Wire 10, 50 256 40 µA µSOIC-10 Full AC Specs, Dual Supply,

Pwr-On-Reset

AD8400 1 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA SO-8 Full AC Specs

AD5260 1 ± 5 V, +15 V 3-Wire 20, 50, 200 256 60 µA TSSOP-14 15 V or ± 5 V,

TC < 50 ppm/°C

AD5241 1 ± 3 V, +5.5 V 2-Wire 10, 100, 1000 256 50 µA SO-14, TSSOP-14 I2C-Compatible, TC

< 50 ppm/°C

AD5231* 1 ± 3 V, +5.5 V 3-Wire 10, 50, 100 1024 20 µA TSSOP-16 Nonvolatile Memory, Direct

Program, I/D, ± 6 dB Settability

AD5222 2 ± 3 V, +5.5 V Up/Down 10, 50, 100, 1000 128 80 µA SO-14, TSSOP-14 No Rollover, Stereo, Pwr-On-

Reset, TC < 50 ppm/°C

AD8402 2 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SO-14, Full AC Specs, nA

TSSOP-14 Shutdown Current

AD5207 2 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 40 µA TSSOP-14 Full AC specs, Dual Supply,

Pwr-On-Reset, SDO

AD5232* 2 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 20 µA TSSOP-16 Nonvolatile Memory, Direct

Program, I/D, ±6 dB Settability

AD5235* 2 ± 3 V, +5.5 V 3-Wire 25, 250 1024 20 µA TSSOP-16 Nonvolatile Memory, Direct

Program, TC < 50 ppm/°C

AD5242 2 ± 3 V, +5.5 V 2-Wire 10, 100, 1000 256 50 µA SO-16, TSSOP-16 I2C-Compatible, TC

< 50 ppm/°C

AD5262* 2 ± 5 V, +15 V 3-Wire 20, 50, 200 256 60 µA TSSOP-16 ± 15 V or ± 5 V, Pwr-On-

Reset, TC < 50 ppm/°C

AD5203 4 5.5 V 3-Wire 10, 100 64 5 µA PDIP, SOL-24, Full AC Specs, nA

TSSOP-24 Shutdown Current

AD5233* 4 ± 3 V, +5.5 V 3-Wire 10, 50, 100 64 20 µA TSSOP-16 Nonvolatile Memory, Direct

Program, I/D, ± 6 dB Settability

AD5204 4 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 60 µA PDIP, SOL-24, Full AC Specs, Dual Supply,

TSSOP-24 Pwr-On-Reset

AD8403 4 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, nA

TSSOP-24 Shutdown Current

AD5206 6 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 60 µA PDIP, SOL-24, Full AC Specs, Dual Supply,

TSSOP-24 Pwr-On-Reset

*Future product, consult factory for latest status.
Latest Digital Potentiometer Information available at www.analog.com/support/standard_linear/selection_guides/dig_pot.html

REV. 0

–13–

AD5207

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm)

14-Lead TSSOP

(RU-14)

0.201 (5.10)

0.193 (4.90)

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

14

0.0256
(0.65)

BSC

8

71

0.0433 (1.10)
MAX

0.0118 (0.30)

0.0075 (0.19)

0.177 (4.50)

0.169 (4.30)

0.256 (6.50)

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

8



0



0.028 (0.70)

0.020 (0.50)

–14–

REV. 0

–15–

C01885–1.5–4/01(0)

–16–

PRINTED IN U.S.A.