Datasheet AD5206 Datasheet (ANALOG DEVICES)

4-/6-Channel

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FEATURES

256 positions Multiple independently programmable channels

AD5204—4-channel

AD5206—6-channel Potentiometer replacement Terminal resistance of 10 kΩ, 50 kΩ, 100 kΩ 3-wire SPI-compatible serial data input +2.7 V to +5.5 V single-supply operation; ±2.7 V dual-supply

oper

ation

Power-on midscale preset

APPLICATIONS

Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, time constants Line impedance matching

GENERAL DESCRIPTION

The AD5204/AD5206 provides 4-/6-channel, 256-position digitally controlled variable resistor (VR) devices. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5204/AD5206 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 10 k, 50 k, or 100 k has a nominal temperature coefficient of 700 ppm/°C.

Each VR has its own VR latch that holds its programmed re

sistance value. These VR latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eleven data bits make up the data-word clocked into the serial input register. The first three bits are decoded to determine which VR latch will be loaded with the last eight bits of the data-word when the strobe is returned to logic high. A serial data output pin at the opposite end of the serial register (AD5204 only) allows simple daisy chaining in multiple VR applications without requiring additional external decoding logic.

CS

Digital Potentiometers

AD5204/AD5206

FUNCTIONAL BLOCK DIAGRAMS

D7

D0

D7

D0

AD5204

RDAC

LATCH

#1

R

RDAC

LATCH

#4

R

CS

CLK

SDO

SDI

GND

A2 A1 A0

DO

D7

SER REG

DI

D0

POWER-ON

PRESET

EN

ADDR

DEC

8

Figure 1.

D7

D0

D7

D0

AD5206

RDAC

LATCH

#1

R

RDAC

LATCH

#6

R

CS

CLK

SDI

GND

A2 A1 A0

D7

SER REG

DI

D0

POWER-ON

PRESET

EN

ADDR

DEC

8

Figure 2.

An optional reset (PR) pin forces all the AD5204 wipers to the midscale position by loading 0x80 into the VR latch.

The AD5204/AD5206 is available in the 24-lead surface-mount

IC, TSSOP, and PDIP packages. The AD5204 is also available in

SO a 32-lead, 5 mm × 5 mm LFCSP package. All parts are guaranteed to operate over the extended industrial temperature range of

−40°C to +85°C. For additional single-, dual-, and quad-channel devices, see the

AD8400/AD8402/AD8403 data sheets.

V

DD

A1

W1

B1

A4

W4

B4

SHDN

V

SS

PR

V

DD

A1

W1

B1

A6

W6

B6

V

SS

6884-001

06884-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5204/AD5206

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REVISION HISTORY

11/07—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Added 32-Lead LFCSP Package........................................Universal

Changed R

Changes to Absolute Maximum Ratings....................................... 6

Changes to Operation Section ...................................................... 12

Updated Outline Dimensions....................................................... 17

Changes to Ordering Guide.......................................................... 18

9/99—Revision 0: Initial Version

to RAB.............................................................Universal

BA

Pin Configurations and Function Descriptions............................7

Typical Performance Characteristics........................................... 10

Operation......................................................................................... 12

Programming the Variable Resistor............................................. 13

Rheostat Operation.................................................................... 13

Programming the Potentiometer Divider................................... 14

Voltage Output Operation......................................................... 14

Digital Interfacing .......................................................................... 15

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 18

Rev. A | Page 2 of 20

AD5204/AD5206

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 5 V ± 10% or 3 V ± 10%, VSS = 0 V, VA = +VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential NL Resistor Nonlinearity Error Nominal Resistor Tolerance

3

4

2

R-DNL RWB, VA = no connect −1 ±1/4 +1 LSB R-INL RWB, VA = no connect −2 ±1/2 +2 LSB ΔRAB TA = 25°C −30 +30 %

1

Max Unit

Resistance Temperature Coefficient ΔRAB/ΔT VAB = VDD, wiper = no connect 700 ppm/°C Nominal Resistance Match ΔR/RAB

Channel 1 to Channel 2, Channel 3, and Channel V

4, or to Channel 5 and Channel 6;

= VDD

AB

0.25 1.5 %

Wiper Resistance RW IW = 1 V/R, VDD = 5 V 50 100 Ω

DC CHARACTERISTICS POTENTIOMETER

DIVIDER MODE

2

Resolution N 8 Bits Differential Nonlinearity Integral Nonlinearity Voltage Divider Temperature

5

DNL −1 ±1/4 +1 LSB INL −2 ±1/2 +2 LSB ΔV

/ΔT Code = 0x40 15 ppm/°C

W

Coefficient Full-Scale Error V Zero-Scale Error V

Code = 0x7F −2 −1 0 LSB

WFSE

Code = 0x00 0 +1 +2 LSB

WZSE

RESISTOR TERMINALS

Voltage Range Capacitance7 Ax, Bx CA, CB

Capacitance7 Wx CW

Shutdown Current

6

8

VA, VB, VW VSS VDD V

f = 1 MHz, measured to GND,

ode = 0x40

c f = 1 MHz, measured to GND,

ode = 0x40

c

I

0.01 5 μA

A_SD

45 pF

60 pF

Common-Mode Leakage ICM VA = VB = VW = 0, VDD = +2.7 V, VSS = −2.5 V 1 nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH VDD = 5 V/3 V 2.4/2.1 V Input Logic Low VIL VDD = 5 V/3 V 0.8/0.6 V Output Logic High VOH R Output Logic Low VOL IOL = 1.6 mA, V

= 1 kΩ to 5 V 4.9 V

PULL–UP

= 5 V 0.4 V

LOGI C

Input Current IIL VIN = 0 V or 5 V ±1 μA Input Capacitance

7

CIL 5 pF

POWER SUPPLIES

Power Single-Supply Range VDD range VSS = 0 V 2.7 5.5 V Power Dual-Supply Range

V

DD/VSS

±2.3 ±2.7 V

range Positive Supply Current IDD VIH = 5 V or VIL = 0 V 12 60 μA Negative Supply Current ISS VSS = –2.5 V, VDD = +2.7 V 12 60 μA Power Dissipation

9

P

VIH = 5 V or VIL = 0 V 0.3 mW

DISS

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% 0.0002 0.005 %/%

DYNAMIC CHARACTERISTICS

7, 10

Bandwidth –3 dB BW_10K RAB = 10 kΩ 721 kHz BW_50K RAB = 50 kΩ 137 kHz BW_100K RAB = 100 kΩ 69 kHz

Rev. A | Page 3 of 20

AD5204/AD5206

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Parameter Symbol Conditions Min Typ

1

Max Unit

Total Harmonic Distortion THDW VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz 0.004 %

t

VW Settling Time

VA = 5 V, VB = 0 V, ±1 LSB error band 2/9/18 μs

S

(10 kΩ/50 kΩ/100 kΩ)

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS

7, 11 , 12

N_WB

= 5 kΩ , f = 1 kHz, PR = 0

R

WB

9 nV/√Hz

Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns Data Setup Time tDS 5 ns Data Hold Time tDH 5 ns CLK-to-SDO Propagation Delay CS Setup Time CS High Pulse Width

13

tPD RL = 2 kΩ , CL < 20 pF 1 150 ns t

15 ns

CSS

t

40 ns

CSW

Reset Pulse Width tRS 90 ns

t

CLK Fall to CS Fall Setup CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Applies to all VRs.

3

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28. IW = VDD/R for both VDD = 3 V and VDD = 5 V.

4

VAB = VDD, wiper (VW) = no connect.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 27.

6

Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.

7

Guaranteed by design and not subject to production test.

8

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

9

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

10

All dynamic characteristics use VDD = 5 V.

11

Applies to all parts.

12

See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)

and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.

13

The propagation delay depends on the values of VDD, RL, and CL (see the Operation section).

0 ns

CSH0

t

0 ns

CSH1

t

10 ns

CS1

Rev. A | Page 4 of 20

AD5204/AD5206

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TIMING DIAGRAMS

1

SDI

CLK

CS

V

OUT

(DATA IN)

(DATA OUT)

V

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

V

DD

0V

RDAC LATCH LOAD

Figure 3. Timing Diagram

1

SDI

SDO

CLK

CS

OUT

Ax OR Dx Ax OR Dx

0

1

Ax OR Dx Ax OR Dx

0

1

0

t

CSH0

1

0

V

DD

0V

t

DS

t

CH

t

CSS

Figure 4. Detailed Timing Diagram

1

PR

0

V

DD

V

OUT

0V

±1 LSB ERROR BAND

Figure 5. AD5204 Preset Timing Diagram

t

DH

CL

±1 LSB ER ROR BAND

t

RS

t

S

t

PD_MAX

t

CS1

t

±1LSB

CSH1

t

06884-003

t

CSW

S

±1 LSB

06884-004

6884-005

Rev. A | Page 5 of 20

AD5204/AD5206

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

VDD to GND −0.3 V to +7 V VSS to GND 0 V to −7 V VDD to VSS 7 V VA, VB, VW to GND VSS, VDD Ax – Bx, Ax – Wx, Bx – Wx ±20 mA Digital Input and Output Voltage to GND 0 V to +7 V Operating Temperature Range −40°C to +85°C Maximum Junction Temperature (TJ max) 150°C Storage Temperature –65°C to +150°C Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (TJ max – TA)/θJA Thermal Resistance, θ

PDIP (N-24-1) 63°C/W

SOIC (RW-24) 52°C/W

TSSOP (RU-24) 50°C/W

LFCSP (CP-32-3) 32.5°C/W

1

Thermal resistance (JEDEC 4-layer (2S2P) board). Paddle soldered to board.

1

JA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 20

AD5204/AD5206

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

NC

2

GND

3

CS

4

AD5204

5

PR

V

SHDN

SDI

CLK

SDO

V

NC

DD

SS

TOP VIEW

6

(Not to Scale)

7

8

9

10

11

12

NC = NO CONNECT

Figure 6. AD5204 SOIC/TSSOP/PDIP Pin Configuration

Table 3. AD5204 Pin Function Descriptions

Pin No. Name Description

1, 2, 12 NC Not Connected. 3 GND Ground. 4

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based

CS

on the address bits, and then it is loaded into the target RDAC latch.

5

PR

6 VDD

7

SHDN

Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80. Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. (It is the sum of

| + |VSS| < 5.5 V.)

|V

DD

Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4. 8 SDI Serial Data Input. Data is input MSB first. 9 CLK Serial Clock Input. This pin is positive edge triggered. 10 SDO Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor. 11 VSS

Negative Power Supply. This pin is specified for operati

| + |VSS| < 5.5 V.)

|V

DD

13 B3 B Terminal RDAC 3. 14 W3 Wiper RDAC 3. Address = 0102.

15 A3 A Terminal RDAC 3. 16 B1 B Terminal RDAC 1. 17 W1 Wiper RDAC 1. Address = 0002. 18 A1 A Terminal RDAC 1. 19 A2 A Terminal RDAC 2. 20 W2 Wiper RDAC 2. Address = 0012. 21 B2 B Terminal RDAC 2. 22 A4 A Terminal RDAC 4. 23 W4 Wiper RDAC 4. Address = 0112.

24 B4 B Terminal RDAC 4.

B4

24

W4

23

A4

22

21

B2

20

W2

19

A2

A1

18

W1

17

B1

16

A3

15

14

W3

13

B3

06884-006

on at both 0 V and –2.7 V. (It is the sum of

Rev. A | Page 7 of 20

AD5204/AD5206

V

www.BDTIC.com/ADI

DD

CLK

SDI

SHDNPRCS

AD5204

TOP VIEW

(Not to Scale)

B1W1A1

V

A2

W2

GND

24

NC

23

NC

22

NC

21

NC

B4

20

19

W4

A4

18

NC

17

B2

NC

06884-053

SDO

32 31 30 29 28 27 26 25

1

S

NC

B3

W3

A3

PIN 1

2

INDICATO R

3

4

5

6

7

8

9 10 11 12 13 14 15 16

NC

NC = NO CONNECT

Figure 7. AD5204 LFCSP Pin Configuration

Table 4. AD5204 LFCSP Pin Function Descriptions

Pin No. Name Description

1 VSS Negative Power Supply. This pin is specified for operation at both 0 V and –2.7 V. (It is the sum of |VDD| + |VSS| < 5.5 V.) 2 to 5, 9,

NC Not Connected. 16, 17, 21 to 24

6 B3 B Terminal RDAC 3. 7 W3 Wiper RDAC 3. Address = 0102. 8 A3 A Terminal RDAC 3. 10 B1 B Terminal RDAC 1. 11 W1 Wiper RDAC 1. Address = 0002. 12 A1 A Terminal RDAC 1. 13 A2 A Terminal RDAC 2.

14 W2 Wiper RDAC 2. Address = 0012. 15 B2 B Terminal RDAC 2.

18 A4 A Terminal RDAC 4. 19 W4 Wiper RDAC 4. Address = 0112. 20 B4 B Terminal RDAC 4. 25 GND Ground. 26

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on

CS

the address bits, and then it is loaded into the target RDAC latch.

27

PR

Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80.

28 VDD Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. (It is the sum of |VDD| + |VSS| < 5.5 V.) 29

SHDN

Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4.

30 SDI Serial Data Input. Data is input MSB first. 31 CLK Serial Clock Input. This pin is positive edge triggered. 32 SDO Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.

Rev. A | Page 8 of 20

AD5204/AD5206

www.BDTIC.com/ADI

1

A6

W6

2

B6

3

GND

4

AD5206

5

CS

V

SDI

CLK

V

B5

W5

A5

DD

SS

TOP VIEW

6

(Not to S cale)

7

8

9

10

11

12

NC = NO CONNECT

Figure 8. AD5206 SOIC/TSSOP/PDIP Pin Configuration

Table 5. AD5206 Pin Function Descriptions

Pin No.

Name Description

1 A6 A Terminal RDAC 6. 2 W6 Wiper RDAC 6. Address = 1012. 3 B6 B Terminal RDAC 6.

4 GND Ground. 5

CS

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the

address bits, and then it is loaded into the target RDAC latch. 6 VDD Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. (It is the sum of |VDD| + |VSS| < 5.5 V.) 7 SDI Serial Data Input. Data is input MSB first.

8 CLK Serial Clock Input. This pin is positive edge triggered. 9 VSS Negative Power Supply. This pin is specified for operation at both 0 V and –2.7 V. (It is the sum of |VDD| + |VSS| < 5.5 V.) 10 B5 B Terminal RDAC 5. 11 W5 Wiper RDAC 5. Address = 1002. 12 A5 A Terminal RDAC 5. 13 B3 B Terminal RDAC 3. 14 W3 Wiper RDAC 3. Address = 0102. 15 A3 A Terminal RDAC 3. 16 B1 B Terminal RDAC 1. 17 W1 Wiper RDAC 1. Address = 0002. 18 A1 A Terminal RDAC 1. 19 A2 A Terminal RDAC 2. 20 W2 Wiper RDAC 2. Address = 0012.

21 B2 B Terminal RDAC 2. 22 A4 A Terminal RDAC 4. 23 W4 Wiper RDAC 4. Address = 0112. 24 B4 B Terminal RDAC 4.

B4

24

W4

23

A4

22

21

B2

20

W2

19

A2

A1

18

W1

17

B1

16

A3

15

14

W3

13

B3

06884-019

Rev. A | Page 9 of 20

AD5204/AD5206

–

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TYPICAL PERFORMANCE CHARACTERISTICS

120

110

100

90

80

70

VDD/VSS= ±2.7V

60

SWITCH RESI STANCE (Ω)

50

40

30

–3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 6.0

V

DD/VSS

= 2.7V/0V

COMMON MODE (V)

VDD/VSS= 5.5V/0V

0

VDD = ±2.7V

–2

V

= –2.7V

SS

V

= 100mV rms

A

–4

DATA =

0x80

V

A

NORMALIZED GAIN (dB)

1k 10k 100k 1M

06884-007

OP42

FREQUENCY (Hz)

100kΩ

10kΩ

50kΩ

06884-010

Figure 9. Incremental On Resistance of the Wiper vs. Voltage

5.99

–6.00

–6.01

–6.02

–6.03

V

= 2.7V

DD

V

= –2.7V

SS

V

= 100mV rms

A

DATA = 0x80 T

= 25°C

A

V

A

OP42

V

= 0V

B

100 1k 10k 100k

100kΩ

FREQUENCY (Hz)

GAIN (dB)

–6.04

–6.05

–6.06

–6.07

–6.08

–6.09

50kΩ

Figure 10. Gain Flatness vs. Frequency

0

V

= 2.7V

–2

DD

= 0V

V

SS

= 100mV rms

V

–4

A

0x80

DATA =

= 25°C

T

A

2.7V

NORMALIZ ED GAIN (dB)

+1.5V

1k 10k 100k 1M

OP42

FREQUENCY (Hz)

10kΩ

100kΩ

Figure 11. −3 dB Bandwidth vs. Terminal Resistance,

2.7 V Single-Supply Operation

50kΩ

10kΩ

Figure 12. −3 dB Bandwidth vs. Terminal Resistance,

7 V Dual-Supply Operation

±2.

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

6884-008

6884-009

1k 10k 100k 1M

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 10k 100k 1M

DATA = 0x80

DATA = 0x40

DATA = 0x20

DATA = 0x10

DATA = 0x08

DATA = 0x04

DATA = 0x02

DATA = 0x01

VDD = 2.7V

= –2.7V

V

SS

= 100mV rms

V

A

= 25°C

T

A

V

A

OP42

FREQUENCY (Hz)

Figure 13. Bandwidth vs. Code, 10

DATA = 0x80

DATA = 0x40

DATA = 0x20

DATA = 0x10

DATA = 0x08

DATA = 0x04

DATA = 0x02

DATA = 0x01

VDD = 2.7V V

= –2.7V

SS

V

= 100mV rms

A

T

= 25°C

A

V

A

OP42

FREQUENCY (Hz)

Figure 14. Bandwidth vs. Code, 50

kΩ Version

06884-011

06884-012

Rev. A | Page 10 of 20

AD5204/AD5206

www.BDTIC.com/ADI

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 10k 100k 1M

VDD = 2.7V V

= –2.7V

SS

V

= 100mV rms

A

T

= 25°C

A

DATA = 0x80

DATA = 0x40

DATA = 0x20

DATA = 0x10

DATA = 0x08

DATA = 0x04

DATA = 0x02

DATA = 0x01

V

A

OP42

FREQUENCY (Hz)

06884-013

8

TA = 25°C

7

6

5

I

4

3

SUPPLY CURRENT (mA)

I

2

I

DD

I

, VDD/VSS = ±2.7V/0V, DATA = 0x55

DD

1

0

10k 100k 1M 10M

IDD, VDD/VSS = 5.5V/0V, DATA =

, VDD/VSS = ±2.7V, DATA = 0x 55

SS

, VDD/VSS = 5V/0V, DATA = 0xFF

I

DD

, VDD/VSS = ±2.7V, DATA = 0x FF

SS

, VDD/VSS = 2.7V/0V, DATA = 0xFF

FREQUENCY (Hz)

0x55

06884-016

Figure 15. Bandwidth vs. Code, 100 kΩ Version Figure 18. Supply Current vs. Clock Frequency

TRIP POINT (V)

2.5

2.0

1.5

SINGLE SUPPLY V

DD

1.0

= V

SS

DUAL SUPPLY

VSS= 0V

60

50

VDD= 5.0V ± 10%

40

30

PSRR (dB)

20

VDD = 3.0V ± 10%

TA = 25°C

VSS = –3.0V ± 10%

0.5

0

123456

SUPPLY VOLTAGE VDD (V)

Figure 16. Digital Input Trip Point vs. Supply Voltage

100

ISS AT VDD/VSS = ±2.7V

10

1

I

AT VDD/VSS = ±2.7V

0.1

SUPPLY CURRENT (mA)

0.01

0.001 0123456

DD

I

AT VDD/VSS = 2.7V/0V

DD

INCREMENTAL INPUT LO GIC VOL TAGE (V)

IDD AT VDD/VSS = 5.5V/0V

TA = 25°C

Figure 17. Supply Current vs. Input Logic Voltage

10

0

10 100 1k 10k 100k

06884-014

Figure 19. Power Supply Reje

1

VDD = +2.7V

= –2.7V

V

SS

= 25°C

T

A

= 10kΩ

R

AB

0.1

0.01 NONINVERTI NG TEST CIRCUIT

THD + NOISE ( %)

0.001 INVERTING TEST CIRCUIT

0.0001

10 100 1k 10k 100k

06884-015

FREQUENCY (Hz)

ction vs. Frequency

FREQUENCY (Hz)

06884-017

6884-018

Figure 20. Total Harmonic Distortion Plus Noise vs. Frequency

Rev. A | Page 11 of 20

AD5204/AD5206

S

www.BDTIC.com/ADI

OPERATION

The AD5204 provides a 4-channel, 256-position digitally controlled VR device, and the AD5206 provides a 6-channel, 256-position digitally controlled VR device. Changing the programmed VR settings is accomplished by clocking in an 11-bit serial data-word into the SDI pin. The format of this data-word is three address bits, MSB first, followed by eight data bits, MSB first.

Tabl e 6 provides the serial register data-word format.

Table 6. Serial Data-Word Format

Address Data

B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB

210 28 27 20

See Tab le 1 0 for the AD5204/AD5206 address assignments to decode the location of the VR latch receiving the serial register data in Bit B7 through Bit B0. The VR outputs can be changed one at a time in random sequence. The AD5204 presets to midscale by asserting the

PR

pin, simplifying fault condition recovery at power up. Both parts have an internal power-on preset that places the wiper in a preset midscale condition at power on. In addition, the AD5204 contains a power shutdown pin

SHDN

(

) that places the RDAC in a zero power consumption

state, where Terminals Ax are open circuited and Wipers Wx are connected to Terminals Bx, resulting in only leakage currents being consumed in the VR structure. In shutdown mode, the VR latch settings are maintained so that the VR settings return to their previous resistance values when the device is returned to operational mode from power shutdown.

R

HDN

D7 D6 D5 D4 D3 D2 D1 D0

RDAC

LATCH

AND

DECODER

Figure 21. AD5204/AD5206 Equivalent RDAC Circuit

S

R

S

R

S

R

S

Ax

Wx

Bx

06884-044

Rev. A | Page 12 of 20

AD5204/AD5206

www.BDTIC.com/ADI

PROGRAMMING THE VARIABLE RESISTOR

RHEOSTAT OPERATION

The nominal resistance of the RDAC between Terminal A and Terminal B is available with values of 10 k, 50 k, and 100 k. The last digits of the part number determine the nominal resistance value, for example, 10 k = 10 and 100 k = 100. The nominal resistance (R accessed by the wiper terminal, plus the B terminal contact. The 8-bit data-word in the RDAC latch is decoded to select one of the 256 possible settings. The wiper’s first connection starts at the B terminal for Data 0x00. This B terminal connection has a wiper contact resistance of 45 . The second connection (for a 10 k part) is the first tap point, located at 84  [= R resistance)/256 + R

W

connection is the next tap point, representing 78 + 45 = 123  for Data 0x02. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10006 . The wiper does not directly connect to the A terminal. See Figure 21 for a simplified diagram of the equivalent RDAC circuit.

The general transfer equation determining the digitally p

rogrammed output resistance between Wx and Bx is

(Dx) = (Dx)/256 × RAB + RW (1)

R

WB

where Dx is t R

is the nominal end-to-end resistance.

AB

For example, when V

he data contained in the 8-bit RDACx latch, and

B

the output resistance values are set as outlined in Tabl e 7 for the R

DAC latch codes (applies to the 10 kΩ potentiometer).

Table 7. Output Resistance Val

= 0 V and Terminal A = Open Circuited

V

B

D (Dec) RWB (Ω) Output State

255 10006 Full scale 128 5045 1 84 1 LSB

0 45 Zero scale (wiper contact resistance)

) of the VR has 256 contact points

AB

(nominal

AB

= 84  + 45 ] for Data 0x01. The third

= 0 V and the A terminal is open circuited,

ues for the RDAC Latch Codes—

Midscale (PR

= 0 condition)

Note that in the zero-scale condition, a finite wiper resistance of 45  is p

resent. Care should be taken to limit the current flow between Wiper W and Terminal B in this state to a maximum value of 20 mA to avoid degradation or possible destruction of the internal switch contact.

Like the mechanical potentiometer that the RDAC replaces, t

he RDAC is completely symmetrical. The resistance between Wiper W and Terminal A produces a digitally controlled resistance, R should be tied to the wiper. Setting the resistance value for R

. When these terminals are used, the B terminal

WA

starts at a maximum value of resistance and decreases as the data loaded to the latch is increased in value. The general transfer equation for this operation is

R

(Dx) = (256 – Dx)/256 × RAB + R

WA

where Dx is t R

is the nominal end-to-end resistance.

AB

For example, when V

he data contained in the 8-bit RDACx latch, and

= 0 V and Terminal B is tied to Wiper W,

A

W

(2)

the output resistance values outlined in Ta b le 8 are set for the

AC latch codes:

RD

Table 8. Output Resistance Values for the RDAC Latch Codes—

= 0 V and Terminal B Tied to Wiper W

V

A

D (DEC) RWA (Ω) Output State

255 84 Full scale 128 5045 1 10006 1 LSB

0 10045 Zero scale

Midscale (PR

= 0 condition)

The typical distribution of RAB from channel to channel matches to within ±1%. However, device-to-device matching is process lot dependent, having a ±30% variation. The change in R

in

AB

terms of temperature has a 700 ppm/°C temperature coefficient.

Rev. A | Page 13 of 20

AD5204/AD5206

www.BDTIC.com/ADI

PROGRAMMING THE POTENTIOMETER DIVIDER

VOLTAGE OUTPUT OPERATION

The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper that can be any value from 0 V up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B divided by the 256-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to Terminal A and Terminal B is

(Dx) = Dx/256 × VAB + VB (3)

V

W

Operation of the digital potentiometer in the divider mode re

sults in more accurate operation over temperature. In this mode, the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to 15 ppm/°C.

CS

CLK

SDO*

SDI

SHDN*

DO

SER REG

DI

DGND

EN

A2

ADDR

DEC

A1 A0 D7

D0

8

PR

Figure 22. Block Diagram

D7

RDAC

LATCH

#1

D0

R

AD5204/AD5206

D7

RDAC

LATCH

#4/#6

D0

R

*AD5204 ONLY

V

DD

A1

W1

B1

A4/A6

W4/W6

B4/B6

06884-047

Rev. A | Page 14 of 20

AD5204/AD5206

A

www.BDTIC.com/ADI

DIGITAL INTERFACING

The AD5204/AD5206 each contain a standard 3-wire serial input control interface. The three inputs are clock (CLK), chip select input (

CS

), and serial data input (SDI). The positiveedge-sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or by other suitable means. in

ternal digital circuitry. When

Figure 22 shows more detail of the

CS

is taken active low, the clock loads data into the serial register on each positive clock edge (see

Tabl e 9). When using a positive (V

) and negative (VSS)

DD

supply voltage, the logic levels are still referenced to digital ground (GND).

The serial data output (SDO) pin contains an open-drain n-channel

FET. This output requires a pull-up resistor to transfer data to the SDI pin of the next package. The pull-up resistor termination voltage can be larger than the V AD5204. For example, the AD5204 can operate at V

supply of the

DD

= 3.3 V, and the pull-up for the interface to the next device can be set at 5 V. This allows for daisy chaining several RDACs from a single-processor serial data line.

If a pull-up resistor is used to connect the SDI pin of the

ext device in the series, the clock period must be increased.

n Capacitive loading at the daisy-chain node (where SDO and SDI are connected) between the devices must be accounted for to successfully transfer data. When daisy chaining is used, the CS

should be kept low until all the bits of every package are clocked into their respective serial registers, ensuring that the address bits and data bits are in the proper decoding locations. This requires 22 bits of address and data complying to the dataword format outlined in

re daisy-chained. During shutdown (

a

Table 6 if two AD5204 4-channel RDACs

SHDN

), the SDO output pin is forced to the off (logic high state) position to disable power dissipation in the pull-up resistor. See

O output circuit schematic.

SD

Table 9. Input Logic Control Truth Table

CLK

CS

PR SHDN

Register Activity

Figure 24 for the equivalent

1

L L H H No SR effect; enables SDO pin. P L H H

Shift one bit in from the SDI pin. The

th

bit that was previously entered is

11 shifted out of the SDO pin.

X P H H

Load SR data into the RDAC latch

ed on A2, A1, A0 decode (Tabl e 10).

bas X H H H No operation. X X L H

Sets all RDAC latches to midscale;

entered and SDO latch

wiper c

cleared. X H P H Latches all RDAC latches to 0x80. X H H L

Open circuits all A resistor terminals,

onnects Wiper W to Terminal B,

c

turns off the SDO output transistor.

1

P = positive edge, X = don’t care, SR = shift register.

Rev. A | Page 15 of 20

Table 10. Address Decode Table

A2 A1 A0 Latch Decoded

0 0 0 RDAC 1 0 0 1 RDAC 2 0 1 0 0 1 1 1 0 0

RDAC 3 RDAC 4 RDAC 5 AD5206 only

1 0 1 RDAC 6 AD5206 only

The data setup and data hold times in the specification table determine the data valid time requirements. The last 11 bits of the data-word entered into the serial register are held when

returns high. When

CS

goes high, the address decoder is gated,

CS

enabling one of four or six positive-edge-triggered RDAC latches (see Figure 23 for details).

D5204/AD5206

CS

CLK

SDI

Figure 23. Equivalent Input Control Logic

ADDR

DECODE

SERIAL

REGISTER

RDAC 1 RDAC 2

RDAC 4/ RDAC 6

06884-048

The target RDAC latch is loaded with the last eight bits of the serial data-word, completing one DAC update. Four separate 8-bit data-words must be clocked in to change all four VR settings.

SHDN

CS

SERIAL

SDI

REGISTER

CLK

PR

Figure 24. Detail SDO Output Sc

D

CK RS

Q

All digital pins (CS, SDI, SDO, PR,

hematic of the AD5204

SHDN

, and CLK) are

SDO

GND

06884-049

protected with a series input resistor and a parallel Zener ESD structure (see Figure 25).

AD5204/AD5206

V

A

V

A

O

V

www.BDTIC.com/ADI

A

V

340kΩ

LOGIC

V

SS

06884-050

Figure 25. ESD Protection of Digital Pins

A, B, W

V

SS

06884-051

Figure 26. ESD Protection of Resistor Terminals

DUT

A

V+

W

B

V+ = V

DD

1LSB = V+/ 256

V

MS

06884-036

Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)

DD

V+

~

W

B

V

MS

Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)

V

OFFSET

GND

IN

OFFSET BIAS

Figure 31. Inverting Programmable Gain Test Circuit

V

IN

OFFSET

GND

OFFSET BIAS

Figure 32. Noninverting Programmable Gain Test Circuit

DUT

W

A

DUT

V+ = VDD ± 10%

PSRR (dB) = 20 log

PSS (%/%) =

B

W

5V

OP279

5

OP279

B

ΔV

MS

DD

V

OUT

V

OUT

ΔV

( )

ΔV

%

06884-041

MS

DD

6884-039

6884-040

NO CONNECT

DUT

A

W

B

Figure 28. Resistor Position Nonlinearity Error

stat Operation; R-INL, R-DNL)

(Rheo

I

MS

V+

DUT

A

B

I

=

1V/R

W

NOMI NAL

V

W

V

MS

Figure 29. Wiper Resistance Test Circuit

I

W

V

MS

V+ V

DD

V

W2

RW =

WHERE V

W1

= VMS WHEN IW = 1/R

AND V

W2

06884-037

– [VW1 + IW(RAWII RBW)]

I

W

= VMS WHEN IW = 0

V

IN

DUT

FFSET

GND

B

2.5V

Figure 33. Gain vs. Frequency Test Circuit

DUT

W

B

I

SW

V

SS

6884-052

Figure 34. Incremental On-Resistance Test Circuit

W

RSW=

CODE =

TO V

DD

+15V

OP42

–15V

0.1 I

SW

0x00

V

OUT

6884-042

+

0.1V

–

06884-043

Rev. A | Page 16 of 20

AD5204/AD5206

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

1.280 (32.51)

1.250 (31.75)

1.230 (31.24)

0.210 (5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

MAX

24

1

0.100 (2.54) BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

13

12

0.280 (7. 11)

0.250 (6.35)

0.240 (6.10)

0.015 (0.38) MIN

SEATING PLANE

0.005 (0.13) MIN

0.060 (1.52) MAX

0.015 (0.38) GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92) MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

CONTROLL ING DIMENS IONS ARE IN INCHES; MILLIMETE R DIMENSIO NS (IN PARENTHESES) ARE ROUNDED-O FF INCH EQ UIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN. CORNER LEADS M AY BE CONFIGURED AS WHOLE O R HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-001

071006-A

Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP]

Nar

row Body

(N-24-1)

Dimensions shown in inches and (millimeters)

15.60 (0.6142)

15.20 (0.5984)

13

7.60 (0.2992)

7.40 (0.2913)

12

Wide Body

(R

W-24)

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

.

2

(

0

5 5

(

0

.

0

2

9

5

)

8

)

.

0

9

1.27 (0.0500)

0.40 (0.0157)

45°

060706-A

0.30 (0.0 118)

0.10 (0.0039)

COPLANARIT Y

0.10

24

1

1.27 (0.0500) BSC

CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DI MENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013-AD

Figure 36. 24-Lead Standard Small Outline Package [SOIC_W]

Dimensions shown in millimeters and (inches)

Rev. A | Page 17 of 20

AD5204/AD5206

www.BDTIC.com/ADI

24

PIN 1

0.15

0.05

0.10 COPLANARITY

Figure 37. 24-Lead Thin Shrink S

7.90

7.80

7.70

13

4.50

4.40

4.30

121

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AD

1.20

MAX

SEATING PLANE

6.40 BSC

0.20

0.09

8° 0°

mall Outline Package [TSSOP]

0.75

0.60

0.45

(RU-24)

Dimensions shown in millimeters

0.08

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

32

1

8

9

3.50 REF

PIN 1 INDICATOR

3.45

3.30 SQ

3.15

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-3)

ensions shown in millimeters

Dim

ORDERING GUIDE

Model1 kΩ Temperature Range Package Description Package Option

AD5204BN10 10 −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD5204BR10 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5204BR10-REEL 10 −40°C to +85°C 24-Lead Standar AD5204BRZ10 AD5204BRZ10-REEL

2

10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24

2

10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24

d Small Outline Package [SOIC_W] RW-24

AD5204BRU10 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] AD5204BRU10-REEL7 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] AD5204BRUZ10 AD5204BRUZ10-REEL7 AD5204BCPZ10-REEL AD5204BCPZ10-REEL7

2

10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

2

10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

2

10 −40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3

2

10 −40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3 AD5204BN50 50 −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] AD5204BR50 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] AD5204BR50-REEL 50 −40°C to +85°C 24-Lead Standar AD5204BRZ50 AD5204BRZ50-REEL

2

50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24

2

50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24

Rev. A | Page 18 of 20

d Small Outline Package [SOIC_W] RW-24

RU-24 RU-24

N-24-1 RW-24

AD5204/AD5206

www.BDTIC.com/ADI

Model1 kΩ Temperature Range Package Description Package Option

AD5204BRU50 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRU50-REEL 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRU50-REEL7 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRUZ502 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRUZ50-REEL7250 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BN100 100 −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD5204BR100 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5204BR100-REEL 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5204BRZ1002 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5204BRZ100-REEL AD5204BRU100 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRU100-REEL7 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRUZ1002 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRUZ100-R7 AD5206BN10 10 −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD5206BR10 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BR10-REEL 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRZ102 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRZ10-REEL AD5206BRU10 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRU10-REEL 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRU10-REEL7 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRUZ102 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRUZ10-RL7 AD5206BN50 50 −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD5206BR50 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BR50-REEL 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRZ502 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRU50 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRU50-REEL 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRU50-REEL7 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRUZ502 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRUZ50-REEL72 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BN100 100 −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD5206BR100 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BR100-REEL 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRZ1002 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRU100 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRU100-REEL7 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRUZ1002 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRUZ100-RL72 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

1

The AD5204/AD5206 each contain 5,925 transistors. Die size is 92 mil × 114 mil, or 10,488 sq. mil.

2

Z = RoHS Compliant Part.

2

100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24

2

100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

2

10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24

2

10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

Rev. A | Page 19 of 20

AD5204/AD5206

www.BDTIC.com/ADI

NOTES

Rev. A | Page 20 of 20

Datasheet AD5206 Datasheet (ANALOG DEVICES)

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

OPERATION

PROGRAMMING THE VARIABLE RESISTOR

RHEOSTAT OPERATION

PROGRAMMING THE POTENTIOMETER DIVIDER

VOLTAGE OUTPUT OPERATION

DIGITAL INTERFACING

OUTLINE DIMENSIONS

ORDERING GUIDE