Datasheet AD5203 Datasheet (Analog Devices)

4-Channel, 64-Position

SHDN

DAC 1

A1
W1
B1
AGND1

6

V

DD

DGND

SDI

CLK

CS

AD5203

SDO

SHDN

A2
W2
B2
AGND2

A3
W3

B3
AGND3

A4
W4
B4
AGND4

6

2

RS

6-BIT

LATCH

CK

RS

6

6-BIT

LATCH

CK

RS

SHDN

DAC 2

SHDN

DAC 3

6

6

SHDN

DAC 4

6-BIT

LATCH

CK

RS

6-BIT

LATCH

CK

RS

DAC

SELECT

A1, A0

1
2
3
4

8-BIT

SERIAL

LATCH

D

CK

Q

RS

a

Digital Potentiometer

AD5203

FEATURES
64 Position
Replaces Four Potentiometers
10 k⍀, 100 k⍀
Power Shutdown—Less than 5 ␮A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset

APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment

GENERAL DESCRIPTION

The AD5203 provides a quad channel, 64-position digitally­controlled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or vari­able resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 pack­ages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digi­tal code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B

terminal resistance of 10 kΩ, or 100 kΩ has a ±1% channel-to-

channel matching tolerance with a nominal temperature coeffi-

cient of 700 ppm/°C.

Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisy­chaining in multiple VR applications without additional external
decoding logic.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

The reset RS pin forces the wiper to the midscale position by
loading 20
tor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance set­ting prior to shutdown.

The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the

extended industrial temperature range of –40°C to +85°C.

For pin compatible higher resolution applications, see the 256­position AD8403 product.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

FUNCTIONAL BLOCK DIAGRAM

into the VR latch. The SHDN pin forces the resis-

H

AD5203–SPECIFICATIONS

(VDD = +3 V ⴞ 10% or +5 V ⴞ 10%, VA = +VDD, VB = 0 V, –40ⴗC < TA < +85ⴗC unless

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL
Resistor Nonlinearity Error
Nominal Resistor Tolerance

Resistance Temperature Coefficient ∆R

Wiper Resistance R

Nominal Resistance Match ∆R/R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs

Resolution N 6 Bits
Differential Nonlinearity Error
Integral Nonlinearity Error

Voltage Divider Temperature Coefficient ∆V

Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

5

6

Ax, Bx C

6

Wx C
Shutdown Supply Current
Shutdown Wiper Resistance R

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)

Power Supply Sensitivity PSS ∆V

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10K R

Total Harmonic Distortion THD

Settling Time tS_10K VA = VDD, V

V

W

Resistor Noise Voltage e

Crosstalk

11

INTERFACE TIMING CHARACTERISTICS Applies to All Parts

Input Clock Pulsewidth tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay

CS Setup Time t
CS High Pulsewidth t

Reset Pulsewidth t
CLK Fall to CS Rise Hold Time t

CS Rise to Clock Rise Setup t

2

2

3

4

4

R-DNL RWB, V
R-INL RWB, V

∆R

DNL –0.25 ±0.1 +0.25 LSB
INL –0.75 ±0.1 +0.75 LSB

VA, VB, V

7

6

8

9

I

C

I
P

PSS ∆VDD = +3 V ± 10% 0.006 0.03 %/%

6, 10

BW_100K R

t

C

13

t

otherwise noted)

= No Connect –0.25 ±0.1 +0.25 LSB

A

= No Connect –0.5 ±0.1 +0.5 LSB

A

AB

/∆TV

AB

W

O

/∆T Code = 20

W

WFSE

WZSE

A, CB

W

A_SD

W_SD

IH

IL

IH

IL

OH

OL

IL

IL

Range 2.7 5.5 V

DD

DD

DD

DISS

W

_100K VA = VDD, V

S

NWB

T

CL

DS

DH

PD

CSS

CSW

RS

CSH

CS1

= V

AB

IW = 1 V/R
CH 1 to CH 2, VAB = VDD , T

Code = 3F
Code = 00

W

, Wiper = No Connect 700 ppm/°C

DD

AB

H

H

H

= +25°C 0.2 1 %

A

f = 1 MHz, Measured to GND, Code = 20
f = 1 MHz, Measured to GND, Code = 20
VA = VDD, V
VA = VDD, VB = 0 V, SHDN = 0, V

= 0 V, SHDN = 0 0.01 5 µA

B

= +5 V 45 100 Ω

DD

VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
R

= 2.2 kΩ to V

L

DD

IOL = 1.6 mA, VDD = +5 V 0.4 V
VIN = 0 V or +5 V, V

VIH = VDD or V

= +5 V ±1 µA

DD

= 0 V 0.01 5 µA

IL

VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, V

= +5 V ± 10% 0.0002 0.001 %/%

DD

= 10 kΩ 600 kHz

AB

= 100 kΩ 71 kHz

AB

= +5.5 V 27.5 µW

DD

VA =1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %

= 0 V, ±1 LSB Error Band 2 µs

B

= 0 V, ±1 LSB Error Band 18 µs

R

WB

R

WB

B

= 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz
= 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz

VA = VDD, VB = 0 V –65 dB

6, 12

Clock Level High or Low 10 ns

R

= 2.2 kΩ, C

L

< 20 pF 1 25 ns

L

–30 +30 %

45 100 Ω

20 ppm/°C

–0.75 –0.2 0 LSB
0 +0.1 +0.75 LSB

0V

H

H

75 pF
120 pF

DD

VDD–0.1 V

5pF

5ns
5ns

10 ns
10 ns
50 ns

0ns

10 ns

V

–2– REV. 0

AD5203

WARNING!

ESD SENSITIVE DEVICE

SDI

CLK

CS

V

OUT

1

0

1

0

1

0

V

DD

0V

D0D1D2D3D4D5A0A1

DAC REGISTER LOAD

CLK

V

OUT

1
0

1
0

1
0

V

DD

0V

SDI

(DATA IN)

SDO

(DATA OUT)

CS

1
0

Ax OR Dx Ax OR Dx

A'x OR D'x

t

DStDH

t

PD MAX

t

PD MIN

t

CH

t

CS1

t

CL

t

CSS

t

CSH

61 LSB

6 1 LSB ERROR BAND

t

CSW

t

S

A'x OR D'x

V

OUT

V

DD

0V

RS

1
0

61 LSB

61 LSB ERROR BAND

t

S

t

RS

NOTES

1

Typicals represent average readings at +25°C and V

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-

tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. IW = VDD/R
for both V

3

VAB = VDD, Wiper (VW) = No connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.

8

Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of IDD vs. logic voltage

inputs result in minimum power dissipation.

9

P

DISS

10

All dynamic characteristics use VDD = +5 V.

11

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

12

See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V

13

Propagation delay depends on value of VDD, RL and CL. See Operation section.

= +3 V or VDD = +5 V.

DD

is calculated from (I

× V

). CMOS logic level inputs result in minimum power dissipation.

DD

DD

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C, unless otherwise noted)

A

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

V

A

IAB, IAW, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

BW

Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Resistance θ

JA

P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W

SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

= +5 V.

DD

= +3 V or +5 V. Input logic should have a 1 V/ µs minimum slew rate.

DD

DD

MAX) . . . . . . . .+150°C

max–T

J

)/θ

A

Figure 1a. Timing Diagram

JA

Table I. Serial-Data Word Format

ADDR DATA
B7 B6 B5 B4 B3 B2 B1 B0

A1 A0 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB

7

2

6

2

5

2

0

2

Figure 1b. Detail Timing Diagram

Figure 1c. Reset Timing Diagram

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. 0

AD5203

PIN CONFIGURATION

AGND2

B2
A2
W2

AGND4

B4
A4
W4

DGND

SHDN

CS

SDI

1
2
3
4
5

AD5203

6

(Not to Scale)

7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

B1
A1
W1
AGND1
B3
A3
W3
AGND3
V

DD

RS

CLK
SDO

PIN FUNCTION DESCRIPTIONS

Pin
No. Name Description

1 AGND2 Analog Ground #2*
2 B2 B Terminal RDAC #2
3 A2 A Terminal RDAC #2
4 W2 Wiper RDAC #2, addr = 01

2

5 AGND4 Analog Ground #4*
6 B4 B Terminal RDAC #4
7 A4 A Terminal RDAC #4
8 W4 Wiper RDAC #4, addr = 11

2

9 DGND Digital Ground*
10 SHDN Active Low Input. Terminal A open circuit.

Shutdown controls Variable Resistors #1
through #4.

11 CS Chip Select Input, Active Low. When CS

returns high data in the serial input register
is decoded based on the address bits and

loaded into the target DAC register.
12 SDI Serial Data Input
13 SDO Serial Data Output. Open drain transistor

requires pull-up resistor.
14 CLK Serial Clock Input, positive edge triggered.
15 RS Active low reset to midscale; sets RDAC

16 V

DD

registers to 20

Positive power supply, specified for opera-

.

H

tion at both +3 V and +5 V.
17 AGND3 Analog Ground #3*
18 W3 Wiper RDAC #3, addr =10

2

19 A3 A Terminal RDAC #3
20 B3 B Terminal RDAC #3
21 AGND1 Analog Ground #1*
22 W1 Wiper RDAC #1, addr = 00

2

23 A1 A Terminal RDAC #1
24 B1 B Terminal RDAC #1

*All AGNDs must be connected to DGND voltage potential.

ORDERING GUIDE

Model k⍀ Temperature Range Package Descriptions Package Options

AD5203AN10 10 –40°C to +85°C 24-Lead Narrow Body Plastic DIP N-24
AD5203AR10 10 –40°C to +85°C 24-Lead Wide Body (SOIC) SOL-24
AD5203ARU10 10 –40°C to +85°C 24-Lead Thin Surface Mount Package (TSSOP) RU-24
AD5203AN100 100 –40°C to +85°C 24-Lead Narrow Body Plastic DIP N-24
AD5203AR100 100 –40°C to +85°C 24-Lead Wide Body (SOIC) SOL-24
AD5203ARU100 100 –40°C to +85°C 24-Lead Thin Surface Mount Package (TSSOP) RU-24

–4– REV. 0

Typical Performance Characteristics–

DIGITAL INPUT CODE – Decimal

R

INL

ERROR – LSB

0.25

–0.25

08 64

16 24 32 40 48 56

0.2

0.05
0

–0.1

–0.2

0.15

0.1

–0.05

–0.15

VDD = +3.0V

TA = –558C

TA = +858C

TA = +258C

DIGITAL INPUT CODE – Decimal

INL NONLINEARITY ERROR – LSB

0.25

–0.25

08 6416 24 32 40 48 56

0.2

0.05
0

–0.1

–0.2

0.15

0.1

–0.05

–0.15

–558C

+858C

+258C

VDD = +3.0V

CODE – Decimal

RHEOSTAT MODE TEMPCO – ppm/8C

120

0

08 64

16 24 32 40 48 56

80

100

60

40

20

VDD = +3.0V
T

A

= –408C/+858C

V

A

= NO CONNECT

R

WB

MEASURED

AD5203

10

9
8
7
6
5
4

RESISTANCE – kV

3
2
1
0

08 64

VDD = +3V, OR +5V

= 10kV

R

AB

R

WB

16 24 32 40

CODE – Decimal

R

WA

48

56

Figure 2. Wiper to End Terminal
␣ ␣ Resistance vs. Code

80

60

40

FREQUENCY

20

SS = 544 UNITS
VDD = +4.5V

= +258C

T

A

5

3F

4.5
4

3.5
3

2.5

VOLTAGE – V

2

WB

V

1.5
1

0.5
0

H

20

H

10

H

08

H

05

H

0

1723456

IWA CURRENT – mA

02

H

RAB = 10kV

= +5V

V

DD

= +258C

T

A

Figure 3. Resistance Linearity vs.
␣ ␣ Conduction Current

12

AD5203-10K VERSION

10

8

6

4

NOMINAL RESISTANCE – kV

2

RAB (END-TO-END)

RWB (WIPER-TO-END)
CODE = 20

H

Figure 4. Resistance Step Position
␣ ␣ Nonlinearity Error vs. Code

0

32 33 34 35 36 37 38 39

30 31

WIPER RESISTANCE – V

Figure 5.␣ Wiper-Contact-Resistance
Histogram

0.25
VDD = +3.0V

0.2
= +258C, +858C, –408C

T

A

0.15

0.1

0.05
0

–0.05

DNL ERROR – LSB

–0.1

–0.15

–0.2

–0.25

0

864

16 24 32 40 48 56

DIGITAL INPUT CODE – Decimal

Figure 8. Potentiometer Divider

Differential Nonlinearity Error vs.

Code

0

–25 0 25 50 75 100

–75 –50 125

TEMPERATURE – 8C

␣ ␣ Figure 6.␣ Nominal Resistance vs.
␣ ␣ Temperature

50

40

30

20

10

POTENTIOMETER MODE TEMPCO – ppm/8C

0

08 6416 24 32 40 48 56

CODE – Decimal

VDD = +3.0V

= –408C/+858C

T

A

= +2.0V

V

A

= 0V

V

B

Figure 9.␣∆VWB/∆T Potentiometer

Mode Tempco

–5–REV. 0

␣␣␣ Figure 7. Potentiometer Divider
␣ ␣ Nonlinearity Error vs. Code

Figure 10.∆RWB/∆T Rheostat Mode
Tempco

AD5203

HOURS OF OPERATION @ 1508C

DR

WB

RESISTANCE – %

0.75

–0.75

0 100 600

200 300 400 500

0.5

0.25

0

–0.25

–0.5

VDD = +5V
CODE = 3F

H

SS = 77 UNITS

AVG –2 S

AVG +2 S

AVG

V

OUT

(20mV/DIV)

TIME 100ns/DIV

–Typical Performance Characteristics

R

W

(20mV/DIV)

CS

(5V/DIV)

TIME 500ns/DIV

Figure 11. One Position Step Change
at Half-Scale (Code 1F

OUTPUT

CS

to 20H)

H

TIME 5ms/DIV

0

–10

–20

GAIN – dB

–30

–40

–50

10 100 1M

CODE = 3F

TA = +258C
SEE TEST CIRCUIT FIGURE 32

H

20

H

10

H

08

H

04

H

02

H

01

H

1k 10k 100k

FREQUENCY – Hz

Figure 12. Gain vs. Frequency for
R = 10 k

10

0.1

THD + NOISE – %

0.01

0.001

Ω

FILTER = 22kHz
V

= +5V

DD

TA = +258C

1

RAB = 10kV

SEE TEST CIRCUIT FIGURE 31

SEE TEST CIRCUIT FIGURE 30

10 100k100 1k 10k

FREQUENCY – Hz

10M

␣␣␣␣ Figure 13. Long-Term Drift
Accelerated by Burn-In

Figure 14. Large Signal Settling Time

0

–10

–20

GAIN – dB

–30

–40

VDD = +5V

= +258C

T

A

5dB/DIV

–50

10 100 1M

Figure 17. 100 kΩ Gain vs. Frequency
vs. Code

FREQUENCY – Hz

CODE = 3F

H

20

H

10

H

08

H

04

H

02

H

01

H

1k 10k 100k

Figure 15.␣ Total Harmonic Distortion
Plus Noise vs. Frequency

0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7

VDD = +5V
CODE = 3F

–0.8

TA = +258C
SEE TEST CIRCUIT FIGURE 32

–0.9

NORMALIZED GAIN FLATNESS – 0.1dB/DIV

–1.0

10 100 1M

RAB = 10kV

RAB = 100kV

H

1k 10k 100k

FREQUENCY – Hz

Figure 18. Normalized Gain Flat­ness vs. Frequency

–6– REV. 0

Figure 16. Digital Feedthrough vs.
Time

10

1

0.1

SUPPLY CURRENT – mA

DD

I

0.01
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

INPUT LOGIC VOLTAGE – Volts

VDD = +5.0V

VDD = +3.0V

Figure 19. Supply Current vs. Logic
Input Voltage

AD5203

FREQUENCY – Hz

1k 1M

10M10k 100k

I

DD

–

SUPPLY CURRENT – mA

1200

1000

800

600

400

200

0

TA = +258C

A

B

C

D

A – VDD = +5.5V

CODE = 15

H

B – VDD = +3.3V

CODE = 15

H

C – VDD = +5.5V

CODE = 3F

H

D – VDD = +3.3V

CODE = 3F

H

TEMPERATURE – 8C

I

DD

– SUPPLY CURRENT – mA

1

0.1

0.001
–55 –35 125–15 5 25 45 65 85 105

0.01
V

DD

= +5.5V

V

DD

= +3.3V

LOGIC INPUT
VOLTAGE = 0, V

DD

80

60

40

PSRR – dB

VDD = +5V DC 61V p-p AC

= +258C

T

A

20

CODE = 80
CL = 10pF
V

0

H

= 4V, VB = 0V

A

FREQUENCY – Hz

100k1k 10k

1M

Figure 20. Power Supply Rejection
vs. Frequency

100

– V

ON

R

80

60

40

VDD = +2.7V

VDD = +5.5V

TA = +258C

0

–5

–10
–15

–20
–25

GAIN – dB

–30

VDD = +5V

–35

V

IN

–40

CODE = 20
TA = +258C

–45
–50

10 100 1M

f

–3dB

= 100mV rms

H

1k 10k 100k

FREQUENCY – Hz

= 65kHz,

R = 100kV

f

–3dB

= 625kHz,

R = 10kV

Figure 21. –3␣ dB Frequency at
Half-Scale

100

VDD = +5V

Figure 22. Supply Current vs. Clock
Frequency

20

0

01 6

Figure 23. Incremental Wiper ON
Resistance vs. V

23 45

VDD – Volts

DD

SHUTDOWN CURRENT – nA

A

I

1
–55 –3510–15 5 25 45 65 85 105 125

TEMPERATURE – 8C

␣␣␣␣Figure 24. Shutdown Current vs.
␣ ␣ ␣ ␣ Temperature

–7–REV. 0

Figure 25. Supply Current vs.
Temperature

AD5203

~

AB

V

IN

2.5V

OP279

+5V

V

OUT

DUT

W

OFFSET

GND

I

SW

0 TO V

DD

R

SW

=

0.1V
I

SW

CODE = ØØ

H

0.1V

DUT

B

W

–Parametric Test Circuits

DUT
A

V+

W

B

V+ = V

DD

1LSB = V+/64

V

MS

OFFSET

GND

A

B

DUT

+5V

~

2.5V DC

W

OP279

V

OUT

V

IN

Figure 26. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)

NO CONNECT

DUT
A

B

W

I

W

V

MS

Figure 27. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)

I

MS

DUT
A

V+

B

IW = 1V/R

V

W

W

NOMINAL

V

MS

V+ < V

DD

VW2 – [VW1 + IW (RAWII RBW)]

= ––––––––––––––––––––––––––

R

W

WHERE V

AND V

W2

= VMS WHEN IW = 1/R

W1

= V

MS

I

W

WHEN IW = 0

␣ ␣ Figure 28.␣ Wiper Resistance Test Circuit

Figure 30. Inverting Programmable Gain Test Circuit

␣ Figure 31. Noninverting Programmable Gain Test Circuit

OFFSET

GND

A

V

~

IN

DUT

W

B

2.5V

+15V

OP42

–15V

V

OUT

␣ Figure 32. Gain vs. Frequency Test Circuit

V

A

V+ = V

± 10%

A

V

DD

V+

~

W

B

V

MS

DD

PSRR (dB) = 20 LOG ( ––––– )

PSS (%/%) = –––––––

DVMS%
DVDD%

Figure 29. Power Supply Sensitivity Test Circuit (PSS,
PSRR)

DV
DV

MS
DD

Figure 33. Incremental ON Resistance Test Circuit

–8– REV. 0

AD5203

OPERATION

The AD5203 provides a quad channel, 64-position digitally­controlled variable resistor (VR) device. Changing the pro­grammed VR settings is accomplished by clocking in an 8-bit
serial data word into the SDI (Serial Data Input) pin. The for­mat of this data word is two address bits, MSB first, followed by
six data bits, MSB first. Table I provides the serial register data
word format. The AD5203 has the following address assign­ments for the ADDR decode, which determines the location of
VR latch receiving the serial register data in Bits B5 through B0:

VR# = A1 × 2 + A0 + 1

VR outputs can be changed one at a time in random sequence.
The serial clock running at 10 MHz makes it possible to load all

four VRs in under 3.2 µs (8 × 4 × 100 ns) for the AD5203. The

exact timing requirements are shown in Figure 1.
The AD5203 resets to a midscale by asserting the RS pin, sim-

plifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin that places the RDAC in a zero power
consumption state where terminals Ax are open-circuited and
the wiper Wx is connected to Bx, resulting in only leakage cur­rents being consumed in the VR structure. In shutdown mode
the VR latch settings are maintained so that, returning to opera­tional mode from power shutdown, the VR settings return to
their previous resistance values.

Ax

Wx

Bx

SHDN

D5
D4
D3
D2
D1
D0

RDAC

LATCH

DECODER

R

S

R

S

R

S

&

R

S

= RAB/64

R

S

Figure 34. Equivalent RDAC Circuit

PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation

The nominal resistance of the RDAC between Terminals A and

B are available with values of 10 kΩ, and 100 kΩ. The final

digits of the part number determine the nominal resistance

value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance

) of the VR has 64 contact points accessed by the wiper

(R

AB

terminal, plus the B terminal contact. The 6-bit data word in
the RDAC latch is decoded to select one of the 64 possible
settings. The wiper’s first connection starts at the B terminal for
data 00

. This B–terminal connection has a wiper contact resis-

H

tance of 45 Ω. The second connection (10 kΩ part) is the first

tap point located at 201 Ω [= R
= 156 Ω + 45 Ω)] for data 01
tap point representing 312 + 45 = 357 Ω for data 02

(nominal resistance)/64 + R

BA

. The third connection is the next

H

. Each

H

W

LSB data value increase moves the wiper up the resistor ladder

until the last tap point is reached at 9889 Ω. The wiper does not

directly connect to the B Terminal. See Figure 34 for a simpli­fied diagram of the equivalent RDAC circuit.

The general transfer equation that determines the digitally pro­grammed output resistance between Wx and Bx is:

R

(Dx) = (Dx)/64 × R

WB

BA

+ R

W

(1)

where Dx is the data contained in the 6-bit RDACx latch and

R

is the nominal end-to-end resistance.

BA

For example, when V

= 0 V and A–terminal is open circuit the

B

following output resistance values will be set for the following
RDAC latch codes (applies to the 10K potentiometer):

D (DEC) R

(⍀) Output State

WB

63 9889 Full-Scale
32 5045 Midscale (RS = 0 Condition)
1 201 1 LSB
0 45 Zero-Scale (Wiper Contact Resistance)

Note that in the zero-scale condition a finite wiper resistance of

45 Ω is present. Care should be taken to limit the current flow

between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.

Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
terminal A also produces a digitally controlled resistance R

WA

.
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for R

starts at a maxi-

WA

mum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:

R

(Dx) = (64-Dx)/64 × R

WA

BA

+ R

W

(2)

where Dx is the data contained in the 6-bit RDACx latch and

R

is the nominal end-to-end resistance. For example, when

BA

= 0 V and B–terminal is tied to the wiper W, the following

V

A

output resistance values will be set for the following RDAC
latch codes:

D (DEC) R

(⍀) Output State

WA

63 201 Full-Scale
32 5045 Midscale (RS = 0 Condition)
1 9889 1 LSB
0 10045 Zero-Scale

The typical distribution of R

from channel to channel matches

BA

within ±1%. However, device-to-device matching is process-lot­dependent, having a ±30% variation. The change in R

BA

with

temperature has a 700 ppm/°C temperature coefficient.

–9–REV. 0

AD5203

PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation

The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A–terminal to +5 V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V.
Each LSB of voltage is equal to the voltage applied across ter­minal AB divided by the 64 position resolution of the potenti­ometer divider. The general equation defining the output
voltage with respect to ground for any given input voltage ap­plied to terminals AB is:

V

(Dx) = Dx/64 × V

W

AB

+ V

B

Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors

not the absolute value, therefore the drift improves to 20 ppm/°C.

DIGITAL INTERFACING

The AD5203 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), CS and serial data
input (SDI). The positive-edge sensitive CLK input requires
clean transitions to avoid clocking incorrect data into the serial
input register. Standard logic families work well. If mechanical
switches are used for product evaluation they should be de­bounced by a flip-flop or other suitable means. The Figure 35
block diagram shows more detail of the internal digital cir­cuitry. When CS is taken active low the clock loads data into
the serial register on each positive clock edge, see Table III.

CS

CLK

SDO

SDI

SHDN

DO

DI

SER
REG

DGND

AD5203

D5

EN

ADDR

DEC

A1
A0

D5

D0

6

RS

R

DAC
LAT

#1

D0

R

D5

R

DAC

LAT

#4

D0

R

AGND

V

A1
W1
B1

A4
W4
B4

DD

Figure 35. Block Diagram

The serial-data-output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. The pull-up
resistor termination voltage may be larger than the V

supply

DD

of the AD5203 SDO output device, e.g., the AD5203 could
operate at V

= 3.3 V and the pull-up for interface to the next

DD

device could be set at +5 V. This allows for daisy chaining sev­eral RDACs from a single processor serial data line. Clock pe­riod needs to be increased when using a pull-up resistor to the
SDI pin of the following device in the series. Capacitive loading
at the daisy chain node SDO-SDI between devices must be
accounted for to successfully transfer data. When daisy chaining
is used, the CS should be kept low until all the bits of every
package are clocked into their respective serial registers insuring
that the address bits and data bits are in the proper decoding
location. This would require 16 bits of address and data comply­ing to the word format provided in Table I if two AD5203 four­channel RDACs are daisy chained. During shutdown, SHDN
the SDO output pin is forced to the off (logic high state) to
disable power dissipation in the pull-up resistor. See Figure 37
for equivalent SDO output circuit schematic.

Table II. Input Logic Control Truth Table

CLK CS RS SHDN Register Activity

L L H H No SR effect, enables SDO pin.
P L H H Shift one bit in from the SDI pin.

The eighth previously entered bit
is shifted out of the SDO pin.

X P H H Load SR data into RDAC latch

based on A1, A0 decode (Table III).
X H H H No Operation.
X X L H Sets all RDAC latches to midscale,

wiper centered and SDO latch

cleared.
X H P H Latches all RDAC latches to 20

.

H

X H H L Open circuits all Resistor A–termi-

nals, connects W to B, turns off

SDO output transistor.

NOTE: P = positive edge, X = don’t care, SR = shift register.

Table III. Address Decode Table

A1 A0 Latch Decoded

0 0 RDAC#1
0 1 RDAC#2
1 0 RDAC#3
1 1 RDAC#4

–10– REV. 0

AD5203

The data setup and data hold times in the specification table
determine the data valid time requirements. The last eight bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it gates the
address decoder which enables one of four positive edge trig­gered RDAC latches, see Figure 36 detail.

CS

CLK

SDI

AD5203

ADDR

DECODE

SERIAL

REGISTER

RDAC 1
RDAC 2

RDAC 4

Figure 36. Equivalent Input Control Logic

The target RDAC latch is loaded with the last six bits of the
serial data word completing one RDAC update. Four separate
8-bit data words must be clocked in to change all four VR
settings.

SHDN

SDI

CLK

CS

RS

SERIAL

REGISTER

Q

D

CK

RS

SDO

All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 38. Applies to
digital input pins CS, SDI, SDO, RS, SHDN, CLK.

1kV

LOGIC

Figure 38. Equivalent ESD Protection Circuit

DYNAMIC CHARACTERISTICS

The total harmonic distortion plus noise (THD+N) measures

0.003% using an offset ground with a rail-to-rail OP279 invert­ing op amp test circuit, see Figure 30. Figure 15 plots THD
versus frequency for both inverting and noninverting amplifier
topologies. Thermal noise is primarily Johnson noise, typically

9 nV/√Hz for the 10 kΩ version measured at 1 kHz. For the
100 kΩ device, thermal noise measures 29 nV/√Hz. Channel-to-

channel crosstalk measures less than –65 dB at f = 100 kHz. To
achieve this isolation, the extra ground pins (AGND) located
between the potentiometer terminals (A, B, W) must be con­nected to circuit ground. The AGND and DGND pins should
be at the same voltage potential. Any unused potentiometers in
a package should be connected to ground. Power supply rejec­tion is typically –50 dB at 10 kHz (care is needed to minimize
power supply ripple injection in high accuracy applications).

Figure 37. Detail, SDO Output Schematic of the AD5203

–11–REV. 0

AD5203

0.210

(5.33)

MAX

0.200 (5.05)

0.125 (3.18)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead Narrow Body Plastic DIP

(N-24)

1.275 (32.30)

1.125 (28.60)

24

112

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100 (2.54)
BSC

13

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

24-Lead SOIC

(SOL-24)

0.6141 (15.60)

0.5985 (15.20)

0.195 (4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

C3364–8–7/98

24

1

0.0118 (0.30)

0.0040 (0.10)

0.177 (4.50)

0.169 (4.30)

13

12

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

PIN 1

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.1043 (2.65)

0.0926 (2.35)

SEATING
PLANE

0.0125 (0.32)

0.0091 (0.23)

24-Lead Thin Surface Mount TSSOP

(RU-24)

0.311 (7.90)

0.303 (7.70)

24 13

0.256 (6.50)

1

0.246 (6.25)

12

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8°
0°

0.0157 (0.40)

x 45°

PRINTED IN U.S.A.

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

PIN 1

0.0256 (0.65)
BSC

0.0118 (0.30)

0.0075 (0.19)

–12–

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

8°
0°

0.028 (0.70)

0.020 (0.50)

REV. 0