Datasheet AD5201BRM50-REEL7, AD5201BRM10-REEL7, AD5200BRM50-REEL7, AD5200BRM10-REEL7 Datasheet (Analog Devices)

256-Position and 33-Position

a

FEATURES
AD5200—256-Position
AD5201—33-Position
10 k, 50 k
3-Wire SPI-Compatible Serial Data Input
Single Supply 2.7 V to 5.5 V or
Dual Supply 2.7 V for AC or Bipolar Operations
Internal Power-On Midscale Preset

APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching

GENERAL DESCRIPTION

The AD5200 and AD5201 are programmable resistor devices,
with 256 positions and 33 positions respectively, that can be digi­tally controlled through a 3-wire SPI serial interface. The terms
programmable resistor, variable resistor (VR), and RDAC are
commonly used interchangeably to refer to digital potentiometers.
These devices perform the same electronic adjustment function
as a potentiometer or variable resistor. Both AD5200/AD5201
contain a single variable resistor in the compact µSOIC-10
package. Each device contains a fixed wiper resistance at the
wiper contact that taps the programmable resistance at a point
determined by a digital code. The code is loaded in the serial
input register. The resistance between the wiper and either end
point of the programmable resistor varies linearly with respect to
the digital code transferred into the VR latch. Each variable
resistor offers a completely programmable value of resistance,
between the A terminal and the wiper, or the B terminal and the
wiper. The fixed A-to-B terminal resistance of 10 kΩ or 50 kΩ

Digital Potentiometers

AD5200/AD5201

FUNCTIONAL BLOCK DIAGRAM

V

CS

CLK

SDI

GND

DD

AD5200/AD5201

SER
REG

8/6

Dx

PWR-ON
PRESET

RDAC

REG

has a nominal temperature coefficient of 500 ppm/°C. The VR
has a VR latch that holds its programmed resistance value. The
VR latch is updated from an SPI-compatible serial-to-parallel
shift register that is loaded from a standard 3-wire serial-input
digital interface. Eight data bits for the AD5200 and six data
bits for the AD5201 make up the data word that is clocked into
the serial input register. The internal preset forces the wiper to
the midscale position by loading 80

and 10H into AD5200 and

H

AD5201 VR latches respectively. The SHDN pin forces the
resistor to an end-to-end open-circuit condition on the A terminal
and shorts the wiper to the B terminal, achieving a microwatt
power shutdown state. When SHDN is returned to logic high,
the previous latch setting puts the wiper in the same resistance
setting prior to shutdown. The digital interface is still active dur­ing shutdown so that code changes can be made that will produce
a new wiper position when the device is returned from shutdown.

All parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C.

V

SS

A

W

B

SHDN

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD5200/AD5201–SPECIFICATIONS

(VDD = 5 V  10%, or 3 V  10%, VSS = 0 V, VA = +VDD, VB = 0 V,

AD5200 ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient R
Wiper Resistance R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)

Resolution N 8 Bits
Differential Nonlinearity
Integral Nonlinearity

4

4

Voltage Divider Temperature Coefficient ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

5

6

A, B CA,

6

WC
Shutdown Supply Current
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

6

POWER SUPPLIES

Logic Supply V
Power Single-Supply Range V
Power Dual-Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation

8

Power Supply Sensitivity PSS ∆VDD = +5 V ± 10%, Code = Midscale –0.01 0.001 +0.01 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ, Code = 80

Total Harmonic Distortion THD

Settling Time (10 kΩ/50 kΩ)tSVA = 5 V, VB = 0 V, ± 1 LSB Error Band 2/9 µs

V

W

Resistor Noise Voltage Density e

NOTES

1

Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi­tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
VSS = –2.7 V.

3

VAB = VDD, Wiper (VW) = No connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.

5

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. A terminal is open-circuited in shutdown mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V, VSS = 0 V.

Specifications subject to change without notice.

2

2

3

R-DNL RWB, VA = No Connect –1 ± 0.25 +1 LSB
R-INL RWB, VA = No Connect –2 ± 0.5 +2 LSB
∆R

AB

/∆TV

AB

W

DNL –1 ± 1/4 +1 LSB
INL –2 ±1/2 +2 LSB

/∆T Code = 80

W

WFSE

WZSE

VA, B,

W

B

7

6, 9

W

I

DD_SD

CM

IH

IL

IH

IL

IL

C

IL

LOGIC

DD RANGE

DD/SS RANGE

DD

SS

P

DISS

BW_50 kΩ R

W

N_WB

–40C < TA < +85C unless otherwise noted.)

TA = 25°C –30 +30 %

= VDD, Wiper = No Connect 500 ppm/ °C

AB

VDD = 5 V 50 100 Ω

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80

H

H

H

H

H

VDD = 5.5 V 0.01 5 µA
VA = VB = VDD/2 1 nA

VDD = 3 V, VSS = 0 V 2.1 V
VDD = 3 V, VSS = 0 V 0.6 V
VIN = 0 V or 5 V ±1 µA

VSS = 0 V –0.3 5.5 V

VIH = +5 V or VIL = 0 V 15 40 µA
VSS = –5 V 15 40 µA
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = 0 V 0.2 mW

= 50 kΩ, Code = 80

AB

H

H

VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 0.003 %

RWB = 5 kΩ, RS = 0 9 nV√Hz

5 ppm/ °C

–1.5 –0.5 0 LSB
0 +0.5 +1.5 LSB

V

SS

V

V

DD

45 pF
60 pF

2.4 V

0.8 V

5pF

2.7 5.5 V

± 2.3 ±2.7 V

600 kHz
100 kHz

= VDD/R for both VDD = +2.7 V,

W

= VDD and VB = 0 V. DNL

A

–2–

REV. B

AD5200/AD5201

(VDD = 5 V  10%, or 3 V  10%, VSS = 0 V, VA = +VDD, VB = 0 V,

AD5201 ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient R
Wiper Resistance R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)

Resolution
Differential Nonlinearity
Integral Nonlinearity

4

5

5

Voltage Divider Temperature Coefficient ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

6

7

A, B CA,

7

WC
Shutdown Supply Current
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

7

POWER SUPPLIES

Logic Supply V
Power Single-Supply Range V
Power Dual-Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation

9

Power Supply Sensitivity PSS ∆VDD = +5 V ± 10% –0.01 0.001 +0.01 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ, Code = 10

Total Harmonic Distortion THD

Settling Time (10 kΩ/50 kΩ)tSVA = 5 V, VB = 0 V, ± 1 LSB Error Band 2/9 µs

V

W

Resistor Noise Voltage Density e

NOTES

1

Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi­tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
VSS = –2.7 V.

3

VAB = VDD, Wiper (VW) = No connect.

4

Six bits are needed for 33 positions even though it is not a 64-position device.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.

6

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

7

Guaranteed by design and not subject to production test.

8

Measured at the A terminal. A terminal is open-circuited in shutdown mode.

9

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

10

All dynamic characteristics use VDD = 5 V, VSS = 0 V.

Specifications subject to change without notice.

2

2

3

R-DNL RWB, VA = No Connect –0.5 ± 0.05 +0.5 LSB
R-INL RWB, VA = No Connect –1 ± 0.1 +1 LSB
∆R

AB

/∆TV

AB

W

N 6 Bits
DNL –0.5 ±0.01 +0.5 LSB
INL –1 ±0.02 +1 LSB

/∆T Code = 10

W

WFSE

WZSE

VA, B,

W

B

8

7, 10

W

I

DD_SD

CM

IH

IL

IH

IL

IL

C

IL

LOGIC

DD RANGEVSS

DD/SS RANGE

DD

SS

P

DISS

BW_50 kΩ R

W

N_WB

–40C < TA < +85C unless otherwise noted.)

TA = 25°C –30 +30 %

= VDD, Wiper = No Connect 500 ppm/ °C

AB

VDD = 5 V 50 100 Ω

Code = 20
Code = 00

f = 1 MHz, Measured to GND, Code = 10
f = 1 MHz, Measured to GND, Code = 10

H

H

H

H

H

VDD = 5.5 V 0.01 5 µA
VA = VB = VDD/2 1 nA

VDD = 3 V, VSS = 0 V 2.1 V
VDD = 3 V, VSS = 0 V 0.6 V
VIN = 0 V or 5 V ±1 µA

= 0 V –0.3 5.5 V

VIH = +5 V or VIL = 0 V 15 40 µA
VSS = –5 V 15 40 µA
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V 0.2 mW

= 50 kΩ, Code = 10

AB

H

H

VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 0.003 %

RWB = 5 kΩ, RS = 0 9 nV√Hz

W

5 ppm/ °C

–1/2 –1/4 0 LSB
0 +1/4 +1/2 LSB

V

SS

V

V

DD

45 pF
60 pF

2.4 V

0.8 V

5pF

2.7 5.5 V

± 2.3 ±2.7 V

600 kHz
100 kHz

= VDD/R for both VDD = +2.7 V,

= VDD and VB = 0 V. DNL

A

REV. B

–3–

AD5200/AD5201–SPECIFICATIONS

(VDD = 5 V  10%, or 3 V  10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40C < TA < +85C

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])

Input Clock Pulsewidth t
Data Setup Time t
Data Hold Time t

CS Setup Time t
CS High Pulsewidth t

CLK Fall to CS Fall Hold Time t
CLK Fall to CS Rise Hold Time t
CS Rise to Clock Rise Setup t

NOTES

1

Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2

Guaranteed by design and not subject to production test.

3

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of

1.5 V. Switching characteristics are measured using V

Specifications subject to change without notice.

SDI

CLK

CS

VOUT

unless otherwise noted.)

, t

CH

CL

DS

DH

CSS

CSW

CSH0

CSH1

CS1

= 5 V.

LOGIC

1

0

1

0
1

0
1

0

Figure 1a. AD5200 Timing Diagram

Clock Level High or Low 20 ns

D7 D6 D5 D4 D3 D2 D1 D0

DAC REGISTER LOAD

1

Max Unit

5ns
5ns
15 ns
40 ns
0ns
0ns
10 ns

1

SDI D5D4D3D2D1D0

0
1

CLK

0

CS

VOUT

1

0
1

0

DAC REGISTER LOAD

Figure 1b. AD5201 Timing Diagram

1

SDI

(DATA IN)

CLK

CS

VOUT

0

1

0

1

0

V

DD

0

Dx Dx

t

CSH0

t

CSS

t

DS

t

CH

t

CL

t

DH

Figure 1c. Detail Timing Diagram

t

CSH1

t

CS1

t

CSW

t

S

1LSB

–4–

REV. B

AD5200/AD5201

TOP VIEW

(Not to Scale)

10

9

8

7

6

1

2

3

4

5

AD5200/

AD5201

B

V

SS

GND

CS

SDI

A

W

V

DD

SHDN

CLK

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted)

1

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +7 V

V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V

SS

V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

A

I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA

MAX

DD

2

Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

Max) . . . . . . . . . 150°C

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300° C

Thermal Resistance θ
Package Power Dissipation = (T

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Max current is bounded by the maximum current handling of the switches,

maximum power dissipation of the package, and maximum applied voltage across
any two of the A, B, and W terminals at a given resistance. Please refer to TPC 31
and TPC 32 for detail.

µSOIC-10 . . . . . . . . . . . . . 200°C/W

JA,

Max – TA)/θ

J

JA

PIN FUNCTION DESCRIPTIONS

Pin Name Description

1 B B Terminal.
2V

SS

Negative Power Supply, specified for opera­tion from 0 V to –2.7 V.

3 GND Ground.
4 CS Chip Select Input, Active Low. When CS

returns high, data will be loaded into the

DAC register.
5 SDI Serial Data Input.
6 CLK Serial Clock Input, positive edge triggered.
7 SHDN Active Low Input. Terminal A open circuit.

Shutdown controls Variable Resistors of

RDAC to temporary infinite.
8V

DD

Positive Power Supply (Sum of VDD + V

SS

≤ 5.5 V).
9 W Wiper Terminal.
10 A A Terminal.

PIN CONFIGURATION

ORDERING GUIDE

Temperature Package Package Full Branding

Model RES k Range Description Option Reel Qty. Information

AD5200BRM10-REEL7 256 10 –40°C/+85°C µSOIC-10 RM-10 5000 DLA
AD5200BRM50-REEL7 256 50 –40°C/+85°C µSOIC-10 RM-10 5000 DLB
AD5201BRM10-REEL7 33 10 –40°C/+85°C µSOIC-10 RM-10 5000 DMA
AD5201BRM50-REEL7 33 50 –40°C/+85°C µSOIC-10 RM-10 5000 DMB

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

WARNING!

the AD5200/AD5201 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. B

–5–

ESD SENSITIVE DEVICE

AD5200/AD5201–Typical Performance Characteristics

0.20

0.15

0.10

0.05

0.00

RDNL – LSB

0.05

0.10

0.15

0.20

VDD = +2.7V, VSS = –2.7V

VDD = 5.5V, VSS = 0V

CODE – Decimal

TPC 1. AD5200 10 kΩ RDNL vs. Code

0.03

V

= 5.5V, VSS = 0V

0.02

0.01

0.00

RDNL – LSB

–0.01

–0.02

–0.03

DD

= +2.7V, VSS = –2.7V

V

DD

CODE – Decimal

TPC 2. AD5201 10 kΩ RDNL vs. Code

VDD = 2.7V, VSS = 0V

224

1921601289664320 256

0.12

0.10

0.08

0.06

0.04

RINL – LSB

0.02

0.00

–0.02

TPC 4. AD5201 10 kΩ RINL vs. Code

0.10

VDD = 2.7V, VSS = 0V

28

2420161284032

0.05

0.00

–0.05

–0.10

DNL – LSB

–0.15

–0.20

–0.25

–0.30

TPC 5. AD5200 10 kΩ DNL vs. Code

VDD = +2.7V

= –2.7V

V

SS

VDD = 2.7V, VSS = 0V

CODE – Decimal

VDD = 2.7V, VSS = 0V

VDD = 5.5V, VSS = 0V

CODE – Decimal

V

= 5.5V, VSS = 0V

DD

28

2420161284032

VDD = +2.7V, VSS = –2.7V

224

1921601289664320 256

0.7

0.6

0.5

0.4

0.3

= 5.5V, VSS = 0V

V

RINL – LSB

–0.1

0.2

0.1

0.0

= +2.7V, VSS = –2.7V

V

DD

DD

CODE – Decimal

TPC 3. AD5200 10 kΩ RINL vs. Code

VDD = 2.7V, VSS = 0V

224

1921601289664320 256

–6–

0.020

0.015

0.010

VDD = +2.7V, VSS = –2.7V

0.005

DNL – LSB

0.000

–0.005

–0.010

VDD = 2.7V, VSS = 0V

CODE – Decimal

TPC 6. AD5201 10 kΩ DNL vs. Code

VDD = 5.5V, VSS = 0V

28

2420161284032

REV. B

0.3

TEMPERATURE – C

I

DD

SUPPLY CURRENT – A

20

–40

18

16

14

12

10

8

6

4

2

0

–20 0 20 40 60 80 100

V

IL

= V

SS

V

IH

= V

DD

VDD = 5.5V

VDD = 2.7V

TEMPERATURE – C

I

A

SHUTDOWN CURRENT – nA

14

–40

12

10

8

6

4

2

0

–

2

–20 0 20 40 60 80 100

VDD = 5.5V

AD5200/AD5201

–0.1

INL – LSB

–0.2

–0.3

–0.4

–0.5

0.2

0.1

0.0

VDD = 5.5V, VSS = 0V

VDD = +2.7V, VSS = –2.7V

VDD = 2.7V, VSS = 0V

CODE – Decimal

TPC 7. AD5200 10 kΩ INL vs. Code

0.020

0.015

0.010

0.005

INL – LSB

0.000

VDD = +2.7V, VSS = –2.7V

224

1921601289664320 256

VDD = 5.5V, VSS = 0V

TPC 10. Supply Current vs. Temperature

–0.005

–0.010

TPC 8. AD5201 10 kΩ INL vs. Code

10

1.0

– mA

0.1

SS

/I

DD

I

0.01

IDD @ VDD/VSS = 3V/0V

0.001

TPC 9. Supply Current vs. Logic Input Voltage

REV. B

VDD = 2.7V, VSS = 0V

CODE – Decimal

IDD @ VDD/VSS = 5V/0V

IDD @ VDD/VSS = 2.5V

ISS @ VDD/VSS = 2.5V

VIH – V

28

2420161284032

TPC 11. Shutdown Current vs. Temperature

160

140

120

100

– 

80

ON

R

60

40

20

0

5.04.03.02.01.00.0

06

VDD = 2.7V

V

SUPPLY

TPC 12. Wiper ON Resistance vs. V

–7–

SEE TEST CIRCUIT 13
T

= 25C

A

VDD = 5.5V

– V

54321

SUPPLY

AD5200/AD5201

500

450

CODE FF

H

400

350

300

– A

250

SS

/I

DD

I

200

150

100

50

0

10k

I

@ VDD/VSS = 3V/0V

DD

100k

FREQUENCY – Hz

I

@ VDD/V

SS

I

@ VDD/V

DD

I

@ VDD/VSS = 5V/0V

DD

= 2.5V

SS

= 2.5V

SS

1M 10M

TPC 13. AD5200 10 kΩ Supply Current vs. Clock Frequency

500

450

400

350

300

– A

250

SS

/I

DD

I

200

150

100

50

0

10k

I

SS

I

DD

I

@ VDD/VSS = 5V/0V

DD

@ VDD/VSS = 3V/0V

I

DD

100k

FREQUENCY – Hz

@ VDD/V

@ VDD/V

CODE 55

H

= 2.5V

SS

= 2.5V

SS

1M 10M

TPC 14. AD5200 10 kΩ Supply Current vs. Clock Frequency

6

0

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

GAIN – dB

–6

–12

–18

–24

–30

–36

–42

–48

–54

1k 10k 100k

FREQUENCY – Hz

1M

TPC 16. AD5200 10 kΩ Gain vs. Frequency vs. Code

6

0

80

–6

–12

–18

–24

GAIN – dB

–30

–36

–42

–48

–54

1k 10k 100k

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY – Hz

1M

TPC 17. AD5200 50 kΩ Gain vs. Frequency vs. Code

80

60

– dB

40

PSRR

+PSRR @ V

= 3V DC 10% p-p AC

DD

CODE = 80H, VA = VDD, VB = 0V

+PSRR @ V

= 5V DC 10% p-p AC

DD

20

@ V

= 3V DC 10% p-p AC

DD

1k 10k

FREQUENCY – Hz

100k

1M

0

–PSRR

100

TPC 15. Power Supply Rejection Ratio vs. Frequency

–8–

6

0

10

H

8

H

4

H

2

H

1

H

GAIN – dB

–6

–12

–18

–24

–30

–36

–42

–48

–54

1k 10k 100k

FREQUENCY – Hz

1M

TPC 18. AD5201 10 kΩ Gain vs. Frequency vs. Code

REV. B

AD5200/AD5201

FREQUENCY – Hz

12

–48

NORMALIZED GAIN FLATNESS – 0.1dB/DIV

10

10k 100k

1M

–42

–36

–30

–24

–18

–12

–6

0

6

100

1k

50k

10k

SEE TEST CIRCUIT 10
CODE = 10

H

V

DD

= 5V

T

A

= 25C

6

0

–6

–12

–18

–24

GAIN – dB

–30

–36

–42

–48

–54

1k 10k 100k

10

H

8

H

4

H

2

H

1

H

FREQUENCY – Hz

1M

TPC 19. AD5201 50 kΩ Gain vs. Frequency vs. Code

12

6

0

–6

–12

–18

GAIN – dB

–24

–30

–36

–42

–48

1k 10k 100k

FREQUENCY – Hz

V

IN

V

DD

R

L

10k

50k

= 100mV rms

= 5V

= 1M

1M

TPC 20. AD5200 –3 dB Bandwidth

12

SEE TEST CIRCUIT 10

6

0

–6

–12

–18

–24

–30

–36

–42

NORMALIZED GAIN FLATNESS – 0.1dB/DIV

–48

10

CODE = 80
V
T

DD

= 25C

A

= 5V

100

H

50k

1k

FREQUENCY – Hz

10k 100k

10k

1M

TPC 22. Normalized Gain Flatness vs. Frequency

TPC 23. AD5201 Normalized Gain Flatness vs. Frequency

REV. B

12

6

0

–6

–12

–18

GAIN – dB

–24

–30

–36

–42

–48

1k 10k 100k

FREQUENCY – Hz

TPC 21. AD5201 –3 dB Bandwidth

V

= 100mV rms

IN

V

= 5V

DD

R

= 1M

L

10k

50k

1M

–9–

V

W

(20mV/DIV)

CS

(5V/DIV)

TPC 24. One Position Step Change at Half Scale

AD5200/AD5201

OUTPUT

(2V/DIV)

INPUT

(5V/DIV)

TPC 25. Large Signal Settling Time

3500

3000

2500

2000

1500

1000

500

RHEOSTAT MODE TEMPCO – ppm/C

0

500

0

32 64 96 128 160 192 224 256

CODE – Decimal

TPC 28. AD5200 ∆RWB/∆T Rheostat Mode Temperature
Coefficient

3000

2500

2000

TPC 26. Digital Feedthrough vs. Time

4000

3500

3000

2500

2000

1500

1000

500

0

POTENTIOMETER MODE TEMPCO – ppm/C

500

0

32 64 96 128 160 192 224 256

CODE – Decimal

TPC 27. AD5200 ∆VWB/∆T Potentiometer Mode
Temperature Coefficient

V

OUT

(20mV/DIV)

1500

1000

500

0

POTENTIOMETER MODE TEMPCO – ppm/C

–

500

0

4 8 12 16 20 24 28 32

CODE – Decimal

TPC 29. AD5201 Potentiometer Mode Temperature
Coefficient

50

40

30

20

10

0

–1

0

POTENTIOMETER MODE TEMPCO – ppm/C

–

20

0

4 8 12 16 20 24 28 32

CODE – Decimal

TPC 30. AD5201 ∆VWB/∆T Potentiometer Mode Tempco

–10–

REV. B

AD5200/AD5201

100.0

10.0

– mA

MAX

RAB = 10k

1.0

THEORETICAL I

RAB = 50k

0.1
032

100.0

10.0

– mA

MAX

1.0

THEORETICAL I

0.1

04

64 96 128

CODE – Decimal

TPC 31. AD5200 I

RAB = 10k

RAB = 50k

812

16

CODE – Decimal

TPC 32. AD5201 I

160

vs. Code

MAX

20 24

vs. Code

MAX

192 224 256

28

32

OPERATION

The AD5200/AD5201 provide 255 and 33 positions digitally­controlled variable resistor (VR) devices. Changing the
programmed VR settings is accomplished by clocking in an 8-bit
serial data word for AD5200, and a 6-bit serial data word for
AD5201, into the SDI (Serial Data Input) pins. Table I provides
the serial register data word format. The AD5200/AD5201 are
preset to a midscale internally during power-on condition. In
addition, the AD5200/AD5201 contain power shutdown
SHDN pins that place the RDAC in a zero power consump­tion state where the immediate switches next to Terminals A and
B are open-circuited. Meanwhile, the wiper W is connected to B
terminal, resulting in only leakage current consumption in the VR
structure. During shutdown, the VR latch contents are maintained
when the RDAC is inactive. When the part is returned from
shutdown, the stored VR setting will be applied to the RDAC.

Table I. AD5200 Serial-Data Word Format

7B6B5B4B3B2B1B0B

7D6D5D4D3D2D1D0D

BSMBSL

7

2

0

2

Table II. AD5201 Serial-Data Word Format

5B * 4B3B2B1B0B

5D * 4D3D2D1D0D

BSMBSL

5

2

*Six data bits are needed for 33 positions.

0

2

PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation

The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 kΩ and 50 kΩ. The final two
digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10 and 50 kΩ = 50. The nominal resistance

) of AD5200 has 256 contact points accessed by the wiper

(R

AB

terminal. The 8-bit data word in the RDAC latch of AD5200 is
decoded to select one of the 256 possible settings. In both parts,
the wiper’s first connection starts at the B terminal for data 00

.

H

This B-terminal connection has a wiper contact resistance of
50 Ω as long as valid V

is applied, regardless of the nominal

DD/VSS

resistance. For a 10 kΩ part, the second connection of AD5200 is
the first tap point with 89 Ω [R
for data 01

. The third connection is the next tap point representing

H

78 + 50 = 128 Ω for data 02

= RAB/255 + RW = 39 Ω + 50 Ω]

WB

. Due to its unique internal structure,

H

AD5201 has 5-bit + 1 resolution, but needs a 6-bit data word to
achieve the full 33 steps resolution. The 6-bit data word in the
RDAC latch is decoded to select one of the 33 possible settings.
Data 34 to 63 will automatically be equal to Position 33. The
wiper 00

connection of AD5201 gives 50 Ω. Similarly, for a

H

10 kΩ part, the first tap point of AD5201 yields 363 Ω for
data 01

, 675 Ω for data 02H. For both AD5200 and AD5201,

H

each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached. Figures 2a and 2b show
the simplified diagrams of the equivalent RDAC circuits.

REV. B

–11–

AD5200/AD5201

A

SHDN

D7
D6
D5
D4
D3
D2
D1
D0

RDAC

LATCH &

DECODER

R

R

R

SHDN

SW

SW

2N1

SW

2N2

SW

1

SW

DIGITAL CIRCUITRY

B

OMITTED FOR CLARITY

R

0

W

R

AB

2N–1

Figure 2a. AD5200 Equivalent RDAC Circuit. 255 positions

SHDN

N

2

2N1

2N2

1

0

2N–1

.

W

R

AB

R

N

2

N

.

2

can be achieved up to Switch SW

A

SHDN

D5
D4
D3
D2
D1
D0

RDAC

LATCH &

DECODER

SW

SW

R

SW

R

SW

SW

R

SW

R

DIGITAL CIRCUITRY

B

OMITTED FOR CLARITY

Figure 2b. AD5201 Equivalent RDAC Circuit. Unlike AD5200,
33 positions can be achieved all the way to Switch SW

The general equation determining the digitally programmed
output resistance between W and B is:

Note D in AD5200 is between 0 to 255 for 256 positions. On
the other hand, D in AD5201 is between 0 to 32 so that 33
positions can be achieved due to the slight internal structure
difference, Figure 2b.

Again if R

= 10 kΩ and A terminal can be opened or tied to

AB

W, the following output resistance between W to B will be set
for the following RDAC latch codes:

AD5200 Wiper-to-B Resistance

DR

WB

(DEC) () Output State

255 10050 Full-Scale (R

+ RW)

AB

128 5070 Midscale
189 1 LSB
0 50 Zero-Scale (Wiper Contact Resistance)

AD5201 Wiper-to-B Resistance

DR

WB

(DEC) () Output State

32 10050 Full-Scale (R

+ RW)

AB

16 5050 Midscale
1 363 1 LSB
0 50 Zero-Scale (Wiper Contact Resistance)

Note that in the zero-scale condition a finite wiper resistance of
50 Ω is present. Care should be taken to limit the current flow
between W and B in this state to no more than ±20 mA to avoid
degradation or possible destruction of the internal switch contact.

Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
Terminal A also produces a digitally controlled resistance R

WA

.
When these terminals are used, the B terminal should be tied to
the wiper. Setting the resistance value for R

starts at a maxi-

WA

mum value of resistance and decreases as the data loaded in
the latch is increased in value. The general equation for this
operation is:

RDDR

RDDR

=+

()

WB AB

WB AB

255

=+

()

32

50 Ω

50 Ω

for AD5200 (1)

for AD5201 (2)

where:

D is the decimal equivalent of the data contained in

RDAC latch.

R

is the nominal end-to-end resistance.

AB

R

is the wiper resistance contributed by the on-resistance

W

of the internal switch.

D

−

255

RD

WA AB

RD

WA AB

()

=

()

()

255

D

−

32

()

=

32

R

+

50 Ω

R

+

50 Ω

for AD5200 (3)

for AD5201 (4)

Similarly, D in AD5200 is between 0 to 255, whereas D in
AD5201 is between 0 to 32.

For R

= 10 kΩ and B terminal is opened or tied to the wiper

AB

W, the following output resistance between W and A will be set
for the following RDAC latch codes:

–12–

REV. B

AD5200/AD5201

AD5200 Wiper-to-A Resistance

DR

WA

(DEC) () Output State

255 50 Full-Scale (R

)

W

128 5030 Midscale
1 10011 1 LSB
0 10050 Zero-Scale (RAB + RW)

AD5201 Wiper-to-A Resistance

DR

WA

(DEC) () Output State

32 50 Full-Scale (R

)

W

16 5050 Midscale
1 9738 1 LSB
0 10050 Zero-Scale (RAB + RW)

The tolerance of the nominal resistance can be ±30% due to
process lot dependance. If users apply the RDAC in rheostat
(variable resistance) mode, they should be aware of such specifi­cation of tolerance. The change in R

with temperature has a

AB

500 ppm/°C temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation

The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input volt­age at A to B.

Unlike the polarity of V

– VSS, which must be positive, volt-

DD

age across A–B, W–A, and W–B can be at either polarity.

If ignoring the effects of the wiper resistance for an approxima­tion, connecting A terminal to 5 V and B terminal to ground
produces an output voltage at the wiper which can be any value
starting at almost zero to almost full scale with the minor devia­tion contributed by the wiper resistance. Each LSB of voltage is
equal to the voltage applied across Terminal AB divided by the

N-1

2

and 2N position resolution of the potentiometer divider for
AD5200 and AD5201 respectively. The general equation defin­ing the output voltage with respect to ground for any valid input
voltage applied to Terminals A and B is:

Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Here the output
voltage is dependent on the ratio of the internal resistors and not
the absolute values; therefore, the drift reduces to 15 ppm/°C.

DIGITAL INTERFACING

The AD5200/AD5201 contain a standard three-wire serial input
control interface. The three inputs are clock (CLK), CS, and
serial data input (SDI). The positive-edge-sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means.
Figure 3 shows more detail of the internal digital circuitry. When
CS is low, the clock loads data into the serial register on each
positive clock edge (see Table III).

V

CS

CLK

SDI

GND

DD

AD5200/AD5201

PWR-ON
PRESET

SER

REG

RDAC

8/6

Dx

REG

V

SS

A

W

B

SHDN

Figure 3. Block Diagram

Table III. Input Logic Control Truth Table

CLK CS SHDN Register Activity

L L H No SR effect.
P L H Shift one bit in from the SDI pin.
X P H Load SR data into RDAC latch.
X H H No operation.
X H L Open circuit on A terminal and short

circuit between W to B terminals.

NOTE
P = positive edge, X = don’t care, SR = shift register.

All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 4. Applies to
digital input pins CS, SDI, SHDN, CLK.

VD

WABB

VDDVV

WABB

D

VV

=+

()

255

=+

()

32

for AD5200 (5)

for AD5201 (6)

where D in AD5200 is between 0 to 255 and D in AD5201 is
between 0 to 32.

For more accurate calculation, including the effects of wiper
resistance, V

VD

W

where R

can be found as:

W

RD

WB

()+()

=

()

WB

R

AB

(D) and RWA(D) can be obtained from Equations

V

A

RD

WA

R

AB

V

B

(7)

1 to 4.

REV. B

–13–

340

LOGIC

V

SS

Figure 4. ESD Protection of Digital Pins

A,B,W

V

SS

Figure 5. ESD Protection of Resistor Terminals

AD5200/AD5201

W

B

VSS TO V

DD

DUT

I

SW

CODE = OO

H

R

SW

=

0.1V
I

SW

0.1V

+

–

I

CM

A

W

B

NC

GND

NC

V

SS

V

DD

DUT

V

CM

NC = NO CONNECT

TEST CIRCUITS

Figures 6 to 14 define the test conditions used in the product
specification table.

DUT

V+ = V

DD

1 LSB = V+/2

A

V+

W

B

N

V

MS

Figure 6. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)

NO CONNECT

DUT

A

B

W

I

W

V

MS

Figure 7. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)

DUT

V

MS2

A

W

B

V

W

IW = VDD/R

V

MS1

NOMINAL

5V

OFFSET

GND

V

IN

A DUT

OFFSET BIAS

OP279

W

B

V

OUT

Figure 11. Noninverting Gain Test Circuit

+15V

W

OP42

–15V

V

OUT

OFFSET

GND

A

V

IN

B

2.5V

Figure 12. Gain vs. Frequency Test Circuit

RW = [V

MS1

– V

MS2

]/I

W

Figure 8. Wiper Resistance Test Circuit

V

A

V

DD

V+

A

W

B

V

MS

V+ = V

10%

DD

PSRR (dB) = 20 LOG

PSS (%/%) =

VMS%

VDD%

V

V

MS

DD

Figure 9. Power Supply Sensitivity Test Circuit
(PSS, PSRR)

OFFSET

GND

V

IN

A DUT

B

W

OFFSET BIAS

OP279

5V

V

OUT

Figure 10. Inverting Gain Test Circuit

Figure 13. Incremental ON Resistance Test Circuit

Figure 14. Common-Mode Leakage Current Test Circuit

–14–

REV. B

AD5200/AD5201

DIGITAL POTENTIOMETER SELECTION GUIDE

Number Resolution Power
of VRs Terminal Interface Nominal (Number Supply

Part per Voltage Data Resistance Of Wiper Current
Number Package Range Control (k) Positions) (IDD) Packages Comments

AD5201 1 ± 3 V, +5.5 V 3-Wire 10, 50 33 60 µA µSOIC-10 Full AC Specs, Dual Supply,

Pwr-On-Reset, Low Cost

AD5220 1 5.5 V Up/Down 10, 50, 100 128 40 µA PDIP, SO-8, µSOIC-8 No Rollover, Pwr-On-Reset

AD7376 1 ± 15 V, +28 V 3-Wire 10, 50, 100, 1000 128 100 µA PDIP-14, SOL-16, Single 28 V or Dual ±15 V

TSSOP-14 Supply Operation

AD5200 1 ± 3 V, +5.5 V 3-Wire 10, 50 256 60 µA µSOIC-10 Full AC Specs, Dual Supply,

Pwr-On-Reset

AD8400 1 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA SO-8 Full AC specs

AD5241* 1 ± 3 V, +5.5 V 2-Wire 10, 100, 1000 256 5 µA SO-14, TSSOP-14 I2C-Compatible, TC

< 50 ppm/°C

AD5231* 1 ± 3 V, +5.5 V 3-Wire 10, 50, 100 1024 10 µA TSSOP-16 Nonvolatile Memory, Direct

Program, I/D, ±6 dB Settability

AD5222 2 ± 3 V, +5.5 V Up/Down 10, 50, 100, 1000 128 80 µA SO-14, TSSOP-14 No Rollover, Stereo, Pwr-On-

Reset, TC < 50 ppm/°C

AD8402 2 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SO-14, Full AC Specs, nA

TSSOP-14 Shutdown Current

AD5232* 2 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 10 µA TSSOP-16 Nonvolatile Memory, Direct

Program, I/D, ±6 dB Settability

AD5242* 2 ± 3 V, +5.5 V 2-Wire 10, 100, 1000 256 5 µA SO-16, TSSOP-16 I2C-Compatible, TC

< 50 ppm/°C

AD5262* 2 ± 5 V, +12 V 3-Wire 10, 50, 100 256 60 µA TSSOP-16 Medium Voltage Operation,

TC < 50 ppm/°C

AD5203 4 5.5 V 3-Wire 10, 100 64 5 µA PDIP, SOL-24, Full AC specs, nA

TSSOP-24 Shutdown Current

AD5233* 4 ± 3 V, +5.5 V 3-Wire 10, 50, 100 64 10 µA TSSOP-16 Nonvolatile Memory, Direct

Program, I/D, ±6 dB Settability

AD5204 4 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, Dual Supply,

TSSOP-24 Pwr-On-Reset

AD8403 4 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, nA

TSSOP-24 Shutdown Current

AD5206 6 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, Dual Supply,

TSSOP-24 Pwr-On-Reset

*Future product, consult factory for latest status.

REV. B

–15–

AD5200/AD5201

0.124 (3.15)

0.112 (2.84)

0.038 (0.97)

0.030 (0.76)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

10-Lead SOIC

(RM-10)

0.124 (3.15)

0.112 (2.84)

6

10

PIN 1

0.0197 (0.50) BSC

0.122 (3.10)

0.110 (2.79)

0.006 (0.15)

0.002 (0.05)

1

5

0.016 (0.41)

0.006 (0.15)

0.199 (5.05)

0.187 (4.75)

0.043 (1.09)

0.037 (0.94)

SEATING
PLANE

0.011 (0.28)

0.003 (0.08)

0.120 (3.05)

0.112 (2.84)

6
0

C02188–0–8/01(B)

0.022 (0.56)

0.021 (0.53)

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

02/01—Data Sheet changed from REV. O to REV. A.

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

TPCs 31 and 32 added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

–16–

REV. B

PRINTED IN U.S.A.