Datasheet AD5174 Datasheet (ANALOG DEVICES)

Single-Channel, 1024-Position, Digital Rheostat

V

FEATURES

Single-channel, 1024-position resolution
10 kΩ nominal resistance
50-times programmable (50-TP) wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C

2.7 V to 5.5 V single-supply operation
±2.5 V to ±2.75 V dual-supply operation for ac or bipolar

operations
SPI-compatible interface
Wiper setting and memory readback
Power on refreshed from memory
Resistor tolerance stored in memory
Thin LFCSP 10-lead, 3 mm × 3 mm× 0.8 mm package
Compact MSOP, 10-lead, 3 mm × 4.9 mm × 1.1 mm package

APPLICATIONS

Mechanical rheostat replacements
Op-amp: variable gain control
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversions
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration

with SPI Interface and 50-TP Memory

AD5174

FUNCTIONAL BLOCK DIAGRAM

DD

POWER-ON

SCLK

SYNC

DIN

SDO

RESET

SPI

SERIAL

INTERFACE

V

SS

REGISTER

10

50-TP

MEMORY

BLOCK

EXT_CAP GND

Figure 1.

AD5174

RDAC

A

W

08718-001

GENERAL DESCRIPTION

The AD5174 is a single-channel, 1024-position digital rheostat
that combines industry leading variable resistor performance
with nonvolatile memory (NVM) in a compact package.

This device supports both dual-supply operation at ±2.5 V to
±2.75 V and single-supply operation at 2.7 V to 5.5 V and offers
50-times programmable (50-TP) memory.

The AD5174 device wiper settings are controllable through the
SPI digital interface. Unlimited adjustments are allowed before
programming the resistance value into the 50-TP memory. The
AD5174 does not require any external voltage supply to facili­tate fuse blow and there are 50 opportunities for permanent
programming. During 50-TP activation, a permanent blow fuse
command freezes the resistance position (analogous to placing
epoxy on a mechanical rheostat).

The AD5174 is available in a 3 mm × 3mm 10-lead LFCSP
package and in a 10-lead MSOP package. The part is guaranteed
to operate over the extended industrial temperature range of

−40°C to +125°C.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

AD5174

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

Interface Timing Specifications.................................................. 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits..................................................................................... 11

Theory of Operation ...................................................................... 12

Serial Data Interface................................................................... 12

Shift Register............................................................................... 12

RDAC Register............................................................................ 12

50-TP Memory Block ................................................................ 12

Write Protection ......................................................................... 12

RDAC and 50-TP Read Operation .......................................... 13

Shutdown Mode ......................................................................... 14

Reset ............................................................................................. 14

SDO Pin and Daisy-Chain Operation..................................... 15

RDAC Architecture.................................................................... 16

Programming the Variable Resistor......................................... 16

EXT_CAP Capacitor.................................................................. 17

Terminal Voltage Operating Range ......................................... 17

Power-Up Sequence ................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

12/10—Rev. A to Rev. B

Changes to SDO Pin Description................................................... 7

Changes to SDO Pin and Daisy-Chain Operation Section....... 15

7/10—Rev. 0 to Rev. A

Changes to Daisy-Chain Operation Section including Changing

Title to SDO Pin and Daisy-Chain Operation Section ............. 15

Added Table 11 ...............................................................................15

Changes to Ordering Guide.......................................................... 18

3/10—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD5174

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < 125°C, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution 10 Bits

Resistor Integral Nonlinearity

|VDD − VSS| = 3.3 V to 3.6 V −1 +1.5 LSB

|VDD − VSS| = 2.7 V to 3.3 V −2.5 +2.5 LSB
Resistor Differential Nonlinearity2 R-DNL
Nominal Resistor Tolerance ±15 %
Resistance Temperature Coefficient
Wiper Resistance Code = zero scale 35 70 Ω

RESISTOR TERMINALS

Terminal Voltage Range
Capacitance A4 f = 1 MHz, measured to GND, code = half scale 90 pF
Capacitance W4 f = 1 MHz, measured to GND, code = half scale 40 pF
Common-Mode Leakage Current4 V

DIGITAL INPUTS

Input Logic4

High V

Low V
Input Current IIN ±1 μA
Input Capacitance4 C

DIGITAL OUTPUT

Output Voltage4

High VOH R

Low VOL R
V
V
Tristate Leakage Current −1 +1 μA
Output Capacitance4 5 pF

POWER SUPPLIES

Single-Supply Power Range VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range ±2.5 ±2.75 V
Supply Current

Positive IDD 1 μA

Negative ISS −1 μA
50-TP Store Current

Positive I

Negative I
50-TP Read Current

4, 8

Positive I

Negative I
Power Dissipation9 P
Power Supply Rejection Ratio4 PSRR ΔVDD/ΔVSS = ±5 V ± 10% −50 −55 dB

2, 3

R-INL |VDD − VSS| = 3.6 V to 5.5 V −1 +1 LSB

4, 5

Code = full scale 35 ppm/°C

4, 6

V

4, 7

V

TERM

= VW 50 nA

A

2.0 V

INH

0.8 V

INL

5 pF

IN

= 2.2 kΩ to VDD V

PULL_UP

= 2.2 kΩ to VDD

PULL_UP

= 2.7 V to 5.5 V, VSS = 0 V 0.4 V

DD

= 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V

DD

DD_OTP_STORE

SS_OTP_STORE

4 mA

−4 mA

−1 +1 LSB

V

SS

− 0.1 V

DD

V

DD

DD_OTP_READ

SS_OTP_READ

DISS

500 μA

−500 μA

VIH = VDD or VIL = GND 5.5 μW

Rev. B | Page 3 of 20

AD5174

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB, RAW = 5 kΩ, Terminal W, see Figure 24 700 kHz
Total Harmonic Distortion VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ −90 dB
Resistor Noise Density RWB = 5 kΩ, TA = 25°C, f = 10 kHz 13 nV/√Hz

1

Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions.

3

The maximum current in each code is defined by IAW = (VDD − 1)/RAW.

4

Guaranteed by design and not subject to production test.

5

See Figure 9 for more details.

6

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

7

Different from operating current; the supply current for the fuse program lasts approximately 55 ms.

8

Different from operating current; the supply current for the fuse read lasts approximately 500 ns.

9

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

10

All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.

INTERFACE TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V; all specifications T

Table 2.

Parameter Limit1 Unit Test Conditions/Comments

2

t

20 ns min SCLK cycle time

1

t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 15 ns min

t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 1 ns min

3

t

400 ns min

8

t9 15 ns min

4

t

450 ns max SCLK rising edge to SDO valid

10

t

MEMORY_READ

t

MEMORY_PROGRAM

t

RESET

t

POWER-UP

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 50 MHz.

3

Refer to t

4

R

PULL_UP

5

Maximum time after VDD − VSS is equal to 2.5 V.

6 μs max Memory readback execute time

350 ms max Memory program time

600 μs max Reset OTP restore time

5

2 ms max Power-on 50-TP restore time

and

MEMORY_READ

= 2.2 kΩ to VDD with a capacitance load of 168 pF.

t

MEMORY_PROGRAM

4, 10

to SCLK falling edge setup time

SYNC

SCLK falling edge to SYNC
Minimum SYNC

rising edge to next SCLK fall ignored

SYNC

for memory commands operations.

MIN

high time

to T

rising edge

, unless otherwise noted.

MAX

Rev. B | Page 4 of 20

AD5174

Shift Register and Timing Diagrams

DB9 (MSB) DB0 (LSB)

C0C1

D9

D7 D6 D5 D4 D3

D8

DATA BITS

Figure 2. Shift Register Content

t

5

D2 D1

t

6

D0

08718-002

t

7

t

9

SCLK

SYNC

DIN

C3

00

t

4

t

8

t

2

t

3

0 0 C3 C2 D7 D6 D5 D2 D1 D0

C2

CONTROL BITS

t

1

SDO

SCLK

SYNC

DIN

SDO

Figure 3. Write Timing Diagram, CPOL=0, CPHA = 1

00 00C3 C3

X X C3 D1 D0

Figure 4. Read Timing Diagram, CPOL=0, CPHA = 1

08718-003

t

9

D1 D0D0 D0

t

10

08718-004

Rev. B | Page 5 of 20

AD5174

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7.0 V
VSS to GND +0.3 V to −7.0 V
VDD to VSS 7 V
VA, VW to GND VSS − 0.3 V, VDD + 0.3 V
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
EXT_CAP to VSS 7 V
IA, IW

Pulsed1

Frequency > 10 kHz ±6 mA/d2
Frequency ≤ 10 kHz ±6 mA/√d2

Continuous ±6 mA
Operating Temperature Range3 −40°C to +125°C
Maximum Junction Temperature

(T

Maximum)

J

150°C

Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A and W terminals at a given
resistance.

2

Pulse duty factor.

3

Includes programming of 50-TP memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.

Table 4. Thermal Resistance

Package Type θ

10-Lead LFCSP 50 3 °C/W
10-Lead MSOP 135 N/A °C/W

1

JEDEC 2S2P test board, still air (0 m/sec airflow).

ESD CAUTION

1

θJC Unit

JA

Rev. B | Page 6 of 20

AD5174

1

2

3

4

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

10
9
8
7
6

SYNC

SCLK
DIN
SDO
GND

SS

.

08718-103

VDD1

2

V

V

EXT_CAP

DD

A

W

SS

1

AD5174

2
3

TOP VIEW

4

(Not to Scale)

5

A

10

SYNC

9

SCLK

8

DIN

7

SDO

6

GND

08718-005

W

V

SS

EXT_CAP

*LEAVE FLOATING O R CONNECTED TO V

AD5174

3

(EXPOSED

4
5

PAD)*

Figure 5. MSOP Pin Configuration Figure 6. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
2 A Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3 W Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
4 VSS

Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors
and 10 μF capacitors.

5 EXT_CAP

External Capacitor. Connect a 1 μF capacitor between EXT_CAP and V

. This capacitor must have a voltage

SS

rating of ≥7 V.
6 GND Ground Pin, Logic Ground Reference.
7 SDO

Serial Data Output. This pin can be used to clock data from the shift register in daisy-chain mode or in readback

mode. This open-drain output requires an external pull-up resistor even if it is not use.
8 DIN

Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit

input register.
9 SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be

transferred at rates of up to 50 MHz.
10

Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC

SYNC

goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks.

The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken

high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored

by the RDAC.
EPAD Exposed Pad Leave floating or connected to VSS

Rev. B | Page 7 of 20

AD5174

TYPICAL PERFORMANCE CHARACTERISTICS

0.8

0.6

0.4

+25°C
–40°C
+125°C

1.0

0.8

VDD/VSS = 5V/0V

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

0 128 256 384 512 640 768 896 1023

CODE (Decimal)

Figure 7. R-INL vs. Code vs. Temperature

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

+25°C
–40°C
+125°C

0 128 256 384 512 640 768 896 1023

CODE (Decimal)

Figure 8. R-DNL vs. Code vs. Temperature

700

600

500

400

300

200

100

RHEOSTAT MO DE T EMPCO (ppm/ °C)

VDD/VSS = 5V/0V

0.6

0.4

CURRENT (mA)

0.2

0

08718-014

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VOLTAGE (V)

Figure 10. Supply Current (I

) vs. Digital Input Voltage

DD

8718-023

500

400

300

200

100

0

–100

CURRENT (nA)

–200

–300

–400

–500

–40 –30 –20 –10 0 20 30 40 50 60 70 80 90 100 11010

08718-015

ISS = 3V

TEMPERATURE (°C)

Figure 11. Supply Current (I

IDD = 5V

IDD = 3V

ISS = 5V

, ISS) vs. Temperature

DD

08718-018

7

6

5

(mA)

4

WA_MAX

3

2

THEORETI CAL l

1

VDD/VSS = 5V/0V

0

0 128 256 384 512 640 768 896 1023

CODE (Decimal)

Figure 9. Tempco ΔR

/ΔT vs. Code

WA

08718-019

Rev. B | Page 8 of 20

0

0 1023850765 935680510 595340 425170 25585

CODE (Decimal )

Figure 12. Theoretical Maximum Current vs. Code

08718-028

AD5174

–

20

GAIN (dB)

0

0x200

–5

–10

0x100

–15

0x080

–20

0x040

–25

0x020

–30

0x010

–35

0x008

–40

0x004
0x002

–45

0x001

–50

1 10M1M100k10k1k10010

FREQUENCY (Hz)

Figure 13. Bandwidth vs. Frequency vs. Code

VDD/VSS = 5V/0V

PSRR (dB)

08718-031

VDD/VSS = 5V/0V

–25

CODE = HALF SCALE

–30

–35

–40

–45

–50

–55

–60

10 100 1M100k10k1k

Figure 16. PSRR vs. Frequency

FREQUENCY (Hz)

08718-024

0

V

= ±2.5V

DD/VSS

CODE = HALF S CAL E
f

= 1V rms

IN

–20

NOISE BW = 22kHz

–40

–60

THD + N (dB)

–80

–100

–120

10 100 1k 10k

FREQUENCY (Hz)

Figure 14. THD + N vs. Frequency

0

–20

–40

–60

THD + N (dB)

–80

–100

0.001 0.01 0.1 1

= ±2.5V

V

DD/VSS

CODE = HALF SCA LE

f

= 1kHz

IN

NOISE BW = 22 kHz

AMPLITUDE ( V rms)

Figure 15. THD + N vs. Amplitude

100k

10kΩ

1M

8

7

6

VOLTAGE (V)

5

4

0.07 0.09 0.11 0.13 0.15 0.17

08718-039

Figure 17. V

TIME (Seco nds)

Waveform While Writing Fuse

EXT_CAP

8718-029

20

10

0

–10

–20

–30

–40

GLITCH AMPLITUDE (mV)

–50

–60

–70

08718-026

–2 420

TIME (µs)

VDD/VSS = ±2.5V
I

= 200µA

AW

08718-102

Figure 18. Maximum Glitch Energy

Rev. B | Page 9 of 20

AD5174

R

1.0

0.5

0.006

0.005

0.004

VDD/VSS = 5V/0V
I

= 10µA

AW

CODE = HALF S CAL E

0.003

0.002

RESISTANCE (%)

0.001

AW

∆

0

–0.001

–0.002

0 1000900800700600500400300200100

OPERATION AT 150°C (Hours)

Figure 20. Long-Term Drift Accelerated Average by Burn-In

08718-101

–0.5

VOLTAGE (mV)

–1.0

–1.5

0

–10 6050403020100

TIME (µs)

Figure 19. Digital Feedthrough

VDD/VSS = ±2.5V
I

= 200µA

AW

08718-100

Rev. B | Page 10 of 20

AD5174

V

V

%

TEST CIRCUITS

Figure 21 to Figure 25 define the test conditions used in the Specifications section.

DUT

W

A

I

W

V

MS

08718-033

Figure 21. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

MS

RWA =

I

W

CODE = 0x00

DUT

W

A

V

MS

R

RW =

WA

2

NC

08718-034

+2.75V –2.75V

I

W

Figure 22. Wiper Resistance

+ = VDD ±10

PSRR (dB) = 20 log

I

W

V

DD

V+

W

A

V

PSS (%/%) =

MS

∆VMS%

∆V

DD

V

MS

V

DD

%

08718-035

Figure 23. Power Supply Sensitivity (PSS, PSRR)

DUT

W

A

1GΩ

V

MS

V

08718-036

Figure 24. Gain vs. Frequency

DUT

I

CM

W

A

GND

GND

GND

NC = NO CONNECT

+2.75V
–2.75V

Figure 25. Common Leakage Current

08718-037

Rev. B | Page 11 of 20

AD5174

THEORY OF OPERATION

The AD5174 is designed to operate as a true variable resistor for
analog signals within the terminal voltage range of V
< V

. The RDAC register contents determine the resistor wiper

DD

position. The RDAC register acts as a scratchpad register, which
allows unlimited changes of resistance settings. The RDAC register
can be programmed with any position setting by using the SPI
interface. When a desirable wiper position is found, this value
can be stored in a 50-TP memory register. Thereafter, the wiper
position is always restored to that position for subsequent
power-ups. The storing of 50-TP data takes approximately 350 ms;
during this time, the AD5174 locks to prevent any changes from
taking place.

The AD5174 also feature a patented 1% end-to-end resistor
tolerance. This simplifies precision, rheostat mode, and open­loop applications where knowledge of absolute resistance is
critical.

SERIAL DATA INTERFACE

The AD5174 contains a serial interface (
and SDO) that is compatible with SPI interface standards, as well
as most DSPs. This device allows writing of data via the serial
interface to every register.

SYNC

SHIFT REGISTER

The shift register is 16 bits wide, as shown in Figure 2. The
16-bit word consists of two unused bits, which should be set to
0, followed by four control bits and 10 RDAC data bits. Data is
loaded MSB first (Bit D9). The four control bits determine the
function of the software command as listed in Tabl e 6. Figure 3
shows a timing diagram of a typical AD5174 write sequence.

The write sequence begins by bringing the
SYNC

pin must be held low until the complete data-word is
loaded from the DIN pin. When
data-word is decoded according to the instructions in .

The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5174 has an internal counter
that counts a multiple of 16 bits (a frame) for proper operation.
For example, AD5174 works with a 32-bit word but does not
work properly with a 31-bit or 33-bit word. The AD5174
does not require a continuous SCLK when
To minimize power consumption in the digital input buffers,
operate all serial interface pins close to the V

SYNC

SYNC

returns high, the serial

SYNC

DD

< V

SS

TERM

, SCLK, DIN,

line low. The

Tabl e 6

is high.

supply rails.

RDAC REGISTER

The RDAC register directly controls the position of the digital
rheostat wiper. For example, when the RDAC register is loaded
with all 0s, the wiper is connected to Terminal A of the variable
resistor. The RDAC register is a standard logic register, and there
is no restriction on the number of changes allowed. The basic
mode of setting the variable resistor wiper position (programming
the RDAC register) is accomplished by loading the serial data
input register with Command 1 (see Tab le 6 ) and with the desired
wiper position data.

50-TP MEMORY BLOCK

The AD5174 contains an array of 50-TP programmable memory
registers, which allow the wiper position to be programmed up
to 50 times. Tabl e 10 shows the memory map. When the desired
wiper position is determined, the user can load the serial data
input register with Command 3 (see Tab l e 6 ), which stores the
wiper position data in a 50-TP memory register. The first address
to be programmed is Location 0x01 (see Tab le 1 0); the AD5174
increments the 50-TP memory address for each subsequent
program until the memory is full. Programming data to 50-TP
consumes approximately 4 mA for 55 ms, and takes approx­imately 350 ms to complete, during which time the shift register
locks to prevent any changes from occurring. Bit C2 of the
control register can be polled to verify that the fuse program
command was completed properly. No change in supply voltage
is required to program the 50-TP memory; however, a 1 μF
capacitor on the EXT_CAP pin is required (see Figure 28).
Prior to 50-TP activation, the AD5174 presets to midscale
on power-up.

WRITE PROTECTION

At power-up, the serial data input register write commands for
both the RDAC register and the 50-TP memory registers are
disabled. The RDAC write protect bit, C1, of the control register
(see Tabl e 8 and Ta b le 9 ) is set to 0 by default. This disables any
change of the RDAC register content regardless of the software
commands, except that the RDAC register can be refreshed
from the 50-TP memory using the software reset, Command 4
(see Tabl e 6). To enable programming of the RDAC register,
the write protect bit (Bit C1), of the control register must first
be programmed by loading the serial data input register with
Command 7. To enable programming of the 50-TP memory,
the program enable bit (Bit C0) of the control register, which
is set to 0 by default, must first be set to 1.

Rev. B | Page 12 of 20

AD5174

RDAC AND 50-TP READ OPERATION

A serial data output SDO pin is available for readback of
the internal RDAC register or 50-TP memory contents. The
contents of the RDAC register can be read back through
SDO by using Command 2 (see Tab l e 6 ). Data from the
RDAC register is clocked out of the SDO pin during the last
10 clocks of the next SPI operation.

It is possible to read back the contents of any of the 50-TP
memory registers through SDO by using Command 5. The
lower six LSB bits, D5 to D0 of the data byte, select which
memory location is to be read back, as shown in Tabl e 10 .

Table 6. Command Operation Truth Table

Command
Number

0 0 0 0 0 X X X X X X X X X X NOP: do nothing.
1 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

2 0 0 1 0 X X X X X X X X X X

3 0 0 1 1 X X X X X X X X X X

4 0 1 0 0 X X X X X X X X X X

52 0 1 0 1 X X X X D5 D4 D3 D2 D1 D0

6 0 1 1 0 X X X X X X X X X X

73 0 1 1 1 X X X X X X X X D1 D0

8 1 0 0 0 X X X X X X X X X X Read contents of control register.
9 1 0 0 1 X X X X X X X X X D0 Software shutdown.
D0 = 0; normal mode.

1

X is don’t care.

2

See Table 10 for 50-TP memory map.

3

See Table 9 for bit details.

Command[DB13:DB10] Data[DB9:DB0]1
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Data from the selected memory location is clocked out of the
SDO pin during the next SPI operation. A binary encoded version
address of the most recently programmed wiper memory location
can be read back using Command 6 (see Tab le 6 ). This can be used
to monitor the spare memory status of the 50-TP memory block.

Tabl e 7 provides a sample listing for the sequence of serial data
input (DIN) words with the serial data output appearing at the
SDO pin in hexadecimal format for a write and read to both the
RDAC register and the 50-TP memory (Memory Location 20).

Operation

Write contents of serial register
data to RDAC.

Read contents of RDAC wiper
register.

Store wiper setting: store RDAC
setting to 50-TP.

Software reset: refresh RDAC with
last 50-TP memory stored value.

Read contents of 50-TP from SDO
output in the next frame.

Read address of last 50-TP
programmed memory location.

Write contents of serial register
data to control register.

D0 = 1; device placed in shutdown
mode.

Rev. B | Page 13 of 20

AD5174

SHUTDOWN MODE

The AD5174 can be shut down by executing the software
shutdown command, Command 9 (see Tabl e 6), and setting
the LSB to 1. This feature places the RDAC in a zero-power­consumption state where Terminal A is open circuited and
the wiper terminal, W, remains connected. It is possible to
execute any command from Ta b le 6 while the AD5174 is in
shutdown mode. The parts can be taken out of shutdown
mode by executing Command 9 and setting the LSB to 0
or by a software reset, Command 4 (see Tabl e 6 ).

Table 7. Write and Read to RDAC and 50-TP Memory

DIN SDO1 Action

0x1C03 0xXXXX Enable update of the wiper position and the 50-TP memory contents through the digital interface.
0x0500 0x1C03 Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.
0x0800 0x0500 Prepares data read from RDAC register.
0x0C00 0x100

0x1800 0x0C00 Prepares data read of the last programmed 50-TP memory monitor location.
0x0000 0xXX19

0x1419 0x0000 Prepares data read from Memory Location 0x19.
0x2000 0x0100

0x0000 0xXXXX

1

X is don’t care.

Stores RDAC register content into the 50-TP memory. A 16-bit word appears out of SDO, where the last 10 bits contain
the contents of the RDAC register (0x100).

NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs (that is, last six bits) contain the binary address of
the last programmed 50-TP memory location, for example, 0x19 (see Table 10).

Prepares data read from the control register. Sends a 16-bit word out of SDO, where the last 10 bits contain the
contents of Memory Location 0x19.

NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register.
If Bit C2 = 1, the fuse program command was successful.

RESET

The AD5174 can be reset through software by executing Com­mand 4 (see Tabl e 6). The reset command loads the RDAC
register with the contents of the most recently programmed 50-TP
memory location. The RDAC register loads with midscale if no
50-TP memory location has been previously programmed.

Table 8. Control Register Bit Map

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 C2 0 C1 C0

Table 9. Control Register Bit Description

Bit Name Description

C0 50-TP program enable
0 = 50-TP program disabled (default)
1 = enable device for 50-TP program
C1 RDAC register write protect
0 = wiper position frozen to value in 50-TP memory (default)1
1 = allow update of wiper position through digital interface
C2 50-TP memory program success bit
0 = fuse program command was unsuccessful (default)
1 = fuse program command was successful

1

Wiper position frozen to the last value programmed in the 50-TP memory. The wiper is frozen to midscale if the 50-TP memory has not been previously programmed.

Rev. B | Page 14 of 20

AD5174

V

Table 10. Memory Map

Data Byte[DB9:DB0]1

Command Number

5

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X X 0 0 0 0 0 0 0 Reserved
X X X 0 0 0 0 0 0 1 1st programmed wiper location (0x01)
X X X 0 0 0 0 0 1 0 2nd programmed wiper location (0x02)
X X X 0 0 0 0 0 1 1 3rd programmed wiper location (0x03)
X X X 0 0 0 0 1 0 0 4th programmed wiper location (0x04)
… … … … … … … … … … …
X X X 0 0 0 1 0 1 0 10th programmed wiper location (0xA)
… … … … … … … … … … …
X X X 0 0 1 0 1 0 0 20th programmed wiper location (0x14)
… … … … … … … … … … …
X X X 0 0 1 1 1 1 0 30th programmed wiper location (0x1E)
… … … … … … … … … … …
X X X 0 1 0 1 0 0 0 40th programmed wiper location (0x28)
… … … … … … … … … … …
X X X 0 1 1 0 0 1 0 50th programmed wiper location (0x32)
… … … … … … … … … … …
X X X 0 1 1 1 0 0 1 MSB resistance tolerance (0x39)
X X X 0 1 1 1 0 1 0 LSB resistance tolerance (0x3A)

1

X is don’t care.

SDO PIN AND DAISY-CHAIN OPERATION

The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting and 50-TP values
using Command 2 and Command 5, respectively (see Ta b le 6 )
or the SDO pin can be used in daisy-chain mode. Data is
clocked out of SDO on the rising edge of SCLK. The SDO pin
contains an open-drain N-channel FET that requires a pull-up
resistor. To place the pin in high impedance and minimize the
power dissipation when the pin is used, the 0x8001 data word
followed by Command 0 should be sent to the part. Tab l e 1 1
provides a sample listing for the sequence of the serial data
input (DIN). Daisy chaining minimizes the number of port pins
required from the controlling IC. As shown in Figure 26, users
need to tie the SDO pin of one package to the DIN pin of the
next package. Users may need to increase the clock period,
because the pull-up resistor and the capacitive loading at the
SDO-to-DIN interface may require additional time delay
between subsequent devices. When two AD5174 devices are
daisy-chained, 32 bits of data are required. The first 16 bits go to
U2, and the second 16 bits go to U1.

Table 11. Minimize Power Dissipation at SDO Pin

DIN SDO1 Action

0xXXXX 0xXXXX Last user command sent to the digipot
0x8001 0xXXXX

0x0000

1

X is don’t care.

Keep the

SYNC

respective serial registers. The
complete the operation.

µC

Register Contents

Prepares the SDO pin to be placed in
high impedance mode

High
Impedance

The SDO pin is placed in high
impedance

pin low until all 32 bits are clocked into their

SYNC

pin is then pulled high to

DD

AD5174

U1

DINMOSI

SDO

SSSCLK

SYNC

SCLK

Figure 26. Daisy-Chain Configuration Using SDO

R

P

2.2kΩ

AD5174

U2

DIN SDO

SYNC

SCLK

08718-006

Rev. B | Page 15 of 20

AD5174

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5174 employs a three-stage
segmentation approach as shown in Figure 27. The AD5174
wiper switch is designed with the transmission gate CMOS
topology.

A

R

L

R

L

10-BIT

ADDRESS

DECODER

Figure 27. Simplified RDAC Circuit

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance between Terminal W and Terminal A,

, is 10 kΩ and has 1024-tap points accessed by the wiper ter-

R

WA

minal. The 10-bit data in the RDAC latch is decoded to select
one of the 1024 possible wiper settings. As a result, the general
equation for determining the digitally programmed output
resistance between the W terminal and the A terminal is

D

DR ×=

)(

1024

where:

D is the decimal equivalent of the binary code loaded in the

10-bit RDAC register.

R

is the end-to-end resistance.

WA

(1)

R

WAWA

R

M

S

W

R

M

R

W

W

R

W

08718-007

In the zero-scale condition, a finite total wiper resistance of
120 Ω is present. Regardless of which setting the part is oper­ating in, take care to limit the current between Terminal A and
Terminal W to the maximum continuous current of ±6 mA or
a pulse current specified in Tab le 3 . Otherwise, degradation or
possible destruction of the internal switch contact may occur.

Calculate the Actual End-to-End Resistance

The resistance tolerance is stored in the internal memory
during factory testing. The actual end-to-end resistance can,
therefore, be calculated (which is valuable for calibration,
tolerance matching, and precision applications).

The resistance tolerance (in percentage) is stored in fixed-point
format, using a 16-bit sign magnitude binary. The sign bit(0 =
negative and 1 = positive) and the integer part is located in
Address 0x39 as shown in Tab le 1 0. Address 0x3A contains the
fractional part as shown in Ta bl e 12 .

That is, if the data readback from Address 0x39 is 0000001010 and
data from Address 0x3A is 0010110000, then the end-to-end
resistance can be calculated as follows.

For Memory Location 0x39,

DB[9:8]: XX = don’t care



DB[7]: 0 = negative

DB[6:0]: 0001010 = 10

For Memory Location 0x3A,

DB[9:8]: XX = don’t care

−8

DB[7:0]: 10110000 = 176 × 2

Therefore, tolerance = −10.6875% and R

= 0.6875

(1023)= 8.931 kΩ.

WA

Table 12. End-to-End Resistance Tolerance Bytes

Data Byte1

Memory Map Address

0x39 X X Sign 26 2
0x3A X X 2−1 2

1

X is don’t care.

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

5

−2

2

Rev. B | Page 16 of 20

2

−3

2

4

2

−4

2

3

2

−5

2

2

2

−6

2

1

2

−7

2

0

−8

AD5174

V

EXT_CAP CAPACITOR

A 1 μF capacitor to VSS must be connected to the EXT_CAP
pin, as shown in Figure 28, on power-up and throughout the
operation of the AD5174.

AD5174

50-TP

EXT_CAP

C1

1µF

Figure 28. EXT_CAP Hardware Setup

MEMORY

BLOCK

V

SS

V

SS

08718-008

TERMINAL VOLTAGE OPERATING RANGE

The positive VDD and negative VSS power supplies of the AD5174
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal A and
Terminal W that exceed V
forward-biased diodes (see Figure 29).

or VSS are clamped by the internal

DD

DD

The ground pin of the AD5174 is primarily used as a digital
ground reference. To minimize the digital ground bounce, join the
AD5174 ground terminal remotely to the common ground. The
digital input control signals to the AD5174 must be referenced
to the device ground pin (GND) and must satisfy the logic level
defined in the Specifications section. An internal level shift
circuit ensures that the common-mode voltage range of the
three terminals extends from V

to VDD, regardless of the

SS

digital input level.

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at
Ter m in a l A a nd Te rm i na l W ( s ee Figure 29), it is important to
power V
and Terminal W; otherwise, the diode is forward-biased such
that V

DD/VSS

up sequence is V
The order of powering V
important as long as they are powered after V

As soon as V
which first sets the RDAC to midscale and then restores the
last programmed 50-TP value to the RDAC register.

first before applying any voltage to Terminal A

DD/VSS

are powered unintentionally. The ideal power-

, GND, VDD, digital inputs, VA, and VW.

SS

, VW, and the digital inputs is not

A

DD/VSS

is powered, the power-on preset activates,

DD

.

Figure 29. Maximum Terminal Voltages Set by V

A

W

V

SS

08718-009

and V

DD

SS

Rev. B | Page 17 of 20

AD5174

OUTLINE DIMENSIONS

3.10

3.00 SQ

2.90

2.48

2.38

2.23

0.50 BSC

PIN 1 INDEX

AREA

0.80

0.75

0.70

SEATING

PLANE

TOP VIEW

0.30

0.25

0.20

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

6

EXPOSED

PAD

5

BOTTOM VIEW

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

10

1.74

1.64

1.49

1

P

N

I

1

A

O

R

T

N

I

D

C

I

)

5

1

.

R

0

(

121009-A

Figure 30. 10-Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3mm Body, Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.50 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

5.15

4.90

4.65

5

15° MAX

6°
0°

0.23

0.13

0.70

0.55

0.40

091709-A

0.30

0.15

1.10 MAX

Figure 31. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 R

AD5174BRMZ-10 10 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DDT
AD5174BRMZ-10-RL7 10 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DDT
AD5174BCPZ-10-RL7 10 1,024 −40°C to +125°C 10-Lead LFCSP_WD CP-10-9 DEF

1

Z = RoHS Compliant Part.

(kΩ) Resolution Temperature Range Package Description Package Option Branding

AB

Rev. B | Page 18 of 20

AD5174

NOTES

Rev. B | Page 19 of 20

AD5174

NOTES

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08718-0-12/10(B)

Rev. B | Page 20 of 20