Datasheet AD5173 Datasheet (ANALOG DEVICES)

256-Position, One-Time Programmable,

A

Dual-Channel, I2C Digital Potentiometers

FEATURES

2-channel, 256-position potentiometers
One-time programmable (OTP) set-and-forget resistance

setting provides a low cost alternative to EEMEM
Unlimited adjustments prior to OTP activation
OTP overwrite allows dynamic adjustments with user-

defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm
Fast settling time: t
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1 (AD5173)
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: I
Wide operating temperature: −40°C to +125°C

APPLICATIONS

Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

= 5 μs typical on power-up

S

= 6 μA maximum

DD

AD5172/AD5173

FUNCTIONAL BLOCK DIAGRAMS

W1

RDAC

SERIAL INPUT

W1

RDAC

SERIAL INPUT

B1 A2 W2

FUSE

LINKS

RDAC

REGISTER 2

/

8

REGISTER

B1 W2

FUSE

LINKS

RDAC

REGISTER 2

/

8

REGISTER

1

V

GND

SDA

SCL

V

GND

AD0

AD1

SDA

SCL

DD

DD

12

REGISTER 1

Figure 1. AD5172 Functional Block Diagram

12

REGISTER 1

ADDRESS

DECODE

Figure 2. AD5173 Functional Block Diagram

B2

4103-001

B2

04103-002

GENERAL DESCRIPTION

The AD5172/AD5173 are dual-channel, 256-position, one-time
programmable (OTP) digital potentiometers

1

that employ fuse
link technology to achieve memory retention of resistance
settings. OTP is a cost-effective alternative to EEMEM for users
who do not need to program the digital potentiometer setting
in memory more than once. These devices perform the same
electronic adjustment function as mechanical potentiometers or
variable resistors but with enhanced resolution, solid-state reliabil­ity, and superior low temperature coefficient performance.

The AD5172/AD5173 are programmed using a 2-wire, I

2

C®-

compatible digital interface. Unlimited adjustments are allowed

1

The terms digital potentiometer, VR, and RDAC are used interchangeably.

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

before permanently setting the resistance value. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).

Unlike traditional OTP digital potentiometers, the AD5172/
AD5173 have a unique temporary OTP overwrite feature that
allows for new adjustments even after a fuse is blown. However,
the OTP setting is restored during subsequent power-up condi­tions. This allows users to treat these digital potentiometers as
volatile potentiometers with a programmable preset.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2003–2009 Analog Devices, Inc. All rights reserved.

AD5172/AD5173

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagrams ............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics: 2.5 kΩ ............................................... 3

Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ ............. 4

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Test Circuits ..................................................................................... 14

Theory of Operation ...................................................................... 15

One-Time Programming (OTP) .............................................. 15

REVISION HISTORY

4/09—Rev. G to Rev. H

Changes to DC Characteristics—Rheostat Mode Parameter and
to DC Characteristics—Potentiometer Divider Mode Parameter,

Table 1 ................................................................................................ 3

12/08—Rev. F to Rev. G

Changes to OTP Supply Voltage Parameter, Table 1.................... 3

Changes to OTP Supply Voltage Parameter, Table 2.................... 5

Changes to Table 5 and Table 6 ....................................................... 8

Changes to One-Time Programming (OTP) Section ................ 15

Changes to Power Supply Considerations Section, Figure 46,

and Figure 46 Caption .................................................................... 17

Changes to Ordering Guide .......................................................... 23

7/08—Rev. E to Rev. F

Changes to Power Supplies Parameter in Table 1 and Table 2 ... 3

Updated Fuse Blow Condition to 400 ms Throughout ............... 5

1/08—Rev. D to Rev. E

Changes to Features .......................................................................... 1

Changes to General Description .................................................... 1

Changes to OTP Supply Voltage and OTP Supply Current in

Table 1 ................................................................................................ 3

Changes to OTP Supply Voltage and OTP Supply Current in

Table 2 ................................................................................................ 5

Added OTP Program Time in Table 3 ........................................... 6

Changes to Table 4 ............................................................................ 7

Changes to Table 5 and Table 6 ....................................................... 8

Inserted Figure 30 ........................................................................... 13

Replaced One-Time Programming (OTP) Section ................... 15

Replaced Power Supply Considerations Section ........................ 17

Deleted Device Programming Software Section ........................ 20

Programming the Variable Resistor and Voltage ................... 15

Programming the Potentiometer Divider ............................... 16

ESD Protection ........................................................................... 17

Terminal Voltage Operating Range ......................................... 17

Power-Up Sequence ................................................................... 17

Power Supply Considerations ................................................... 17

Layout Considerations ............................................................... 18

I2C Interface .................................................................................... 19

Write Mode ................................................................................. 19

Read Mode .................................................................................. 19

I2C Controller Programming .................................................... 20

I2C-Compatible, 2-Wire Serial Bus .......................................... 21

Level Shifting for Different Voltage Operation ...................... 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

Replaced I

2

C-Compatible, 2-Wire Serial Bus Section ............... 21

Changes to Ordering Guide .......................................................... 23

6/06—Rev. C to Rev. D

Changes to Features .......................................................................... 1

Changes to One-Time Programming (OTP) Section................ 15

Changes to Figure 44 and Figure 45............................................. 17

Changes to Power Supply Considerations Section .................... 18

Changes to Figure 46 and Figure 47............................................. 18

Changes to Device Programming Software Section .................. 19

Updated Outline Dimensions ....................................................... 24

6/05—Rev. B to Rev. C

Added Footnote 8, Footnote 9, and Footnote 10 to Table 1 ........ 3

Added Footnote 8 to Table 2 ............................................................ 5

Changes to Table 5 and Table 6 ....................................................... 9

Changes to Power Supply Considerations Section .................... 17

Changes to I

2

C-Compatible 2-Wire Serial Bus Section ............ 23

Added Level Shifting for Different Voltage Operation Section ...... 24

Updated Outline Dimensions ....................................................... 25

Changes to Ordering Guide .......................................................... 25

10/04—Rev. A to Rev. B

Updated Format ................................................................. Universal

Changes to Specifications ................................................................. 3

Changes to One-Time Programming (OTP) Section................ 13

Changes to Power Supply Considerations Section .................... 15

Changes to Figure 44 and Figure 45............................................. 15

Changes to Figure 46 and Figure 47............................................. 16

11/03—Rev. 0 to Rev. A

Changes to Electrical Characteristics—2.5 kΩ .............................. 3

11/03—Revision 0: Initial Version

Rev. H | Page 2 of 24

AD5172/AD5173

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS: 2.5 kΩ

VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER

4

MODE
Differential Nonlinearity
Integral Nonlinearity

5

INL −2 ±0.6 +2 LSB

5

Voltage Divider Temperature Coefficient (ΔVW/VW)/ΔT Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance A, B

Capacitance W

6

7

7

C

Shutdown Supply Current
Common-Mode Leakage ICM V

DIGITAL INPUTS AND OUTPUTS

SDA and SCL

Input Logic High
Input Logic Low

9

9

V

AD0 and AD1

Input Logic High VIH V

Input Logic Low VIL V
Input Current IIL V
Input Capacitance

7

C

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage

9, 10

V

Supply Current IDD V
OTP Supply Current
Power Dissipation

9, 11 , 12

13

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

Bandwidth, −3 dB BW Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW

2

2

R-INL R

3

R-DNL RWB, VA = no connect −2 ±0.1 +2 LSB

∆RAB T

DNL −1.5 ±0.1 +1.5 LSB

Code = 0xFF −14 −5.5 0 LSB

WFSE

Code = 0x00 0 4.5 12 LSB

WZSE

VA, VB, VW GND VDD V
CA, CB

W

8

I

V

A_SD

VIH V

V

IL

5 pF

IL

DD_RANGE

T

DD_OTP

I

14

V

DD_OTP

P

V

DISS

, VA = no connect −14 ±2 +14 LSB

WB

= 25°C −20 +55 %

A

f = 1 MHz, measured to

45 pF

GND, code = 0x80
f = 1 MHz, measured to

60 pF

GND, code = 0x80

= 5.5 V 0.01 1 μA

DD

= VB = VDD/2 1 nA

A

= 5 V 0.7 VDD VDD + 0.5 V

DD

= 5 V −0.5 +0.3 VDD V

DD

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 μA

IN

2.7 5.5 V
= 25°C 5.6 5.7 5.8 V

A

= 5 V or VIL = 0 V 3.5 6 μA

IH

= 5.0 V, TA = 25°C 100 mA

DD_OTP

= 5 V or VIL = 0 V, VDD = 5 V 33 μW

IH

= 5 V ± 10%,

V

DD

±0.02 ±0.08 %/%

code = midscale

= 1 V rms, VB = 0 V,

V

A

0.1 %

f = 1 kHz

Rev. H | Page 3 of 24

AD5172/AD5173

Parameter Symbol Conditions Min Typ1Max Unit

VW Settling Time tS

= 5 V, VB = 0 V, ±1 LSB

V

A

error band

Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3

VA = VDD, VB = 0 V, wiper (VW) = no connect.

4

Specifications apply to all VRs.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

6

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

7

Guaranteed by design, but not subject to production test.

8

Measured at Terminal A. Terminal A is open circuited in shutdown mode.

9

The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.

However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

10

Different from the operating power supply; the power supply for OTP is used one time only.

11

Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.

12

See Figure 30 for an energy plot during an OTP program.

13

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

14

All dynamic characteristics use VDD = 5 V.

R

N_WB

WB

= 1.25 kΩ, RS = 0 Ω 3.2 nV/√Hz

ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.

1 μs

Table 2.

Parameter Symbol Conditions Min Typ

1

Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance

2

2

R-INL R

3

R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB

ΔRAB T

, VA = no connect −2.5 ±0.25 +2.5 LSB

WB

= 25°C −20 +20 %

A

Resistance Temperature Coefficient (ΔRAB/RAB)/ΔT 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER

4

MODE
Differential Nonlinearity
Integral Nonlinearity

5

INL −1 ±0.3 +1 LSB

5

DNL −1 ±0.1 +1 LSB

Voltage Divider Temperature Coefficient (ΔVW/VW)/ΔT Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF −2.5 −1 0 LSB

WFSE

Code = 0x00 0 1 2.5 LSB

WZSE

RESISTOR TERMINALS

Voltage Range
Capacitance A, B

6

7

VA, VB, VW GND VDD V
CA, CB

f = 1 MHz, measured to

45 pF

GND, code = 0x80

Capacitance W

7

C

W

f = 1 MHz, measured to

60 pF

GND, code = 0x80
Shutdown Supply Current
Common-Mode Leakage ICM V

8

I

V

A_SD

DD

= VB = VDD/2 1 nA

A

= 5.5 V 0.01 1 μA

DIGITAL INPUTS AND OUTPUTS

SDA and SCL

Input Logic High
Input Logic Low

9

9

V

VIH V

V

IL

= 5 V 0.7 VDD VDD + 0.5 V

DD

= 5 V −0.5 +0.3 VDD V

DD

AD0 and AD1

Input Logic High VIH V

Input Logic Low VIL V
Input Current IIL V
Input Capacitance

7

C

5 pF

IL

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 μA

IN

Rev. H | Page 4 of 24

AD5172/AD5173

Parameter Symbol Conditions Min Typ

1

Max Unit

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage

9, 10

V

Supply Current IDD V
OTP Supply Current
Power Dissipation

13

9, 11 , 12

I
P

Power Supply Sensitivity PSS

2.7 5.5 V

DD_RANGE

T

DD_OTP

V

DD_OTP

DISS

= 25°C 5.6 5.7 5.8 V

A

= 5 V or VIL = 0 V 3.5 6 μA

IH

= 5.0 V, TA = 25°C 100 mA

DD_OTP

= 5 V or VIL = 0 V,

V

IH

= 5 V

V

DD

= 5 V ± 10%,

V

DD

33 μW

±0.02 ±0.08 %/%

code = midscale

DYNAMIC CHARACTERISTICS

14

Bandwidth, −3 dB BW RAB = 10 kΩ, code = 0x80 600 kHz
R
R
Total Harmonic Distortion THDW

VW Settling Time tS

= 50 kΩ, code = 0x80 100 kHz

AB

= 100 kΩ, code = 0x80 40 kHz

AB

= 1 V rms, VB = 0 V,

V

A

f = 1 kHz, R

= 5 V, VB = 0 V, ±1 LSB

V

A

= 10 kΩ

AB

0.1 %

2 μs

error band

Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3

VA = VDD, VB = 0 V, wiper (VW) = no connect.

4

Specifications apply to all VRs.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

6

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

7

Guaranteed by design, but not subject to production test.

8

Measured at Terminal A. Terminal A is open circuited in shutdown mode.

9

The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.

However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

10

Different from the operating power supply; the power supply for OTP is used one time only.

11

Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.

12

See Figure 30 for an energy plot during an OTP program.

13

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

14

All dynamic characteristics use VDD = 5 V.

R

N_WB

WB

= 5 kΩ, RS = 0 Ω 9 nV/√Hz

Rev. H | Page 5 of 24

AD5172/AD5173

TIMING CHARACTERISTICS

VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
Bus-Free Time Between Stop and Start, t
Hold Time (Repeated Start), t

Low Period of SCL Clock, t
High Period of SCL Clock, t

HD;STA

t

LOW

t

HIGH

Setup Time for Repeated Start Condition, t
Data Hold Time, t
Data Setup Time, t

2

HD;DAT

t

SU;DAT

Fall Time of Both SDA and SCL Signals, tF t
Rise Time of Both SDA and SCL Signals, tR t
Setup Time for Stop Condition, t
OTP Program Time t11 400 ms

1

See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 48 to Figure 51).

2

The maximum t

has to be met only if the device does not stretch the low period (t

HD;DAT

Timing Diagram

1

t

BUF

t

400 kHz

SCL

1.3 μs

1

2

After this period, the first clock
pulse is generated.

1.3 μs

3

0.6 μs

4

t

SU;STA

0.6 μs

5

t6 0.9 μs

100 ns

7

300 ns

8

300 ns

9

t

SU;STO

t

8

0.6 μs

10

) of the SCL signal.

LOW

t

t

6

9

0.6 μs

t

2

SCL

SDA

t

2

t

1

PS

t

3

t

9

t

8

Figure 3. I

t

4

2

C Interface Detailed Timing Diagram

t

7

t

5

S

t

10

04103-0-039

P

Rev. H | Page 6 of 24

AD5172/AD5173

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V

VA, VB, VW to GND VDD

Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1

Pulsed ±20 mA

Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (T

) 150°C

JMAX

Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Thermal Resistance

2

θJA for 10-Lead MSOP 200°C/W

1

The maximum terminal current is bound by the maximum current handling

of the switches, the maximum power dissipation of the package, and the
maximum applied voltage across any two of the A, B, and W terminals at a
given resistance.

2

The package power dissipation is (T

− TA)/θJA.

JMAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. H | Page 7 of 24

AD5172/AD5173

G

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

B1

2

A1

AD5172

3

W2

TOP VIEW

(Not to Scale)

ND

4

V

5

DD

Figure 4. AD5172 Pin Configuration

10

W1

9

B2

8

A2

SDA

7

SCL

6

4103-045

B1

AD0

W2

GND

V

DD

1

2

AD5173

3

TOP VIEW

(Not to Scale)

4

5

W1

10

B2

9

AD1

8

SDA

7

SCL

6

04103-046

Figure 5. AD5173 Pin Configuration

Table 5. AD5172 Pin Function Descriptions

Pin
No. Mnemonic Description

1 B1 B1 Terminal. GND ≤ VB1 ≤ VDD.
2 A1 A1 Terminal. GND ≤ VA1 ≤ VDD.
3 W2 W2 Terminal. GND ≤ VW2 ≤ VDD.
4 GND Digital Ground.
5 VDD

Positive Power Supply. Specified for
operation from 2.7 V to 5.5 V. For OTP
programming, V

needs to be a minimum

DD

of 5.6 V but no more than 5.8 V and to be
capable of driving 100 mA.

6 SCL

Serial Clock Input. Positive-edge triggered.
Requires a pull-up resistor. If this pin is driven
directly from a logic controller without a
pull-up resistor, ensure that the VIH minimum

.

DD

7 SDA

is 0.7 V × V
Serial Data Input/Output. Requires a pull-up

resistor. If this pin is driven directly from a
logic controller without a pull-up resistor,
ensure that the V

minimum is 0.7 V × VDD.

IH

8 A2 A2 Terminal. GND ≤ VA2 ≤ VDD.
9 B2 B2 Terminal. GND ≤ VB2 ≤ VDD.
10 W1 W1 Terminal. GND ≤ VW1 ≤ VDD.

Table 6. AD5173 Pin Function Descriptions

Pin
No. Mnemonic Description

1 B1 B1 Terminal. GND ≤ VB1 ≤ VDD.
2 AD0

Programmable Address Bit 0 for Multiple

Package Decoding.
3 W2 W2 Terminal. GND ≤ VW2 ≤ VDD.
4 GND Digital Ground.
5 VDD

Positive Power Supply. Specified for

operation from 2.7 V to 5.5 V. For OTP

programming, V

needs to be a minimum

DD

of 5.6 V but no more than 5.8 V and to be

capable of driving 100 mA.
6 SCL

Serial Clock Input. Positive-edge triggered.

Requires a pull-up resistor. If this pin is driven

directly from a logic controller without a

pull-up resistor, ensure that the V

7 SDA

is 0.7 V × V

Serial Data Input/Output. Requires a pull-up

.

DD

resistor. If this pin is driven directly from a

logic controller without a pull-up resistor,

ensure that the VIH minimum is 0.7 V × VDD.
8 AD1

Programmable Address Bit 1 for Multiple

Package Decoding.
9 B2 B2 Terminal. GND ≤ VB2 ≤ VDD.
10 W1 W1 Terminal. GND ≤ VW1 ≤ VDD.

minimum

IH

Rev. H | Page 8 of 24

AD5172/AD5173

A

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.5

1.0

0.5

0

T MODE INL (LSB)

–0.5

–1.0

RHEOST

–1.5

–2.0

VDD = 2.7V

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

TA = 25°C
R

= 10kΩ

AB

04103-003

Figure 6. R-INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL (LSB)

–0.4

–0.5

VDD = 2.7V; TA = –40°C, +25° C, +85°C, +125°C

1289632 640 160 192 224 256

CODE (DECIMAL)

RAB = 10kΩ

04103-006

Figure 9. DNL vs. Code vs. Temperature

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

RHEOSTAT MODE DNL (LSB)

–0.3

–0.4

–0.5

VDD = 2.7V

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

TA = 25°C
R

= 10kΩ

AB

04103-004

Figure 7. R-DNL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTI OMETER MO DE INL (L SB)

–0.4

–0.5

VDD = 5.5V
T

= –40°C, +25° C, +85°C, +125°C

A

VDD = 2.7V
T

= –40°C, +25° C, +85°C, +125°C

A

1289632 640 160 192 224 256

CODE (DECIMAL)

RAB = 10kΩ

04103-005

Figure 8. INL vs. Code vs. Temperature

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTI OMETER MO DE INL (LSB)

–0.8

–1.0

VDD = 2.7V

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 5.5V

TA = 25°C
R

= 10kΩ

AB

04103-007

Figure 10. INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL (LSB)

–0.4

–0.5

VDD = 2.7V

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

TA = 25°C
R

= 10kΩ

AB

04103-008

Figure 11. DNL vs. Code vs. Supply Voltages

Rev. H | Page 9 of 24

AD5172/AD5173

A

A

T

A

2.0

1.5

1.0

0.5

VDD = 2.7V
T

= –40°C, +25° C, +85°C, +125°C

A

RAB = 10kΩ

4.50

RAB = 10kΩ

3.75

3.00

0

T MODE INL (LSB)

–0.5

–1.0

RHEOST

–1.5

–2.0

VDD = 5.5V
T

= –40°C, +25° C, +85°C, +125°C

A

1289632 640 160 192 224 256

CODE (DECIMAL)

04103-009

Figure 12. R-INL vs. Code vs. Temperature

0.5

0.4

0.3

0.2

0.1

T MODE DNL (LSB)

–0.1

–0.2

RHEOST

–0.3

–0.4

–0.5

VDD = 2.7V, 5.5V; TA = –40°C, +25° C, +85°C, +125°C

0

1289632 640 160 192 224 256

CODE (DECIMAL)

RAB = 10kΩ

04103-010

Figure 13. R-DNL vs. Code vs. Temperature

2.25

1.50

ZSE, ZERO -SCALE ERROR ( LSB)

0.75

VDD = 2.7V, VA = 2.7V

VDD = 5.5V, VA = 5.0V

0

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 15. Zero-Scale Error vs. Temperature

10

)

(µ

1

, SUPPLY CURREN

DD

I

0.1
–40 –7 26 59 92 125

VDD = 5V

VDD = 3V

TEMPERATURE (° C)

Figure 16. Supply Current vs. Temperature

04103-012

04103-013

2.0

1.5

1.0

0.5

0

–0.5

–1.0

FSE, FULL-SCALE ERRO R (LSB)

–1.5

–2.0

–40 –25 –10 5 20 35 50 65 80 95 110 125

VDD = 2.7V, VA = 2.7V

VDD = 5.5V, VA = 5.0V

TEMPERATURE (°C)

RAB = 10kΩ

04103-011

Figure 14. Full-Scale Error vs. Temperature

120

100

80

60

40

20

RHEOSTAT MO DE TEMPCO (ppm/° C)

0

–20

VDD = 2.7V
T

= –40°C TO +85°C, –40°C T O +125°C

A

VDD = 5.5V
T

= –40°C TO + 85°C, –40°C TO +125°C

A

1289632 640 160 192 224 256

CODE (DECIMAL)

Figure 17. Rheostat Mode Tempco ΔRWB/ΔT vs. Code

RAB = 10kΩ

04103-014

Rev. H | Page 10 of 24

AD5172/AD5173

50

40

30

VDD = 2.7V
T

20

10

0

–10

–20

POTENTI OMETER MO DE TEMPCO (ppm/° C)

–30

= –40°C TO + 85°C, –40°C TO +125°C

A

VDD = 5.5V
T

= –40°C TO +85°C, –40° C TO +125° C

A

1289632 640 160 192 224 256

CODE (DECIMAL)

RAB = 10kΩ

Figure 18. AD5172 Potentiometer Mode Tempco ΔVWB/ΔT vs. Code

04103-047

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 100k10k 1M

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

FREQUENCY ( Hz)

Figure 21. Gain vs. Frequency vs. Code, RAB = 50 kΩ

04103-050

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

10k 1M100k 10M

0x80

0x40

0x20

0x10

0x08
0x04

0x010x02

FREQUENCY ( Hz)

Figure 19. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 100k10k 1M

0x80

0x40

0x20

0x10

0x08

0x04

0x02
0x01

FREQUENCY ( Hz)

Figure 20. Gain vs. Frequency vs. Code, RAB = 10 kΩ

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

04103-048

–60

1k 100k10k 1M

Figure 22. Gain vs. Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

04103-049

–60

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

FREQUENCY ( Hz)

= 100 kΩ

AB

100kΩ
60kHz

50kΩ
120kHz

10kΩ
570kHz

2.5kΩ

2.2MHz

10k1k 100k 1M 10M

FREQUENCY ( Hz)

04103-051

04103-052

Figure 23. −3 dB Bandwidth at Code = 0x80

Rev. H | Page 11 of 24

AD5172/AD5173

10

TA = 25°C

1

0.1

, SUPPLY CURRENT (mA)

DD

I

0.01
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VDD = 2.7V

DIGITAL INPUT VOLTAGE (V)

VDD = 5.5V

Figure 24. Supply Current vs. Digital Input Voltage

V

W

V

W2

V

W1

04103-057

04103-056

Figure 27. Analog Crosstalk

V

W

SCL

V

V

04103-053

Figure 25. Digital Feedthrough

W2

W1

04103-054

Figure 26. Digital Crosstalk

Figure 28. Midscale Glitch, Code 0x80 to Code 0x7F

V

W

SCL

Figure 29. Large-Signal Settling Time

04103-058

04103-055

Rev. H | Page 12 of 24

AD5172/AD5173

T

1

CH1 20.0mA M 200ns A CH1 32.4mA

T 588.000ns

CHANNEL 1
MAXIMUM:
103mA

CHANNEL 1
MINIMUM:
–1.98mA

04103-062

Figure 30. OTP Program Energy for Single Fuse

Rev. H | Page 13 of 24

AD5172/AD5173

V

A

V

V

TEST CIRCUITS

Figure 31 to Figure 38 illustrate the test circuits that define the test conditions used in the product specification tables (see Tabl e 1 and Tab l e 2 ).

DUT

A

V+

W

B

V+ = V

DD

1LSB = V+/ 2

V

MS

N

04103-015

Figure 31. Potentiometer Divider Nonlinearity Error (INL, DNL)

NC

DUT

A

W

B

NC = NO CONNECT

I

W

V

MS

4103-016

Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL)

DUT

A

V

MS2

W

B

V

W

IW= VDD/R

V

MS1

RW= [V

NOMINAL

– V

MS1

MS2

]/I

W

04103-017

Figure 33. Wiper Resistance

DUT

W

B

OFFSET

GND

V

IN

2.5V

Figure 35. Test Circuit for Gain vs. Frequency

0.1

RSW=

I

DUT

B

W

I

SW

GND TO V

SW

CODE = 0x00

DD

Figure 36. Incremental On Resistance

NC

DUT

V

DD

GND

NC

NC = NO CONNECT

I

A

W

B

V

Figure 37. Common-Mode Leakage Current

+5V

AD8610

–5V

CM

CM

0.1V

V

OUT

04103-019

04103-020

4103-021

A

DUT

V

DD

A

V+

W

B

V+ = VDD± 10%

PSRR (dB) = 20 log

PSS (%/ %) =

V

MS

Figure 34. Power Supply Sensitivity (PSS, PSSR)

ΔV

MS

()

ΔV

VMS%

DD

Δ

ΔVDD%

A1

RDAC1

W1

NC

IN

04103-018

B1

CTA = 20 log [V

NC = NO CONNECT

Figure 38. Analog Crosstalk

V

V

DD

SS

RDAC2

OUT/VIN

W2

A2

V

OUT

B2

]

04103-022

Rev. H | Page 14 of 24

AD5172/AD5173

W

THEORY OF OPERATION

SCL

SDA

2

I

C INTERFACE

COMPARATOR

ONE-TIME

PROGRAM/T EST

CONTROL BL OCK

Figure 39. Detailed Functional Block Diagram

The AD5172/AD5173 are 256-position, digitally controlled
variable resistors (VRs) that employ fuse link technology to
achieve memory retention of the resistance setting.

An internal power-on preset places the wiper at midscale
during power-on. If the OTP function is activated, the device
powers up at the user-defined permanent setting.

ONE-TIME PROGRAMMING (OTP)

Prior to OTP activation, the AD5172/AD5173 presets to midscale
during initial power-on. After the wiper is set to the desired
position, the resistance can be permanently set by programming
the T bit high, with the proper coding (see Tab le 8 and Tab le 9 ),
and one-time V
family of digital potentiometers requires V

5.6 V and 5.8 V to blow the fuses to achieve a given nonvolatile
setting. However, during operation, V
result, an external supply is required for one-time programming.
The user is allowed only one attempt to blow the fuses. If the user
fails to blow the fuses during this attempt, the structure of the
fuses can change such that they may never be blown, regardless
of the energy applied during subsequent events. For details, see
the Power Supply Considerations section.

The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Tabl e 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses are
blown, all fuse latches are enabled upon subsequent power-on;
therefore, the output corresponds to the stored setting. Figure 39
shows a detailed functional block diagram.

. The fuse link technology of the AD517x

DD_OTP

to be between

DD_OTP

can be 2.7 V to 5.5 V. As a

DD

A

B

04103-026

DAC
REG

FUSES

EN

MUX

FUSE

REG

DECODER

Table 7. Validation Status

E1 E0 Status

0 0 Ready for programming.
1 0

Fatal error. Some fuses are not blown. Do not retry.
Discard this unit.

1 1 Successful. No further programming is possible.

PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE

Rheostat Operation

The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance (R
accessed by the wiper terminal and the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the
256 possible settings.

A

W

B

Figure 40. Rheostat Mode Configuration

Assuming a 10 kΩ part is used, the first connection of the wiper
starts at the B terminal for Data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminal W and Ter­minal B. The second connection is the first tap point, which
corresponds to 139 Ω (R
50 Ω) for Data 0x01. The third connection is the next tap point,
representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so
on. Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at 10,100 Ω (R

) of the VR has 256 contact points

AB

A

W

B

= RAB/256 + 2 × RW = 39 Ω + 2 ×

WB

A

B

W

+ 2 × RW).

AB

04103-027

Rev. H | Page 15 of 24

AD5172/AD5173

−

A

R

S

D7
D6
D5
D4
D3
D2
D1
D0

RDAC

LATCH

AND

DECODER

Figure 41. AD5172/AD5173 Equivalent RDAC Circuit

R

S

R

S

W

R

S

B

4103-028

The general equation that determines the digitally programmed
output resistance between W and B is

WB

128

D

DR ×+×= 2

)(

AB

(1)

RR

W

where:

D is the decimal equivalent of the binary code loaded in the

8-bit RDAC register.

R

is the end-to-end resistance.

AB

R

is the wiper resistance contributed by the on resistance of

W

the internal switch.

In summary, if R
the output resistance, R

is 10 kΩ and the A terminal is open circuited,

AB

, is set according to the RDAC latch

WB

codes, as listed in Tab l e 8.

Table 8. Codes and Corresponding RWB Resistance

D (Dec) RWB (Ω) Output State

255 9961 Full scale (RAB – 1 LSB + RW)
128 5060 Midscale
1 139 1 LSB
0 100 Zero scale (wiper contact resistance)

Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible destruc­tion of the internal switch contact may occur.

Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a digi­tally controlled complementary resistance, R

. When these

WA

terminals are used, the B terminal can be opened. Setting the
resistance value for R

starts at a maximum value of resistance

WA

and decreases as the data loaded in the latch increases in value.
The general equation for this operation is

–256

128

D

ABWA

DR ×+×= 2

)(

(2)

RR

W

When R
output resistance, R

is 10 kΩ and the B terminal is open circuited, the

AB

, is set according to the RDAC latch

WA

codes, as listed in Tab l e 9.

Table 9. Codes and Corresponding RWA Resistance

D (Dec) RWA (Ω) Output State

255 139 Full scale
128 5060 Midscale
1 9961 1 LSB
0 10,060 Zero scale

Typical device-to-device matching is process-lot dependent
and can vary up to ±30%. Because the resistance element is
processed using thin-film technology, the change in R

AB

with

temperature has a very low temperature coefficient of 35 ppm/°C.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at
wiper to B and at wiper to A, proportional to the input voltage
at A to B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.

V

I

Figure 42. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the vol­tage applied across Terminal A and Terminal B divided by the
256 positions of the potentiometer divider. The general equation
defining the output voltage at V
valid input voltage applied to Terminal A and Terminal B is

D

)(

DV

W

256

256

V

+=

A

256

A more accurate calculation, which includes the effect of wiper
resistance, V

, is

W

)(

DR

WB

)( += (4)

DV

W

V

A

R

AB

Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, R
values. Therefore, the temperature drift reduces to 15 ppm/°C.

to GND, which must be

DD

A

W

V

O

B

04103-029

with respect to ground for any

W

D

(3)

V

B

)(

DR

WA

V

R

B

AB

and RWB, not on the absolute

WA

Rev. H | Page 16 of 24

AD5172/AD5173

V

A

ESD PROTECTION

All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as
shown in Figure 43 and Figure 44.

340Ω

LOGIC

GND

Figure 43. ESD Protection of Digital Pins

A, B, W

04103-030

rack-mount power supply) must be rated at 5.6 V to 5.8 V and
must be able to provide a 100 mA transient current for 400 ms
for successful one-time programming. When programming
is completed, the V

supply must be removed to allow

DD_OTP

normal operation at 2.7 V to 5.5 V; the device consumes only
microamps of current.

5.7V

R1

10kΩ

2.7V

PPLY FOR OTP ONLY

P1

P2

C1

10µFC20.1µF

V

DD

AD5172/
AD5173

GND

Figure 44. ESD Protection of Resistor Terminals

04103-031

TERMINAL VOLTAGE OPERATING RANGE

The AD5172/AD5173 VDD to GND power supply defines the
boundary conditions for proper 3-terminal digital potenti­ometer operation. Supply signals present on Terminal A,
Ter min al B , an d Ter mi nal W t h at e xc e ed V

or GND are

DD

clamped by the internal forward-biased diodes (see Figure 45).

DD

A

W

B

GND

04103-032

Figure 45. Maximum Terminal Voltages Set by V

and GND

DD

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance
at Te rm i na l A, Te rm ina l B, a nd Te rm ina l W ( se e Figure 45), it
is important to power V

/GND before applying voltage to

DD

Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that V

is powered unintentionally and

DD

may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, V
relative order of powering V
not important, as long as they are powered after V

, digital inputs, and then VA/VB/VW. The

DD

, VB, VW, and the digital inputs is

A

/GND.

DD

POWER SUPPLY CONSIDERATIONS

To minimize the package pin count, both the one-time pro­gramming and normal operating voltage supplies are applied to
the same V
employ fuse link technology that requires 5.6 V to 5.8 V to blow
the internal fuses to achieve a given setting, but normal V
be 2.7 V to 5.5 V. Such dual-voltage requirements need isolation
between the supplies if V
The fuse programming supply (either an on-board regulator or

terminal of the device. The AD5172/AD5173

DD

is lower than the required V

DD

DD

DD_OTP

can

.

P1 = P2 = FDV 302P, NDS0610

4103-035

Figure 46. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply

For example, for those who operate their systems at 2.7 V, use of
the bidirectional, low threshold, P-channel MOSFETs is recom­mended for the isolation of the supply. As shown in Figure 46,
this assumes that the 2.7 V system voltage is applied first and
that the P1 and P2 gates are pulled to ground, thus turning on
P1 and then P2. As a result, V

of the AD5172/AD5173

DD

approaches 2.7 V. When the AD5172/AD5173 setting is found,
the factory tester applies the V

to both the VDD and the

DD_OTP

MOSFET gates, thus turning P1 and P2 off. To program the
AD5172/AD5173 while the 2.7 V source is protected, execute
the OTP command at this time. When the OTP is completed,
the tester withdraws the V

, and the setting of the AD5172

DD_OTP

or AD5173 is fixed permanently.

The AD5172/AD5173 achieve the OTP function by blowing
internal fuses. Always apply the 5.6 V to 5.8 V one-time pro­gram voltage requirement at the first fuse programming attempt.
Failure to comply with this requirement may lead to changing
the fuse structures, rendering programming inoperable.

Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × V

and VDD + 0.5 V.

DD

Poor PCB layout introduces parasitics that can affect fuse
programming. Therefore, it is recommended to add a 1 μF to
10 μF tantalum capacitor in parallel with a 1 nF ceramic capacitor
as close as possible to the VDD pin. The type and value chosen for
both capacitors are important. These capacitors work together to
provide both fast responsiveness and large supply current handling
with minimum supply droop during transients. As a result,
these capacitors increase the OTP programming success by not
inhibiting the proper energy needed to blow the internal fuses.
Additionally, C1 minimizes transient disturbance and low
frequency ripple, whereas C2 reduces high frequency noise
during normal operation.

Rev. H | Page 17 of 24

AD5172/AD5173

LAYOUT CONSIDERATIONS

In PCB layout, it is a good practice to employ compact, minimum
lead length design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths should
have low resistance and low inductance.

Note that the digital ground should also be joined remotely to
the analog ground at one point to minimize the ground bounce.

V

DD

+

C1

10µFC20.1µF

Figure 47. Power Supply Bypassing

V

DD

AD5172

GND

04103-036

Rev. H | Page 18 of 24

AD5172/AD5173

I2C INTERFACE

WRITE MODE

Table 10. AD5172 Write Mode

S 0 1 0 1 1 1 1

Slave address byte Instruction byte Data byte

Table 11. AD5173 Write Mode

S 0 1 0 1 1 AD1 AD0

Slave address byte Instruction byte Data byte

READ MODE

Table 12. AD5172 Read Mode

S 0 1 0 1 1 1 1 R A D7 D6 D5 D4 D3 D2 D1 D0 A E1 E0 X X X X X X A P

Slave address byte Instruction byte Data byte

Table 13. AD5173 Read Mode

S 0 1 0 1 1 AD1 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A E1 E0 X X X X X X A P

Slave address byte Instruction byte Data byte

W

A A0 SD T 0 OW X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P

W

A A0 SD T 0 OW X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P

Table 14. SDA Bits Descriptions

Bit Description

S Start condition.
P Stop condition.
A Acknowledge.
AD0, AD1 Package pin-programmable address bits.
X Don’t care.
W

Write.
R Read.
A0 RDAC subaddress select bit.
SD

Shutdown connects wiper to B terminal and open circuits the A terminal. It does not change the

contents of the wiper register.
T OTP programming bit. Logic 1 programs the wiper permanently.
OW

Overwrites the fuse setting and programs the digital potentiometer to a different setting. Upon

power-up, the digital potentiometer is preset to either midscale or fuse setting, depending on

whether the fuse link was blown.
D7, D6, D5, D4, D3, D2, D1, D0 Data bits.
E1, E0 OTP validation bits.
00 = ready to program.
10 = fatal error. Some fuses not blown. Do not retry. Discard this unit.
11 = programmed successfully. No further adjustments are possible.

Rev. H | Page 19 of 24

AD5172/AD5173

S

S

S

S

I2C CONTROLLER PROGRAMMING

Write Bit Patterns

SCL

SDA

TART BY

MASTER

SCL

SDA

TART BY

MASTER

Read Bit Patterns

SCL

SDA

TART BY

MASTER

SCL

SDA

TART BY

MASTER

1

01

01111

FRAME 1

SLAVE ADDRESS BYTE

1

01

0 1 1 AD1 AD0

FRAME 1

SLAVE ADDRESS BYTE

1

01

01111

FRAME 1

SLAVE ADDRESS BYTE

Figure 50. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5172

1

01

0 1 1 AD1 AD0

FRAME 1

SLAVE ADDRESS BYTE

Figure 51. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5173

19

R/W A0 SD 0 OW X X X

ACK BY
AD5172

T

FRAME 2

INSTRUCTIO N BYTE

19

D7 D6 D5 D4 D3

ACK BY
AD5172

FRAME 3

DATA BYTE

Figure 48. Writing to the RDAC Register—AD5172

19

R/W A0 SD 0 OW X X X

ACK BY
AD5173

T

FRAME 2

INSTRUCTIO N BYTE

19

D7 D6 D5 D4 D3

ACK BY
AD5173

FRAME 3

DATA BYTE

Figure 49. Writing to the RDAC Register—AD5173

19

R/W D7D6 D4D3D2D1D019E1 E0 X X X

ACK BY
AD5172

R/W D7D6 D4D3D2D1D019E1 E0 X X X

ACK BY
AD5173

D5

FRAME 2

INSTRUCTIO N BYTE

D5

FRAME 2

INSTRUCTIO N BYTE

ACK BY
MASTER

ACK BY
MASTER

FRAME 3

DATA BYTE

19

FRAME 3

DATA BYTE

D2 D1 D0

D2 D1 D0

XXX

XXX

9

ACK BY
AD5172

STOP BY

MASTER

9

ACK BY
AD5173

STOP BY

MASTER

9

NO ACK
BY MASTER

STOP BY

MASTER

9

NO ACK
BY MASTER

STOP BY

MASTER

04103-040

04103-041

04103-042

04103-043

Rev. H | Page 20 of 24

AD5172/AD5173

I2C-COMPATIBLE, 2-WIRE SERIAL BUS

This section describes how the 2-wire, I2C-compatible serial bus
protocol operates.

The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 48 and Figure 49).
The following byte is the slave address byte, which consists of

W

the slave address followed by an R/
whether data is read from or written to the slave device). The
AD5172 has a fixed slave address byte, whereas the AD5173
has two configurable address bits, AD0 and AD1 (see
and ).

Figure 49

The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to or read from its serial register. If the

W

bit is high, the master reads from the slave device. If the

R/

W

R/

bit is low, the master writes to the slave device.

In write mode, the second byte is the instruction byte. The first
bit (MSB) of the instruction byte is the RDAC subaddress select
bit. Logic low selects Channel 1; logic high selects Channel 2.

The second MSB, SD, is a shutdown bit. A logic high causes an
open circuit at Terminal A while shorting the wiper to Terminal B.
This operation yields almost 0 Ω in rheostat mode or 0 V in
potentiometer mode. It is important to note that the shutdown
operation does not disturb the contents of the register. When
brought out of shutdown, the previous setting is applied to the
RDAC. In addition, during shutdown, new settings can be
programmed. When the part is returned from shutdown, the
corresponding VR setting is applied to the RDAC.

The third MSB, T, is the OTP programming bit. A logic high
blows the polyfuses and programs the resistor setting permanently.
The OTP program time is 400 ms.

The fourth MSB must always be at Logic 0.

The fifth MSB, OW, is an overwrite bit. When raised to a logic high,
OW allows the RDAC setting to be changed even after the internal
fuses are blown. However, when OW is returned to Logic 0, the
position of the RDAC returns to the setting prior to the overwrite.
Because OW is not static, if the device is powered off and on,
the RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether the fuses had been
permanently set.

The remainder of the bits in the instruction byte are don’t cares
(see Figure 48 and Figure 49).

bit (this bit determines

Figure 48

After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 3).

In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from the write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, transitions on the
SDA line must occur during the low period of SCL and remain
stable during the high period of SCL (see Figure 50 and Figure 51).

Note that the channel of interest is the one that is previously
selected in write mode. If users need to read the RDAC values
of both channels, they must program the first channel in write
mode and then change to read mode to read the first channel
value. After that, the user must return to write mode with the
second channel selected and read the second channel value in
read mode. It is not necessary for users to issue the Frame 3
data byte in write mode for subsequent readback operations.
Refer to Figure 50 and Figure 51 for the programming format.

Following the data byte, the validation byte contains two valida­tion bits, E0 and E1 (see Tab le 7 ). These bits signify the status of
the one-time programming (see Figure 50 and Figure 51).

After all data bits are read or written, the master establishes a
stop condition. A stop condition is defined as a low-to-high
transition on the SDA line while SCL is high. In write mode,

th

the master pulls the SDA line high during the 10

clock pulse to
establish a stop condition (see Figure 48 and Figure 49). In read
mode, the master issues a no acknowledge for the ninth clock
pulse (that is, the SDA line remains high). The master brings

th

the SDA line low before the 10

clock pulse and then brings the
SDA line high to establish a stop condition (see Figure 50 and
Figure 51).

A repeated write function provides the user with the flexibility
of updating the RDAC output multiple times after addressing
and instructing the part only once. For example, after the RDAC
has acknowledged its slave address and instruction bytes in write
mode, the RDAC output is updated on each successive byte. If
different instructions are needed, however, the write/read mode
must restart with a new slave address, instruction, and data byte.
Similarly, a repeated read function of the RDAC is also allowed.

Rev. H | Page 21 of 24

AD5172/AD5173

V

V

Multiple Devices on One Bus (AD5173 Only)

Figure 52 shows four AD5173 devices on the same serial bus.
Each has a different slave address because the states of the AD0
and AD1 pins are different. This allows each device on the bus to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully

2

C-compatible interface.

I

5V

R

PRP

MASTER

5V

SDA

SCL

AD1

AD0

AD5173

SDA

AD1

AD0

AD5173

Figure 52. Multiple AD5173 Devices on One I

SCL

5V

SDA

SCL

AD1

AD0

AD5173

5V

2

C Bus

SDA

SCL

AD1

AD0

AD5173

SDA

SCL

04103-044

LEVEL SHIFTING FOR DIFFERENT VOLTAGE OPERATION

If the SCL and SDA signals come from a low voltage logic
controller and are below the minimum V
level shift the signals for read/write communications between
the AD5172/AD5173 and the controller. Figure 53 shows one
of the implementations. For example, when SDA1 is at 2.5 V,
M1 turns off, and SDA2 becomes 5 V. When SDA1 is at 0 V,
M1 turns on, and SDA2 approaches 0 V. As a result, proper
level shifting is established. It is best practice for M1 and M2
to be low threshold N-channel power MOSFETs, such as the
FDV301N from Fairchild Semiconductor.

= 2.5V

DD1

SDA1

SCL1

CONTROL LER

2.5V

R

R

P

P

G

G

D

S

S

M1

M2

Figure 53. Level Shifting for Different Voltage Operation

level (0.7 V × VDD),

IH

R

P

D

DD2

R

P

2.7V TO 5.5V

AD5172/
AD5173

= 5V

SDA2

SCL2

04103-061

Rev. H | Page 22 of 24

AD5172/AD5173

OUTLINE DIMENSIONS

3.10

3.00

2.90

6

10

3.10

3.00

2.90

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.05

0.33

0.17

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 54. 10-Lead Mini Small Outline Package [MSOP]

ORDERING GUIDE

1

Model

AD5172BRM2.5 2.5 −40°C to +125°C 10-Lead MSOP RM-10 DCY
AD5172BRM2.5-RL7 2.5 −40°C to +125°C 10-Lead MSOP RM-10 DCY
AD5172BRMZ2.5

2

AD5172BRM10 10 −40°C to +125°C 10-Lead MSOP RM-10 DCZ
AD5172BRM10-RL7 10 −40°C to +125°C 10-Lead MSOP RM-10 DCZ
AD5172BRMZ10
AD5172BRMZ10-RL7

2

10 −40°C to +125°C 10-Lead MSOP RM-10 DCT

2

AD5172BRM50 50 −40°C to +125°C 10-Lead MSOP RM-10 DCX
AD5172BRMZ50
AD5172BRMZ50-RL7

2

50 −40°C to +125°C 10-Lead MSOP RM-10 DCU

2

AD5172BRM100 100 −40°C to +125°C 10-Lead MSOP RM-10 DCW
AD5172BRMZ100

2

100 −40°C to +125°C 10-Lead MSOP RM-10 DCV

AD5172BRMZ100-RL7
AD5173BRM2.5 2.5 −40°C to +125°C 10-Lead MSOP RM-10 DCM
AD5173BRM2.5-RL7 2.5 −40°C to +125°C 10-Lead MSOP RM-10 DCM
AD5173BRMZ2.5

2

2.5 −40°C to +125°C 10-Lead MSOP RM-10 DCH

AD5173BRMZ2.5-RL7
AD5173BRM10 10 −40°C to +125°C 10-Lead MSOP RM-10 DCQ
AD5173BRM10-RL7 10 −40°C to +125°C 10-Lead MSOP RM-10 DCQ
AD5173BRMZ10
AD5173BRMZ10-RL7

2

10 −40°C to +125°C 10-Lead MSOP RM-10 DCL

2

AD5173BRM50 50 −40°C to +125°C 10-Lead MSOP RM-10 DCN
AD5173BRM50-RL7 50 −40°C to +125°C 10-Lead MSOP RM-10 DCN
AD5173BRMZ50
AD5173BRMZ50-RL7

2

50 −40°C to +125°C 10-Lead MSOP RM-10 DCJ

2

AD5173BRM100 100 −40°C to +125°C 10-Lead MSOP RM-10 DCP
AD5173BRM100-RL7 100 −40°C to +125°C 10-Lead MSOP RM-10 DCP
AD5173BRMZ100

1

The part has a YWW or #YWW label and an assembly lot number label on the bottom side of the package. The Y shows the year that the part was made; for example,

Y = 5 means the part was made in 2005. WW shows the work week that the part was made.

2

Z = RoHS Compliant Part.

2

100 −40°C to +125°C 10-Lead MSOP RM-10 DCK

RAB (kΩ) Temperature Range Package Description Package Option Branding

2.5 −40°C to +125°C 10-Lead MSOP RM-10 DCR

10 −40°C to +125°C 10-Lead MSOP RM-10 DCT

50 −40°C to +125°C 10-Lead MSOP RM-10 DCU

2

100 −40°C to +125°C 10-Lead MSOP RM-10 DCV

2

2.5 −40°C to +125°C 10-Lead MSOP RM-10 DCH

10 −40°C to +125°C 10-Lead MSOP RM-10 DCL

50 −40°C to +125°C 10-Lead MSOP RM-10 DCJ

5.15

4.90

4.65

5

1.10 MAX

SEATING
PLANE

0.23

0.08

8°
0°

(RM-10)

Dimensions shown in millimeters

0.80

0.60

0.40

Rev. H | Page 23 of 24

AD5172/AD5173

NOTES

Purchase of licensed I2C components of Analog Devices, Inc., or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I

©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04103-0-4/09( H)

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Rev. H | Page 24 of 24