Datasheet AD5170 Datasheet (Analog Devices)

256-Position Two-Time Programmable

G

2

I

C Digital Potentiometer

FEATURES

256-position
TTP (two-time programmable) set-and-forget resistance

setting allows second-chance permanent programming

Unlimited adjustments prior to OTP (one-time

programming) activation

OTP overwrite allows dynamic adjustments with user

defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: t
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins AD0 and AD1
Single-supply 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power, I
Wide operating temperature: –40°C to +125°C
Evaluation board and software are available
Software replaces µC in factory programming applications

APPLICATIONS

Systems calibration
Electronics level setting
Mechanical Trimmers® replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

GENERAL OVERVIEW

The AD5170 is a 256-position, two-time programmable (TTP)
digital potentiometer
enable two opportunities at permanently programming the
resistance setting. OTP is a cost-effective alternative to EEMEM
for users who do not need to program the digital potentiometer
setting in memory more than once. This device performs the
same electronic adjustment function as mechanical
potentiometers or variable resistors with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.

= 5 µs typ in power-up

S

= 6 µA maximum

DD

1

that employs fuse link technology to

AD5170

FUNCTIONAL BLOCK DIAGRAM

W

BA

V

DD

ND

AD0

AD1

SDA

SCL

12

ADDRESS

DECODE

The AD5170 is programmed using a 2-wire, I2C® compatible
digital interface. Unlimited adjustments are allowed before
permanently (there are actually two opportunities) setting the
resistance value. During OTP activation, a permanent blow fuse
command freezes the wiper position (analogous to placing
epoxy on a mechanical trimmer).

Unlike traditional OTP digital potentiometers, the AD5170 has
a unique temporary OTP overwrite feature that allows for new
adjustments even after the fuse has been blown. However, the
OTP setting is restored during subsequent power-up
conditions. This feature allows users to treat these digital
potentiometers as volatile potentiometers with a programmable
preset.

For applications that program the AD5170 at the factory,
Analog Devices offers device programming software running
on Windows NT®, 2000, and XP® operating systems. This
software effectively replaces any external I
enhancing the time-to-market of the user’s systems.

1

The terms digital potentiometer, VR, and RDAC are used interchangeably.

FUSE

LINKS

RDAC

REGISTER

SERIAL INPUT

REGISTER

Figure 1.

/

8

04104-0-001

2

C controllers, thus

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5170

TABLE OF CONTENTS

Electrical Characteristics — 2.5 kΩ ............................................... 3

Electrical Characteristics — 10 kΩ, 50 kΩ, 100 kΩ Versions..... 4

Timing Characteristics — 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

Versions.............................................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Typical Performance Characteristics ............................................. 7

Test Circuits..................................................................................... 11

Theory of Operation ...................................................................... 12

One-Time Programming (OTP).............................................. 12

Programming the Variable Resistor and Voltage ................... 12

Programming the Potentiometer Divider............................... 13

ESD Protection ........................................................................... 14

REVISION HISTORY

11/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Electrical Characteristics Table 1............................... 3

Changes to Electrical Characteristics Table 2............................... 4

Changes to One-Time Programming ......................................... 12

Changes to Figure 37, Figure 38, and Figure 39 ........................ 14

Changes to Power Supply Considerations................................... 14

Changes to Figure 40...................................................................... 15

Changes to Layout Considerations .............................................. 15

Terminal Voltage Operating Range ......................................... 14

Power-Up Sequence................................................................... 14

Power Supply Considerations................................................... 14

Layout Considerations............................................................... 15

Evaluation Software/Hardware..................................................... 16

Software Programming ............................................................. 16

2

I

C Interface .................................................................................... 18

2

I

C Compatible 2-Wire Serial Bus ........................................... 20

Pin Configuration and Function Descriptions........................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

11/03—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD5170

ELECTRICAL CHARACTERISTICS — 2.5 kΩ

VDD = 5 V ± 10% or 3 V ±10%, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect –2 ±0.1 +2 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect –6 ±0.75 +6 LSB
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient (∆RAB/RAB)/∆T VAB = VDD, Wiper = no connect 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)

Differential Nonlinearity4 DNL –1.5 ±0.1 +1.5 LSB
Integral Nonlinearity4 INL –2 ±0.6 +2 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF –10 –2.5 0 LSB

WFSE

Code = 0x00 0 2 10 LSB

WZSE

RESISTOR TERMINALS

Voltage Range5 V

GND VDD V

A,VB,VW

Capacitance6 A, B CA, CB f = 1 MHz, measured to GND, code = 0x80 45 pF
Capacitance W CW f = 1 MHz, measured to GND, code = 0x80 60 pF
Shutdown Supply Current7 I

V

A_SD

Common-Mode Leakage ICM V

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
Input Logic Low VIL V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance5 C

5 pF

IL

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage V

2.7 5.5 V

DD RANGE

T

DD_OTP

Supply Current IDD V
OTP Supply Current I
Power Dissipation8 P

V

DD_OTP

V

DISS

Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = midscale ±0.02 ±0.08 %/%

DYNAMIC CHARACTERISTICS9

Bandwidth –3 dB BW_2.5K Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW V
VW Settling Time tS V
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V.

R

N_WB

= 25°C –20 +55 %

A

= 5.5 V 0.01 1 µA

DD

= VB = VDD/2 1 nA

A

= 5 V 2.4 V

DD

= 5 V 0.8 V

DD

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 µA

IN

= 25°C 5.25 5.5 V

A

= 5 V or VIL = 0 V 3.5 6 µA

IH

= 5.5 V, TA = 25°C 100 mA

DD_OTP

= 5 V or VIL = 0 V, VDD = 5 V 30 µW

IH

= 1 V rms, VB = 0 V, f = 1 kHz 0.1 %

A

= 5 V, VB = 0 V, ±1 LSB error band 1 µs

A

= 1.25 kΩ, RS = 0 3.2 nV/√Hz

WB

Rev. A | Page 3 of 24

AD5170

ELECTRICAL CHARACTERISTICS — 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect –1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2

R-INL R
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient (∆RAB/RAB)/∆T VAB = VDD, wiper = no connect 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)

Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB
Integral Nonlinearity4
Voltage Divider Temperature

INL –1 ±0.3 +1 LSB

(∆VW/VW)/∆T

Coefficient
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF –2.5 –1 0 LSB

WFSE

Code = 0x00 0 1 2.5 LSB

WZSE

RESISTOR TERMINALS

Voltage Range5
Capacitance6 A, B
Capacitance6 W
Shutdown Supply Current7 I

VA,VB,VW
CA, CB

C

f = 1 MHz, measured to GND, code = 0x80 60 pF

W

V

A_SD

Common-Mode Leakage ICM V

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
Input Logic Low VIL V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V

C

Input Capacitance6

5 pF

IL

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage8 V

2.7 5.5 V

DD RANGE

5.25 5.5 V

DD_OTP

Supply Current IDD V
OTP Supply Current9 I
Power Dissipation10 P

DD_OTP

V

DISS

Power Supply Sensitivity PSS VDD = 5 V ± 10%, code = midscale ±0.02 ±0.08 %/%

DYNAMIC CHARACTERISTICS11

Bandwidth –3 dB BW RAB = 10 kΩ, code = 0x80 600 kHz
R
R
Total Harmonic Distortion THDW V
VW Settling Time

tS V

(10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

Different from operating power supply, power supply OTP is used one time only.

9

Different from operating current, supply current for OTP lasts approximately 400 ms for one time only.

10

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

11

All dynamic characteristics use VDD = 5 V.

R

N_WB

, VA = no connect –2.5 ±0.25 +2.5 LSB

WB

= 25°C –20 +20 %

A

Code = 0x80 15 ppm/°C

GND VDD V
f = 1 MHz, measured to GND, code = 0x80 45 pF

= 5.5 V 0.01 1 µA

DD

= VB = VDD/2 1 nA

A

= 5 V 2.4 V

DD

= 5 V 0.8 V

DD

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 µA

IN

= 5 V or VIL = 0 V 3.5 6 µA

IH

V

= 5.5 V, TA = 25°C

DD_OTP

= 5 V or VIL = 0 V, VDD = 5 V 30 µW

IH

= 50 kΩ, code = 0x80 100 kHz

AB

= 100 kΩ, code = 0x80 40 kHz

AB

=1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 0.1 %

A

= 5 V, VB = 0 V, ±1 LSB error band 2 µs

A

= 5 kΩ, RS = 0 9 nV/√Hz

WB

100 mA

Rev. A | Page 4 of 24

AD5170

TIMING CHARACTERISTICS — 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications apply to all parts)

SCL Clock Frequency f
t

Bus Free Time between STOP and START t1 1.3 µs

BUF

t

Hold Time (Repeated START) t2

HD;STA

t

Low Period of SCL Clock t3 1.3 µs

LOW

t

High Period of SCL Clock t4 0.6 µs

HIGH

t

Setup Time for Repeated START Condition t5 0.6 µs

SU;STA

t

Data Hold Time2 t

HD;DAT

t

Data Setup Time t7 100 ns

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
t

Setup Time for STOP Condition t10 0.6 µs

SU;STO

1

See timing diagrams for locations of measured values.

2

The maximum t

has only to be met if the device does not stretch the LOW period (t

HD;DAT

400 kHz

SCL

After this period, the first clock

0.6 µs

pulse is generated.

0.9 µs

6

) of the SCL signal.

LOW

Rev. A | Page 5 of 24

AD5170

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Value

VDD to GND –0.3 V to +7 V
VA, VB, VW to GND VDD
Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx1

Pulsed ±20 mA
Continuous ±5 mA

Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T

) 150°C

JMAX

Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2 θJA: MSOP-10 230°C/W

1

Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

– TA)/θJA.

JMAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 24

AD5170

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.5

1.0

0.5

0

–0.5

–1.0

RHEOSTAT MODE INL (LSB)

–1.5

–2.0

VDD = 2.7V

Figure 2. R-INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

RHEOSTAT MODE DNL (LSB)

–0.3

–0.4

–0.5

Figure 3. R-DNL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE INL (LSB)

–0.4

–0.5

Figure 4. INL vs. Code vs. Temperature

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 2.7V

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 5.5V
T

= –40°C, +25°C, +85°C, +125°C

A

VDD = 2.7V

= –40°C, +25°C, +85°C, +125°C

T

A

1289632 640 160 192 224 256

CODE (DECIMAL)

TA = 25°C
R

= 10kΩ

AB

TA = 25°C
R

= 10kΩ

AB

RAB = 10kΩ

04104-0-002

04104-0-003

04104-0-004

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL (LSB)

–0.4

–0.5

VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C

1289632 640 160 192 224 256

CODE (DECIMAL)

RAB = 10kΩ

04104-0-005

Figure 5. DNL vs. Code vs. Temperature

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE INL (LSB)

–0.8

–1.0

VDD = 2.7V

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 5.5V

TA = 25°C
R

= 10kΩ

AB

04104-0-006

Figure 6. INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL (LSB)

–0.4

–0.5

VDD = 2.7V

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

TA = 25°C
R

= 10kΩ

AB

04104-0-007

Figure 7. DNL vs. Code vs. Supply Voltages

Rev. A | Page 7 of 24

AD5170

2.0

VDD = 2.7V

1.5
TA = –40°C, +25°C, +85°C, +125°C

1.0

0.5

RAB = 10kΩ

4.50
RAB = 10kΩ

3.75

3.00

0

–0.5

–1.0

RHEOSTAT MODE INL (LSB)

–1.5

–2.0

Figure 8. R-INL vs. Code vs. Temperature

0.5

0.4

0.3

0.2

VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C

0.1

0

–0.1

–0.2

RHEOSTAT MODE DNL (LSB)

–0.3

–0.4

–0.5

Figure 9. R-DNL vs. Code vs. Temperature

2.0

1.5

1.0

0.5

0

–0.5

–1.0

FSE, FULL-SCALE ERROR (LSB)

–1.5

VDD = 2.7V, VA = 2.7V

VDD = 5.5V
T

= –40°C, +25°C, +85°C, +125°C

A

1289632 640 160 192 224 256

CODE (DECIMAL)

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 5.5V, VA = 5.0V

RAB = 10kΩ

RAB = 10kΩ

04104-0-008

04104-0-009

2.25

1.50

ZSE, ZERO-SCALE ERROR (LSB)

0.75

VDD = 2.7V, VA = 2.7V

VDD = 5.5V, VA = 5.0V

0

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 11. Zero-Scale Error vs. Temperature

10

A)

µ

1

, SUPPLY CURRENT (

DD

I

0.1
–40 –7 26 59 92 125

VDD = 5V

VDD = 3V

TEMPERATURE (°C)

Figure 12. Supply Current vs. Temperature

120

100

80

60

40

20

RHEOSTAT MODE TEMPCO (ppm/°C)

0

VDD = 2.7V
T

= –40°C TO +85°C, –40°C TO +125°C

A

VDD = 5.5V
T

= –40°C TO +85°C, –40°C TO +125°C

A

RAB = 10kΩ

04104-0-011

04104-0-012

–2.0

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 10. Full-Scale Error vs. Temperature

04104-0-010

Rev. A | Page 8 of 24

–20

CODE (DECIMAL)

Figure 13. Rheostat Mode Tempco ∆R

1289632 640 160 192 224 256

/∆T vs. Code

WB

04104-0-013

AD5170

50

40

30

VDD = 2.7V
T

20

10

0

–10

–20

POTENTIOMETER MODE TEMPCO (ppm/°C)

–30

= –40°C TO +85°C, –40°C TO +125°C

A

VDD = 5.5V
T

= –40°C TO +85°C, –40°C TO +125°C

A

CODE (DECIMAL)

Figure 14. Potentiometer Mode Tempco ∆V

1289632 640 160 192 224 256

RAB = 10kΩ

/∆T vs. Code

WB

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

10k 1M100k 10M

Figure 15. Gain vs. Frequency vs. Code, R

0x80

0x40
0x20
0x10

0x08
0x04

0x010x02

FREQUENCY (Hz)

= 2.5 kΩ

AB

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 100k10k 1M

Figure 16. Gain vs. Frequency vs. Code, R

0x80

0x40

0x20
0x10
0x08
0x04

0x02
0x01

FREQUENCY (Hz)

= 10 kΩ

AB

04104-0-014

04104-0-015

04104-0-016

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 100k10k 1M

Figure 17. Gain vs. Frequency vs. Code, R

0x80

0x40

0x20
0x10

0x08
0x04
0x02
0x01

FREQUENCY (Hz)

AB

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 100k10k 1M

Figure 18. Gain vs. Frequency vs. Code, R

0x80

0x40

0x20

0x10

0x08
0x04
0x02
0x01

FREQUENCY (Hz)

AB

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

100kΩ
60kHz

50kΩ
120kHz

10kΩ
570kHz

2.5kΩ

2.2MHz

10k1k 100k 1M 10M

FREQUENCY (Hz)

Figure 19. –3 dB Bandwidth at Code = 0x80

04104-0-017

= 50 kΩ

04104-0-018

= 100 kΩ

04104-0-019

Rev. A | Page 9 of 24

AD5170

10

TA = 25°C

1

0.1

, SUPPLY CURRENT (mA)

DD

I

0.01
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VDD = 2.7V

DIGITAL INPUT VOLTAGE (V)

Figure 20. I

VDD = 5.5V

vs. Input Voltage

DD

V

W

SCL

04104-0-020

V

V

SCL

W

Figure 22. Midscale Glitch, Code 0x80 to 0x7F

W

04104-0-025

04104-0-023

Figure 21. Digital Feedthrough

04104-0-021

Figure 23. Large Signal Settling Time

Rev. A | Page 10 of 24

AD5170

V

TEST CIRCUITS

Figure 24 to Figure 29 illustrate the test circuits that define the
test conditions used in the product specification tables.

V+ = V

DUT

A

V+

W

B

DD

1LSB = V+/2

V

MS

N

04104-0-026

Figure 24. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

NO CONNECT

DUT

A

W

B

I

W

V

MS

04104-0-027

Figure 25. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

MS2

DUT

A

W

B

V

W

IW = VDD/R

V

MS1

RW = [V

NOMINAL

MS1

– V

MS2

]/I

W

04104-0-028

Figure 26. Test Circuit for Wiper Resistance

V

A

DUT

A

∆V

DD

V+

W

B

V+ = VDD± 10%
PSRR (dB) = 20 LOG
PSS (%/%) =

V

MS

∆VMS%
∆VDD%

∆V

MS

( )

∆V

DD

Figure 27. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

OFFSET

GND

DUT

A

V

IN

2.5V

W

B

+15V

AD8610

–15V

V

OUT

04104-0-030

Figure 28. Test Circuit for Gain vs. Frequency

NC

DUT

GND

A

B

NC

V

DD

I

W

CM

NC = NO CONNECT

V

CM

04104-0-032

Figure 29. Test Circuit for Common-Mode Leakage Current

04104-0-029

Rev. A | Page 11 of 24

AD5170

THEORY OF OPERATION

SCL

SDA

2

C INTERFACE

I

COMPARATOR

ONE-TIME

PROGRAM/TEST

CONTROL BLOCK

Figure 30. Detailed Functional Block Diagram

The AD5170 is a 256-position, digitally controlled variable
resistor (VR) that employs fuse link technology to achieve
memory retention of resistance setting.

An internal power-on preset places the wiper at midscale
during power-on. If the OTP function has been activated, the
device powers up at the user-defined permanent setting.

ONE-TIME PROGRAMMING (OTP)

Prior to OTP activation, the AD5170 presets to midscale during
initial power-on. After the wiper is set at the desired position,
the resistance can be permanently set by programming the T bit
high along with the proper coding (see Table 7 and Table 8) and
one time V
AD517x family of digital pots requires V
and 5.5 V to blow the fuses to achieve a given nonvolatile
setting. On the other hand, V
operation. As a result, system supply that is lower than 5.25 V
requires external supply for one-time programming. Note that
the user is allowed only one attempt in blowing the fuses. If the
user fails to blow the fuses at the first attempt, the fuses’
structures may have changed such that they may never be
blown regardless of the energy applied at subsequent events. For
details, see the Power Supply Considerations section.

The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses have
been blown, all fuse latches are enabled upon subsequent
power-on; therefore, the output corresponds to the stored
setting. Figure 30 shows a detailed functional block diagram.

. Note that fuse link technology of the

DD_OTP

can be 2.7 V to 5.5 V during

DD

between 5.25 V

DD_OTP

A

W

B

04103-0-026

DAC

REG.

FUSES

EN

MUX

FUSE

REG.

DECODER

PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE

Rheostat Operation

The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance (R
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of 256
possible settings.

A

W

B

Figure 31. Rheostat Mode Configuration

Assuming a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminal W and
Terminal B. The second connection is the first tap point, which
corresponds to 139 Ω (R
for data 0x01. The third connection is the next tap point, repre­senting 178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on.
Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at 10,100 Ω (R

) of the VR has 256 contact points

AB

A

W

B

= RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω)

WB

A

B

W

+ 2 × RW).

AB

04103-0-027

Rev. A | Page 12 of 24

AD5170

For R

= 10 kΩ and the B terminal open-circuited, the

AB

following output resistance, R

is set for the RDAC latch

WA ,

codes, as shown in Table 6.

SD BIT

A

R

S

D7
D6
D5
D4
D3
D2
D1
D0

RDAC

LATCH

AND

DECODER

Figure 32. AD5170 Equivalent RDAC Circuit

R

S

R

S

W

R

S

B

04104-0-034

The general equation that determines the digitally programmed
output resistance between Terminal W and Terminal B is

D

DR ×+×= 2

)(

128

(1)

WABWB RR

where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, R

is the wiper resistance contributed by the on resistance of

R

W

is the end-to-end resistance, and

AB

the internal switch.

In summary, if R
circuited, the output resistance R

= 10 kΩ and the A terminal is open-

AB

is set for the RDAC latch

WB

codes, as shown in Table 5.

Table 5. Codes and Corresponding R

Resistance

WB

D (Dec.) RWB (Ω) Output State

255 9,961 Full Scale (RAB – 1 LSB + RW)
128 5,060 Midscale
1 139 1 LSB
0 100 Zero Scale (Wiper Contact Resistance)

Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between Terminal W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or possible destruction of the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper, Terminal W, and Terminal A also
produces a digitally controlled complementary resistance, R

.

WA

When these terminals are used, the B terminal can be opened.
Setting the resistance value for R

starts at a maximum value

WA

of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is

–256

)(

DR ×+×= 2

D

128

(2)

WABWA RR

Table 6. Codes and Corresponding R

Resistance

WA

D (Dec.) RWA (Ω) Output State

255 139 Full Scale
128 5,060 Midscale
1 9,961 1 LSB
0 10,060 Zero Scale

Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. Since the resistance element is pro­cessed using thin film technology, the change in R

AB

with

temperature has a very low 35 ppm/°C temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of V
positive, voltage across A–B, W–A, and W–B can be at either
polarity.

V

I

Figure 33. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at V

with respect to ground for any valid input

W

voltage applied to Terminal A and Terminal B is

D

256

V

+=

DV

)(

For a more accurate calculation, which includes the effect of
wiper resistance, V

DV

W

can be found as

W

WB

)( +=

R

AB

DR

)(

V

Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, R
solute values. Thus, the temperature drift reduces to 15 ppm/°C.

to GND, which must be

DD

A

W

V

O

B

D

256

−

256

WA

A

(3)

V

BAW

)(

DR

V

(4)

R

B

AB

and RWB, and not the ab-

WA

04104-0-035

Rev. A | Page 13 of 24

AD5170

2

ESD PROTECTION

All digital inputs—SDA, SCL, AD0, and AD1—are protected
with a series input resistor and parallel Zener ESD structures, as
shown in Figure 34 and Figure 35.

340Ω

LOGIC

GND

Figure 34. ESD Protection of Digital Pins

04104-0-037

fuse programming supply (either an on-board regulator or
rack-mount power supply) must be rated at 5.25 V to 5.5 V and
able to provide a 100 mA current for 400 ms for successful one­time programming. Once fuse programming is completed, the

supply must be removed to allow normal operation at

V

DD_OTP

2.7 V to 5.5 V and the device will consume current in µA range.
Figure 37 shows the simplest implementation of a dual supply
requirement by using a jumper. This approach saves one voltage
supply, but draws additional current and requires manual
configuration.

A, B, W

GND

04104-0-038

Figure 35. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

The AD5170 VDD to GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera­tion. Supply signals present on Terminal A, Terminal B, and
Terminal W that exceed V

or GND will be clamped by the

DD

internal forward-biased diodes (see Figure 36).

V

DD

A

W

B

GND

04104-0-039

Figure 36. Maximum Terminal Voltages Set by V

and GND

DD

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance
at Te r mi n al A , Te r mi n al B , a n d Ter min al W (s e e F i gu r e 3 6 ), i t i s
important to power V

/GND before applying any voltage to

DD

Terminal A, Terminal B, and Terminal W. Otherwise, the diode
will be forward biased such that V

is powered unintentionally

DD

and may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, V
The relative order of powering V

, the digital inputs, and then VA/VB/VW.

DD

, VB, VW, and the digital

A

inputs is not important as long as they are powered after

/GND.

V

DD

POWER SUPPLY CONSIDERATIONS

To minimize the package pin count, both the one-time pro­gramming and normal operating voltage supplies share the
same V
link technology that requires 5.25 V to 5.5 V for blowing the
internal fuses to achieve a given setting, but normal V
anywhere between 2.7 V and 5.5 V after the fuse programming
process. As a result, dual voltage supplies and isolation are
needed if system V

terminal of the AD5170. The AD5170 employs fuse

DD

DD

is lower than the required V

DD

DD_OTP

. The

can be

5.5V
R1 50kΩ

R2

250kΩ

CONNECT J1 HERE

FOR OTP

C1

10µFC21nF

CONNECT J1 HERE

AFTER OTP

V

DD

AD5170

04104-0-049

Figure 37. Power Supply Requirement

An alternate approach in 3.5 V to 5.25 V systems adds a signal
diode between the system supply and the OTP supply for
isolation, as shown in Figure 38.

APPLY FOR OTP ONLY

5.5V

3.5V–5.25V

D1

C1

1µFC21nF

V

DD

AD5170

04104-0-050

Figure 38. Isolate 5.5 V OTP Supply from 3.5 V to 5.25 V Normal Operating

Supply. The V

5.5V
R1

10kΩ

.7V

P1

P1=P2=FDV302P, NDS0610

must be removed once OTP is completed.

DD_OTP

APPLY FOR OTP ONLY

V

DD

AD5170

P2

C1

10µFC21nF

Figure 39. Isolate 5.5 V OTP Supply from 2.7 V Normal Operating Supply.

The V

supply must be removed once OTP is completed.

DD_OTP

For users who operate their systems at 2.7 V, use of the
bidirectional low threshold P-Ch MOSFETs is recommended
for the supply’s isolation. As shown in Figure 39, this assumes

04104-0-051

Rev. A | Page 14 of 24

AD5170

V

the 2.7 V system voltage is applied first, and the P1 and P2 gates
are pulled to ground, thus turning on P1 and subsequently P2.
As a result, V
AD5170 setting is found, the factory tester applies the V
to both the V

of the AD5170 approaches 2.7 V. When the

DD

DD_OTP

and the MOSFETs gates turning off P1 and P2.

DD

The OTP command is executed at this time to program the
AD5170 while the 2.7 V source is protected. Once the fuse
programming is completed, the tester withdraws the V

DD_OTP

and the setting for AD5170 is permanently fixed.

AD5170 achieves the OTP function through blowing internal
fuses. Users should always apply the 5.25 V to 5.5 V one-time
program voltage requirement at the first fuse programming
attempt. Failure to comply with this requirement may lead to a
change in the fuse structures, rendering programming
inoperable.

LAYOUT CONSIDERATIONS

It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.

Note that the digital ground should also be joined remotely to
the analog ground at one point to minimize the ground bounce.

V

DD

+

C1

10µFC21nF

DD

AD5170

Poor PCB layout introduces parasitics that may affect the fuse
programming. Therefore, it is recommended to add a 10 µF
tantalum capacitor in parallel with a 1 nF ceramic capacitor as
close as possible to the V

pin. The type and value chosen for

DD

both capacitors are important. This combination of capacitor
values provides both a fast response and larger supply current
handling with minimum supply droop during transients. As a
result, these capacitors increase the OTP programming success
by not inhibiting the proper energy needed to blow the internal
fuses. Additionally, C1

minimizes transient disturbance and low
frequency ripple while C2 reduces high frequency noise during
normal operation.

Figure 40. Power Supply Bypassing

GND

04104-0-040

Rev. A | Page 15 of 24

AD5170

EVALUATION SOFTWARE/HARDWARE

Figure 41. AD5170 Computer Software Interface

There are two ways of controlling the AD5170. Users can either
program the devices with computer software or external I
controllers.

2

C

SOFTWARE PROGRAMMING

Due to the advantages of the one-time programmable feature,
users may consider programming the device in the factory
before shipping the final product to end-users. ADI offers
device programming software that can be implemented in the
factory on PCs running Windows® 95 or later. As a result,
external controllers are not required, which significantly
reduces development time. The program is an executable file
that does not require knowledge of any programming languages
or programming skills. It is easy to set up and to use. Figure 41
shows the software interface. The software can be downloaded
from www.analog.com.

The AD5170 starts at midscale after power-up prior to OTP
programming. To increment or decrement the resistance, the
user may simply move the scrollbars on the left. To write any
specific value, the user should use the bit pattern in the upper
screen and press the Run button. The format of writing data to
the device is shown in Table 7. Once the desired setting is
found, the user presses the Program Permanent button to blow
the internal fuse links.

To read the validation bits and data from the device, the user
simply presses the Read button. The format of the read bits is
shown in Table 8.

To apply the device programming software in the factory, users
must modify a parallel port cable and configure Pin 2, Pin 3,
Pin 15, and Pin 25 for SDA_write, SCL, SDA_read, and DGND,
respectively, for the control signals (Figure 42). Users should
also lay out the PCB of the AD5170 with SCL and SDA pads, as
shown in Figure 43, such that pogo pins can be inserted for
factory programming.

Rev. A | Page 16 of 24

AD5170

13
25
12
24
11
23
10
22
9
21
8
20

7
19
6
18
5
17
4
16
3
15
2
14
1

R3

100Ω

R2

100Ω

R1

100Ω

READ

WRITE

SCL

SDA

04104-0-042

Figure 42. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,

Pin 15 = SDA_read, and Pin 25 = DGND.

AD0
GND
VDD

Figure 43. Recommended AD5170 PCB Layout. The SCL and SDA pads allow

pogo pins to be inserted so that signals can be communicated through the

parallel port for programming (Figure 42).

AD5170

B
A

W
NC
AD1
SDA
SCL

04104-0-043

Rev. A | Page 17 of 24

AD5170

I2C INTERFACE

Table 7. Write Mode

W

S 0 1 0 1 1 AD1 AD0

Slave Address Byte Instruction Byte Data Byte

Table 8. Read Mode

S 0 1 0 1 1 AD1 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A E1 E0 X X X X X X A P

Slave Address Byte Instruction Byte Data Byte

A 2T SD T 0 OW X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P

S = Start Condition.

P = Stop Condition.

A = Acknowledge.

AD0, AD1 = Package Pin Programmable Address Bits.

X = Don’t Care.

W

= Write.

R = Read.

2T = Second fuse link array for two-time programming. Logic 0
corresponds to first trim. Logic 1 corresponds to second trim.
Note that blowing trim #2 before trim #1 effectively disables
trim #1 and in turn only allows one-time programming.

SD = Shutdown connects wiper to B terminal and open circuits
the A terminal. It does not change the contents of the wiper
register.

T = OTP Programming Bit. Logic 1 permanently programs the
wiper.

OW = Overwrite the fuse setting and program the digital
potentiometer to a different setting. Note that upon power-up,
the digital potentiometer presets to either midscale or fuse
setting depending on whether the fuse link has been blown.

D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.

E1, E0 = OTP Validation Bits.

0, 0 = Ready to Program.

1, 0 = Fatal Error. Some fuses not blown. Do not retry.
Discard this unit.

1, 1 = Programmed Successfully. No further adjustments are
possible.

Rev. A | Page 18 of 24

AD5170

t

2

SCL

t

8

t

t

6

9

SDA

START BY
MASTER

START BY
MASTER

t

1

PS

1

SCL

01

SDA

SLAVE ADDRESS BYTE

1

SCL

01

SDA

SLAVE ADDRESS BYTE

t

0 1 1 AD1 AD0

FRAME 1

0 1 1 AD1 AD0

FRAME 1

t

2

3

t

4

t

9

t

8

2

Figure 44. I

R/W A0 SD 0 OW X X X

ACK BY
AD5170

C Interface Detailed Timing Diagram

19

T

INSTRUCTION BYTE

FRAME 2

t

7

Figure 45. Writing to the RDAC Register

19

R/W D7 D6 D4 D3 D2 D1 D0

ACK BY
AD5170

D5

FRAME 2

INSTRUCTION BYTE

Figure 46. Reading Data from the RDAC Register

t

5

S

19

D7 D6 D5 D4 D3

ACK BY
AD5170

19

E1 E0 X X X

ACK BY
MASTER

FRAME 3

DATA BYTE

FRAME 3

DATA BYTE

D2 D1 D0

XXX

t

10

P

9

ACK BY
AD5170

STOP BY

MASTER

9

NO ACK
BY MASTER

STOP BY

MASTER

04104-0-044

04104-0-045

04104-0-046

Rev. A | Page 19 of 24

AD5170

I2C COMPATIBLE 2-WIRE SERIAL BUS

The 2-wire I2C serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 45). The
following byte is the slave address byte, which consists of
the slave address followed by an R/

mines whether data is read from, or written to, the slave
device). AD0 and AD1 are configurable address bits which
allow up to four devices on one bus (see Table 7).

The slave address corresponding to the transmitted address
bits responds by pulling the SDA line low during the ninth
clock pulse (this is termed the Acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to, or read from,
its serial register. If the R/

bit is high, the master will read

W
from the slave device. If the R/

write to the slave device.

2. In the write mode, the second byte is the instruction byte.

The first bit (MSB), 2T, of the instruction byte is the
second trim enable bit. A logic low selects the first array of
fuses, and a logic high selects the second array. This means
that after blowing the fuses with trim#1, the user still has
another chance to blow them again with trim#2. Note that
using trim#2 before trim#1 effectively disables trim#1 and,
in turn, only allows one-time programming.

The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to
note that the shutdown operation does not disturb the
contents of the register. When brought out of shutdown,
the previous setting is applied to the RDAC. Also, during
shutdown, new settings can be programmed. When the
part is returned from shutdown, the corresponding VR
setting is applied to the RDAC.

The third MSB, T, is the OTP (one-time programmable)
programming bit. A logic high blows the poly fuses and
programs the resistor setting permanently. For example, if
the user wanted to blow the first array of fuses, the
instruction byte would be 00100XXX. To blow the second
array of fuses, the instruction byte would be 10100XXX. A
logic low of the T bit simply allows the device to act as a
typical volatile digital potentiometer.

The fourth MSB must always be at Logic 0.

bit (this bit deter-

W

bit is low, the master will

W

The fifth MSB, OW, is an overwrite bit. When raised to a
logic high, OW allows the RDAC setting to be changed
even after the internal fuses have been blown. However,
once OW is returned to a logic zero, the position of the
RDAC returns to the setting prior to overwrite. Because
OW is not static, if the device is powered off and on, the
RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether the fuses have
been permanently set.

The remainder of the bits in the instruction byte are Don’t
Care bits (see Figure 45).

After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an Acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see
Figure 44).

3. In the read mode, the data byte follows immediately after

the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference from the write mode, with eight
data bits followed by an Acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 46).

Following the data byte, the validation byte contains two
validation bits, E0 and E1. These bits signify the status of
the one-time programming (see Figure 46).

4. After all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line

th

high during the 10

clock pulse to establish a STOP

condition (see Figure 45). In read mode, the master issues a

th

No Acknowledge for the 9

clock pulse (i.e., the SDA line

remains high). The master then brings the SDA line low

th

before the 10

clock pulse, which goes high to establish a

STOP condition (see Figure 46).

A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in the write mode, the
RDAC output updates on each successive byte. If different
instructions are needed, the write/read mode has to start again
with a new slave address, instruction, and data byte. Similarly, a
repeated read function of the RDAC is also allowed.

Rev. A | Page 20 of 24

AD5170

Table 9. Validation Status

E1 E0 Status

0 0 Ready for Programming.
1 0

Fatal Error. Some fuses not blown. Do not retry.
Discard this unit.

1 1 Successful. No further programming is possible.

Multiple Devices on One Bus

Figure 47 shows four AD5170s on the same serial bus. Each has
a different slave address because the states of their AD0 and
AD1 pins are different. This allows each device on the bus to be
written to, or read from, independently. The master device

2

output bus line drivers are open-drain pull-downs in a fully I

C

compatible interface.

MASTER

5V

R

PRP

5V

SDA

AD1

AD0

AD5170

SCL

SCL

SDA

AD1

AD0

AD5170

Figure 47. Multiple AD5170s on One I

5V

SDA

AD1

AD0

AD5170

SCL

2

C Bus

5V

SDA

AD1

AD0

AD5170

SCL

SDA

SCL

04104-0-047

Rev. A | Page 21 of 24

AD5170

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD0

1

B

2

A

3

AD5170

TOP VIEW

4

5

DD

10

W

9

NC

8

AD1

7

SDAGND

6

SCLV

04104-0-048

Figure 48. Pin Configuration

Table 10. Pin Function Descriptions

Pin Mnemonic Description

1 B B Terminal.
2 A A Terminal.
3 AD0 Programmable Address Bit 0 for Multiple Package Decoding.
4 GND Digital Ground.
5 VDD Positive Power Supply.
6 SCL Serial Clock Input. Positive Edge Triggered.
7 SDA Serial Data Input/Output.
8 AD1 Programmable Address Bit 1 for Multiple Package Decoding.
9 NC No Connect.
10 W W Terminal.

Rev. A | Page 22 of 24

AD5170

OUTLINE DIMENSIONS

3.00 BSC

6

10

3.00 BSC

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.00

0.27

0.17

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 49. 10-Lead Mini Small Outline Package [MSOP]

ORDERING GUIDE

Model RAB (kΩ) Temperature Package Description Package Option Branding

AD5170BRM2.5 2.5 –40°C to +125°C MSOP-10 RM-10 D0Y
AD5170BRM2.5-RL7 2.5 –40°C to +125°C MSOP-10 RM-10 D0Y
AD5170BRM10 10 –40°C to +125°C MSOP-10 RM-10 D0Z
AD5170BRM10-RL7 10 –40°C to +125°C MSOP-10 RM-10 D0Z
AD5170BRM50 50 –40°C to +125°C MSOP-10 RM-10 D0W
AD5170BRM50-RL7 50 –40°C to +125°C MSOP-10 RM-10 D0W
AD5170BRM100 100 –40°C to +125°C MSOP-10 RM-10 D0X
AD5170BRM100-RL7 100 –40°C to +125°C MSOP-10 RM-10 D0X
AD5170EVAL1 Evaluation Board

1

The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

4.90 BSC

5

1.10 MAX

SEATING
PLANE

0.23

0.08

(RM-10)

Dimensions shown in millimeters

8°
0°

0.80

0.60

0.40

Rev. A | Page 23 of 24

AD5170

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04104–0–11/04(A)

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Rev. A | Page 24 of 24