Datasheet AD5162 Datasheet (ANALOG DEVICES)

Dual 256-Position SPI

A

www.BDTIC.com/ADI

FEATURES

2-channel, 256-position
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: t
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pin AD0
Computer software replaces µC in factory programming

applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: I
Wide operating temperature: −40°C to +125°C
Evaluation board available

APPLICATIONS

Systems calibrations
Electronics level settings
Mechanical Trimmers® replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

GENERAL DESCRIPTION

The AD5162 provides a compact 3 mm × 4.9 mm packaged
solution for dual 256-position adjustment applications. This
device performs the same electronic adjustment function as a
3-terminal mechanical potentiometer. Available in four different
end-to-end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ),
this low temperature coefficient device is ideal for high accu­racy and stability variable resistance adjustments. The wiper
settings are controllable through an SPI digital interface. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code
transferred into the RDAC

1

The terms digital potentiometer, VR, and RDAC are used interchangeably.

= 5 µs typical on power-up

S

= 6 µA max

DD

1

latch.

Digital Potentiometer

AD5162

FUNCTIONAL BLOCK DIAGRAM

1

V

DD

GND

CLK

SDI

CS

REGISTER 1

A = 0 A = 1

Operating from a 2.7 V to 5.5 V power supply and consuming
less than 6 µA allows the AD5162 to be used in portable
battery-operated applications.

For applications that program the AD5162 at the factory,
Analog Devices offers device programming software running
on Windows® NT/2000/XP operating systems. This software
effectively replaces any external SPI controllers, which in turn
enhances users’ systems time-to-market. An AD5162 evaluation
kit and software are available. The kit includes a cable and
instruction manual.

W1

WIPER

SPI INTERFACE

B1 W2

WIPER

REGISTER 2

Figure 1.

B2

AD5162

04108-0-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5162

www.BDTIC.com/ADI

TABLE OF CONTENTS

Electrical Characteristics—2.5 kΩ Version................................... 3

Programming the Potentiometer Divider............................... 14

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4

Timing Characteristics—All Versions ........................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Pin Configuration......................................................................... 7

Pin Function Descriptions .......................................................... 7

Typical Performance Characteristics ............................................. 8

Tes t Ci rc u it s ..................................................................................... 12

Theory of Operation ...................................................................... 13

Pro g ram m ing t he Vari a bl e Re s ist o r a n d Vol ta g e .................... 13

REVISION HISTORY

11/03 Changed from REV. 0 to REV. A:

Changes to Electrical Characteristics.................................... Page 3

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range.......................................... 14

Power-Up Sequence ................................................................... 14

Layout and Power Supply Bypassing ....................................... 15

Constant Bias to Retain Resistance Setting............................. 15

Evaluation Board ........................................................................ 15

SPI Interface .................................................................................... 16

SPI Compatible 3-Wire Serial Bus ........................................... 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

11/03 Revision 0: Initial Version

Rev. A | Page 2 of 20

AD5162

www.BDTIC.com/ADI

ELECTRICAL CHARACTERISTICS—2.5 kΩ VERSION

Table 1. VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance

2

2

3

R-DNL RWB, VA = no connect −2 ±0.1 +2 LSB
R-INL RWB, VA = no connect −6 ±0.75 +6 LSB
∆R

AB

TA = 25°C −20 +55 %
Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect 35 ppm/°C
R

(Wiper Resistance) R

WB

WB

Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity

4

DNL −1.5 ±0.1 +1.5 LSB
Integral Nonlinearity INL −2 ±0.6 +2 LSB
Voltage Divider Temperature

(∆V

)/∆T Code = 0x80 15 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

WFSE

WZSE

Code = 0xFF −10 −2.5 0 LSB
Code = 0x00 0 2 10 LSB

RESISTOR TERMINALS

Voltage Range
Capacitance6 A, B C

5

V

A, B, W

A, B

GND V
f = 1 MHz, measured to GND, Code =

45 pF

0x80

Capacitance6 W C

W

f = 1 MHz, measured to GND, Code =

60 pF

0x80

Common-Mode Leakage I

CM

VA = VB = VDD/2 1 nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

6

IH

IL

IH

IL

IL

C

IL

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
VIN = 0 V or 5 V ±1 µA
5 pF

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

7

DD RANGE

DD

P

DISS

2.7 5.5 V
VIH = 5 V or VIL = 0 V 3.5 6 µA
VIH = 5 V or VIL = 0 V, VDD = 5 V 30 µW

Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = midscale ±0.02 ±0.08 %/%

DYNAMIC CHARACTERISTICS

8

Bandwidth −3 dB BW_2.5 K Code = 0x80 4.8 MHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage Density e

See notes at end of section.

W

S

N_WB

VA = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VA = 5 V, VB = 0 V, ±1 LSB error band 1 µs
RWB = 1.25 kΩ, RS = 0 3.2

1

Max Unit

DD

V

nV/√Hz

Rev. A | Page 3 of 20

AD5162

www.BDTIC.com/ADI

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 2. VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < 125°C; unless otherwise noted

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance

2

2

3

R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB
R-INL RWB, VA = no connect −2.5 ±0.25 +2.5 LSB
∆R

AB

TA = 25°C −20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect 35 ppm/°C
RWB (Wiper Resistance) R

WB

Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity
Integral Nonlinearity

4

4

DNL −1 ±0.1 +1 LSB

INL −1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

WFSE

WZSE

Code = 0xFF −2.5 −1 0 LSB
Code = 0x00 0 1 2.5 LSB

RESISTOR TERMINALS

Voltage Range
Capacitance6 A, B C

5

V

A,B,W

A,B

GND V
f = 1 MHz, measured to GND,

45 pF

Code = 0x80

Capacitance6 W C

W

f = 1 MHz, measured to GND,

60 pF

Code = 0x80

Common-Mode Leakage I

CM

VA = VB = VDD/2 1 nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance C

IH

IL

IH

IL

IL

IL

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
VIN = 0 V or 5 V ±1 µA
5 pF

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation P

DD RANGE

DD

DISS

Power Supply Sensitivity PSS

2.7 5.5 V
VIH = 5 V or VIL = 0 V 3.5 6 µA
VIH = 5 V or VIL = 0 V, VDD = 5 V 30 µW

= 5 V ± 10%, Code =

V

DD

±0.02 ±0.08 %/%

midscale

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB BW

= 10 kΩ/50 kΩ/100 kΩ,

R

AB

600/100/40 kHz

Code = 0x80

Total Harmonic Distortion THD

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) t

S

W

VA = 1 V rms, VB = 0 V,
f = 1 kHz, R

= 10 kΩ

AB

VA = 5 V, VB = 0 V,

0.1 %

2 µs

±1 LSB error band

Resistor Noise Voltage Density e

See notes at end of section.

N_WB

RWB = 5 kΩ, RS = 0 9

1

Max Unit

V

DD

nV/√Hz

Rev. A | Page 4 of 20

AD5162

www.BDTIC.com/ADI

TIMING CHARACTERISTICS—ALL VERSIONS

Table 3. VDD = +5 V ± 10%, or +3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted

Parameter Symbol Conditions Min Typ

SPI INTERFACE TIMING CHARACTERISTICS9 (Specifications Apply to All Parts)

Clock Frequency f
Input Clock Pulse Width tCH, t
Data Setup Time t
Data Hold Time t
CS Setup Time

CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup

See notes at end of section.

CLK

Clock level high or low 20 ns
5 ns
5 ns
15 ns

40 ns
0 ns
0 ns
10 ns

DS

DH

t

CSS

t

CSW

t

CSH0

t

CSH1

t

CS1

CL

NOTES

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

8

All dynamic characteristics use VDD = 5 V.

9

See timing diagrams for locations of measured values.

1

Max Unit

25 MHz

Rev. A | Page 5 of 20

AD5162

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 4. TA = 25°C, unless otherwise noted

Parameter Value

VDD to GND –0.3 V to +7 V
VA, VB, VW to GND V
Terminal Current, Ax to Bx, Ax to Wx,

Bx to Wx

Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 s) 300°C
Thermal Resistance2 θJA: MSOP-10

1

Maximum terminal current is bounded by the maximum current handling of

2

Package power dissipation = (T

1

Pulsed ±20 mA
Continuous ±5 mA

JMAX

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

− TA)/θJA.

JMAX

DD

) 150°C

230°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 20

AD5162

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN CONFIGURATION

1

B1

2

A1

3

W2

4

5

DD

AD5162

TOP VIEW

Figure 2.

10

W1

9

B2

8

CS

7

SDIGND

6

CLKV

04108-0-002

PIN FUNCTION DESCRIPTIONS

Table 5.

Pin
No.

1 B1 B1 Terminal.
2 A1 A1 Terminal.
3 W2 W2 Terminal.
4 GND Digital Ground.
5 V
6 CLK

7 SDI Serial Data Input.
8

9 B2 B2 Terminal.
10 W1 W1 Terminal.

Mnemonic Description

DD

Positive Power Supply.
Serial Clock Input. Positive edge

triggered.

Chip Select Input, Active Low. When CS

CS

returns high, data is loaded into the DAC
register.

Rev. A | Page 7 of 20

AD5162

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.5

1.0

0.5

0

–0.5

–1.0

RHEOSTAT MODE INL (LSB)

–1.5

–2.0

VDD = 2.7V

Figure 3. R-INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

RHEOSTAT MODE DNL (LSB)

–0.3

–0.4

–0.5

Figure 4. R-DNL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE INL (LSB)

–0.4

–0.5

Figure 5. INL vs. Code vs. Temperature

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 2.7V

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 5.5V
T

= –40°C, +25°C, +85°C, +125°C

A

VDD = 2.7V
T

= –40°C, +25°C, +85°C, +125°C

A

1289632 640 160 192 224 256

CODE (DECIMAL)

TA = 25°C
R

= 10kΩ

AB

TA = 25°C
R

= 10kΩ

AB

RAB = 10kΩ

04108-0-003

04108-0-004

04108-0-005

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL (LSB)

–0.4

–0.5

VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C

1289632 640 160 192 224 256

CODE (DECIMAL)

RAB = 10kΩ

04108-0-006

Figure 6. DNL vs. Code vs. Temperature

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE INL (LSB)

–0.8

–1.0

VDD = 2.7V

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 5.5V

TA = 25°C
R

= 10kΩ

AB

04108-0-007

Figure 7. INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL (LSB)

–0.4

–0.5

VDD = 2.7V

VDD = 5.5V

1289632 640 160 192 224 256

CODE (DECIMAL)

TA = 25°C
R

= 10kΩ

AB

04108-0-008

Figure 8. DNL vs. Code vs. Supply Voltages

Rev. A | Page 8 of 20

AD5162

www.BDTIC.com/ADI

2.0

1.5

1.0

0.5

VDD = 2.7V
T

= –40°C, +25°C, +85°C, +125°C

A

RAB = 10kΩ

4.50
RAB = 10kΩ

3.75

3.00

0

–0.5

–1.0

RHEOSTAT MODE INL (LSB)

–1.5

–2.0

Figure 9. R-INL vs. Code vs. Temperature

0.5

0.4

0.3

0.2

VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C

0.1

0

–0.1

–0.2

RHEOSTAT MODE DNL (LSB)

–0.3

–0.4

–0.5

Figure 10. R-DNL vs. Code vs. Temperature

2.0

1.5

1.0

0.5

0

–0.5

–1.0

FSE, FULL-SCALE ERROR (LSB)

–1.5

VDD = 2.7V, VA = 2.7V

VDD = 5.5V
T

= –40°C, +25°C, +85°C, +125°C

A

1289632 640 160 192 224 256

CODE (DECIMAL)

1289632 640 160 192 224 256

CODE (DECIMAL)

VDD = 5.5V, VA = 5.0V

RAB = 10kΩ

RAB = 10kΩ

04108-0-009

04108-0-010

2.25

1.50

ZSE, ZERO-SCALE ERROR (LSB)

0.75

VDD = 2.7V, VA = 2.7V

VDD = 5.5V, VA = 5.0V

0

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 12. Zero-Scale Error vs. Temperature

10

A)

µ

1

, SUPPLY CURRENT (

DD

I

0.1
–40 –7 26 59 92 125

VDD = 5V

VDD = 3V

TEMPERATURE (°C)

Figure 13. Supply Current vs. Temperature

120

100

80

60

40

20

RHEOSTAT MODE TEMPCO (ppm/°C)

0

VDD = 2.7V
T

= –40°C TO +85°C, –40°C TO +125°C

A

VDD = 5.5V
T

= –40°C TO +85°C, –40°C TO +125°C

A

RAB = 10kΩ

04108-0-012

04108-0-013

–2.0

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 11. Full-Scale Error vs. Temperature

04108-0-011

–20

Figure 14. Rheostat Mode Tempco ∆R

Rev. A | Page 9 of 20

1289632 640 160 192 224 256

CODE (DECIMAL)

/∆T vs. Code

WB

04108-0-014

AD5162

www.BDTIC.com/ADI

50

40

30

VDD = 2.7V
T

20

10

0

–10

–20

POTENTIOMETER MODE TEMPCO (ppm/°C)

–30

Figure 15. Potentiometer Mode Tempco ∆V

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

10k 1M100k 10M

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 100k10k 1M

= –40°C TO +85°C, –40°C TO +125°C

A

VDD = 5.5V
T

= –40°C TO +85°C, –40°C TO +125°C

A

1289632 640 160 192 224 256

CODE (DECIMAL)

0x80

0x40
0x20
0x10

0x08
0x04

0x010x02

FREQUENCY (Hz)

Figure 16. Gain vs. Frequency vs. Code, R

0x80

0x40

0x20
0x10
0x08
0x04

0x02
0x01

FREQUENCY (Hz)

Figure 17. Gain vs. Frequency vs. Code, R

RAB = 10kΩ

/∆T vs. Code

WB

= 2.5 kΩ

AB

= 10 kΩ

AB

0

0x80

0x40

0x20
0x10

0x08
0x04
0x02
0x01

FREQUENCY (Hz)

= 50 kΩ

AB

04108-0-018

04108-0-015

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 100k10k 1M

Figure 18. Gain vs. Frequency vs. Code, R

0

0x80

0x40

0x20

0x10

0x08
0x04
0x02
0x01

FREQUENCY (Hz)

= 100 kΩ

AB

04108-0-019

04108-0-016

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 100k10k 1M

Figure 19. Gain vs. Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

04108-0-017

100kΩ
60kHz

50kΩ
120kHz

10kΩ
570kHz

2.5kΩ

2.2MHz

10k1k 100k 1M 10M

FREQUENCY (Hz)

Figure 20. –3 dB Bandwidth @ Code = 0x80

04108-0-020

Rev. A | Page 10 of 20

AD5162

www.BDTIC.com/ADI

10

TA = 25°C

1

0.1

, SUPPLY CURRENT (mA)

DD

I

0.01
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VDD = 2.7V

DIGITAL INPUT VOLTAGE (V)

Figure 21. I

VDD = 5.5V

vs. Input Voltage

DD

V

W

CLK

04108-0-025

V

W2

V

W1

04108-0-024

Figure 24. Analog Crosstalk

V

W

04108-0-021

Figure 22. Digital Feedthrough

V

W2

V

W1

04108-0-022

V

CS

Figure 23. Digital Crosstalk

Figure 25. Midscale Glitch, Code 0x80 to 0x7F

W

Figure 26. Large Signal Settling Time

04108-0-026

04108-0-023

Rev. A | Page 11 of 20

AD5162

V

www.BDTIC.com/ADI

TEST CIRCUITS

Figure 27 through Figure 32 illustrate the test circuits that
define the test conditions used in the product specification
tables.

V+ = V

DUT

A

V+

W

B

Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error

(INL, DNL)

NO CONNECT

DUT

A

W

B

Figure 28. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

MS2

DUT

A

W

B

V

W

V

MS1

IW = VDD/R

Figure 29. Test Circuit for Wiper Resistance

DD

1LSB = V+/2

V

MS

I

W

V

MS

NOMINAL

RW = [V

MS1

N

04108-0-027

04108-0-028

– V

MS2

]/I

W

04108-0-029

V

A

DUT

A

∆V

DD

V+

W

B

V+ = VDD± 10%
PSRR (dB) = 20 LOG
PSS (%/%) =

V

MS

∆VMS%
∆VDD%

∆V

MS

( )

∆V

DD

04108-0-030

Figure 30. Test Circuit for Power Supply Sensitivity

(PSS, PSSR)

OFFSET

GND

DUT

A

V

IN

2.5V

W

B

+15V

AD8610

–15V

V

OUT

04108-0-031

Figure 31. Test Circuit for Gain vs. Frequency

NC

DUT

GND

NC

A

W

B

V

DD

Figure 32. Test Circuit for Common-Mode Leakage Current

I

CM

NC = NO CONNECT

V

CM

04108-0-033

Rev. A | Page 12 of 20

AD5162

−

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD5162 is a 256-position digitally controlled variable
resistor (VR) device.

The general equation determining the digitally programmed
output resistance between W and B is

An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.

PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE

Rheostat Operation

The nominal resistance of the RDAC between terminals A and
B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance (R
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.

Assuming that a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
139 Ω (R
0x01. The third connection is the next tap point, representing
178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 Ω (R

) of the VR has 256 contact points accessed by

AB

A

W

B

Figure 33. Rheostat Mode Configuration

= RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for data

WB

D7
D6
D5
D4
D3
D2
D1
D0

DECODER

Figure 34. AD5162 Equivalent RDAC Circuit

RDAC

LATCH

AND

A

W

B

R

S

R

S

R

S

R

S

A

W

B

+ 2 × RW).

AB

A

W

B

04108-0-035

04108-0-034

WB

256

D

DR ×+×= 2

)(

AB

(1)

RR

W

where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.

is the end-to-end resistance.

R

AB

is the wiper resistance contributed by the ON resistance of

R

W

the internal switch.

In summary, if R
circuited, the following output resistance R

= 10 kΩ and the A terminal is open

AB

is set for the

WB

indicated RDAC latch codes.

Table 6. Codes and Corresponding R

Resistance

WB

D (Dec) RWB (Ω) Output State

255 9,961 Full scale (RAB − 1 LSB + RW)
128 5,060 Midscale
1 139 1 LSB
0 100 Zero scale (wiper contact resistance)

Note that, in the zero-scale condition, a finite wiper resistance
of 100 Ω is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance R

. When these

WA

terminals are used, the B terminal can be opened. Setting the
resistance value for R

starts at a maximum value of resistance

WA

and decreases as the data loaded in the latch increases in value.
The general equation for this operation is

D

256

DR ×+×

= 2

)(

256

= 10 kΩ and the B terminal open circuited, the

For R

AB

following output resistance R

ABWA

WA

(2)

RR

W

is set for the indicated RDAC

latch codes.

Table 7. Codes and Corresponding R

Resistance

WA

D (Dec) RWA (Ω) Output State

255 139 Full scale
128 5,060 Midscale
1 9,961 1 LSB
0 10,060 Zero scale

Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. Because the resistance element is
processed in thin film technology, the change in R

AB

with

temperature has a very low 35 ppm/°C temperature coefficient.

Rev. A | Page 13 of 20

AD5162

www.BDTIC.com/ADI

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.

V

I

Figure 35. Potentiometer Mode Configuration

to GND, which must be

DD

A

W

V

O

B

04108-0-036

ESD PROTECTION

All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures shown in Figure 36 and
Figure 37. This applies to the digital input pins SDI, CLK,

CS

and

.

340Ω

LOGIC

GND

Figure 36. ESD Protection of Digital Pins

A, B, W

04108-0-037

If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt­age applied across terminal AB divided by the 256 positions of
the potentiometer divider. The general equation defining the
output voltage at V

with respect to ground for any valid input

W

voltage applied to terminals A and B is

D

DV

W

V

)(

256

+=

A

256

256

D

−

(3)

V

B

A more accurate calculation, which includes the effect of wiper
resistance, V

, is

W

DR

DR

)(

WB

DV

)( +=

W

V

A

R

AB

WA

)(

(4)

V

B

R

AB

Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R

and RWB and not the

WA

absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.

GND

Figure 37. ESD Protection of Resistor Terminals

04108-0-038

TERMINAL VOLTAGE OPERATING RANGE

The AD5162 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera­tion. Supply signals present on terminals A, B, and W that
exceed V

or GND are clamped by the internal forward biased

DD

diodes (see Figure 38).

V

DD

A

W

B

GND

04108-0-039

Figure 38. Maximum Terminal Voltages Set by V

and GND

DD

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 38), it is important to
power V
and W; otherwise, the diode is forward biased such that V
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
of powering V
as long as they are powered after V

/GND before applying any voltage to terminals A, B,

DD

DD

, digital inputs, and then VA, VB, VW. The relative order

DD

, VB, VW, and the digital inputs is not important

A

/GND.

DD

is

Rev. A | Page 14 of 20

AD5162

www.BDTIC.com/ADI

LAYOUT AND POWER SUPPLY BYPASSING

It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disc or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electro­lytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 39). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.

V

DD

+

C3

10µFC10.1µF

Figure 39. Power Supply Bypassing

V

DD

AD5162

GND

04108-0-040

110%

108%

106%

104%

102%

100%

98%

96%

BATTERY LIFE DEPLETED

94%

92%

90%

0

51015

Figure 40. Battery Operating Life Depletion

DAYS

TA= 25

°C

20 25 30

04108-0-041

EVALUATION BOARD

An evaluation board, along with all necessary software, is
available to program the AD5162 from any PC running
Windows 98/2000/XP. The graphical user interface, as shown in
Figure 41, is straightforward and easy to use. More detailed
information is available in the user manual, which comes with
the board.

CONSTANT BIAS TO RETAIN RESISTANCE SETTING

For users who desire nonvolatility but cannot justify the addi­tional cost for the EEMEM, the AD5162 may be considered as a
low cost alternative by maintaining a constant bias to retain the
wiper setting. The AD5162 is designed specifically with low
power in mind, which allows low power consumption even in
battery-operated systems. The graph in Figure 40 demonstrates
the power consumption from a 3.4 V 450 mAhr Li-Ion cell
phone battery, which is connected to the AD5162. The measure­ment over time shows that the device draws approximately

1.3 µA and consumes negligible power. Over a course of
30 days, the battery is depleted by less than 2%, the majority of
which is due to the intrinsic leakage current of the battery itself.

This demonstrates that constantly biasing the potentiometer is
not an impractical approach. Most portable devices do not
require the removal of batteries for the purpose of charging.
Although the resistance setting of the AD5162 is lost when the
battery needs replacement, such events occur rather infre­quently such that this inconvenience is justified by the lower
cost and smaller size offered by the AD5162. If and when total
power is lost, the user should be provided with a means to
adjust the setting accordingly.

Figure 41. AD5162 Evaluation Board Software

The AD5162 starts at midscale upon power-up. To increment or
decrement the resistance, the user may simply move the scroll­bars on the left. To write any specific value, the user should use
the bit pattern in the upper screen and press the Run button.
The format of writing data to the device is shown in Table 8.

Rev. A | Page 15 of 20

AD5162

)

www.BDTIC.com/ADI

SPI INTERFACE

SPI COMPATIBLE 3-WIRE SERIAL BUS

The AD5162 contains a 3-wire SPI compatible digital interface
(SDI,

first. The format of the word is shown in Table 8.

The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When

loads data into the serial register on each positive clock edge
(see Figure 42).

The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5162 uses a
9-bit serial input data register word that is transferred to the
internal RDAC register when the

Extra MSB bits are ignored.

, and CLK). The 9-bit serial word must be loaded MSB

CS

is low, the clock

CS

line returns to logic high.

CS

Table 8. Serial Data-Word Format

B8 B7 B6 B5 B4 B3 B2 B1 B0

A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB

8

2

7

2

2

0

V

SDI

CLK

CS

OUT

1
0

1
0

1
0

1
0

A0 D7 D6 D5 D4 D3 D2 D1 D0

RDAC REGISTER LOAD

Figure 42. SPI Interface Timing Diagram

= 5 V, VB = 0 V, VW = V

(V

A

OUT

)

04108-0-042

SDI

(DATA IN

CLK

V

OUT

1

CSHO

Dx Dx

t

CH

t

CSS

t

DS

CS

0

1

0

t

1

0

V

DD

0

Figure 43. SPI Interface Detailed Timing Diagram (V

t

CSH1

t

CS1

t

CSW

t

S

±1LSB

04108-0-043

t

CH

t

CL

= 5 V, VB = 0 V, VW = V

A

OUT

)

Rev. A | Page 16 of 20

AD5162

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

3.00 BSC

6

10

3.00 BSC

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.00

0.27

0.17

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 44. 10-Lead Mini Small Outline Package [MSOP]

4.90 BSC

5

1.10 MAX

SEATING
PLANE

Dimensions shown in millimeters

(RM-10)

0.23

0.08

8°
0°

0.80

0.60

0.40

ORDERING GUIDE

Model RAB (Ω) Temperature Package Description Package Option Branding

AD5162BRM2.5 2.5 k –40°C to +125°C MSOP-10 RM-10 D0Q
AD5162BRM2.5-RL7 2.5 k –40°C to +125°C MSOP-10 RM-10 D0Q
AD5162BRM10 10 k –40°C to +125°C MSOP-10 RM-10 D0R
AD5162BRM10-RL7 10 k –40°C to +125°C MSOP-10 RM-10 D0R
AD5162BRM50 50 k –40°C to +125°C MSOP-10 RM-10 D0S
AD5162BRM50-RL7 50 k –40°C to +125°C MSOP-10 RM-10 D0S
AD5162BRM100 100 k –40°C to +125°C MSOP-10 RM-10 D0T
AD5162BRM100-RL7 100 k –40°C to +125°C MSOP-10 RM-10 D0T
AD5162EVAL See Note 1 Evaluation Board

1

The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

Rev. A | Page 17 of 20