Datasheet AD5161 Datasheet (Analog Devices)

A

256-Position SPI/I2C Selectable

FEATURES

256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm × 4.9 mm) package Pin selectable SPI/I Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, I Wide operating temperature –40°C SDO output allows multiple device daisy-chaining Evaluation board available

APPLICATIONS

Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment

GENERAL OVERVIEW

The AD5161 provides a compact 3 mm × 4.9 mm packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance.

The wiper settings are controllable through a pin selectable SPI

2

C compatible digital interface, which can also be used to

or I read back the wiper register content. When the SPI mode is used, the device can be daisy-chained (SDO to SDI), allowing several parts to share the same control lines. In the I address pin AD0 can be used to place up to two devices on the same bus. In this same mode, command bits are available to reset the wiper position to midscale or to shut down the device into a state of zero power consumption.

Operating from a 2.7 V to 5.5 V power supply and consuming less than 5 µA allows for usage in portable battery-operated applications.

2

C compatible interface

= 8 µA

DD

to +125°C

2

C mode,

Digital Potentiometer

AD5161

FUNCTIONAL BLOCK DIAGRAM

SDO/NCV

DD

SDI/SDA

CLK/SCL

DIS

CS/AD0

SPI OR I2C

INTERFACE

WIPER

REGISTER

GND

Figure 1.

PIN CONFIGURATION

10

9

8

7

6

W

V

DD

DIS

GND

CLK/SCL

CS/ADO

SDO/NC

SDI/SD

1

A

2

B

3

4

5

AD5161

TOP VIEW

(Not to Scale)

Figure 2.

Note: The terms digital potentiometer, VR, and RDAC are used interchangeably.

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Patent Rights to use these components in an I conforms to the I

2

C Standard Specification as defined by Philips.

2

C system, provided that the system

A

W

B

2

C

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

AD5161

DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, V Resistor Integral Nonlinearity2 R-INL RWB, V Nominal Resistor Tolerance3 ∆RAB T Resistance Temperature Coefficient ∆RAB/∆T VAB = VDD, Wiper = no connect 45 ppm/°C Wiper Resistance RW 50 120 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N 8 Bits Differential Nonlinearity4 DNL –1.5 ±0.1 +1.5 LSB Integral Nonlinearity4 INL –1.5 ±0.6 +1.5 LSB Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C Full-Scale Error V Zero-Scale Error V

Code = 0xFF –6 –2.5 0 LSB

WFSE

Code = 0x00 0 +2 +6 LSB

WZSE

RESISTOR TERMINALS Voltage Range5 V Capacitance6 A, B C

GND VDD V

A,B,W

A,B

Capacitance6 W CW

Shutdown Supply Current7 I

DD_SD

Common-Mode Leakage ICM V DIGITAL INPUTS AND OUTPUTS Input Logic High VIH 2.4 V Input Logic Low VIL 0.8 V Input Logic High VIH V Input Logic Low VIL V Input Current IIL V Input Capacitance6 C

5 pF

IL

POWER SUPPLIES Power Supply Range V

2.7 5.5 V

DD RANGE

Supply Current IDD V Power Dissipation8 P

V

DISS

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth –3dB BW_5K RAB = 5 kΩ, Code = 0x80 1.2 MHz Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 % VW Settling Time tS

Resistor Noise Voltage Density e

RWB = 2.5 kΩ, RS = 0 6 nV/√Hz

N_WB

= no connect –1.5 ±0.1 +1.5 LSB

A

= no connect –4 ±0.75 +4 LSB

A

= 25°C –30 +30 %

A

f = 1 MHz, measured to GND,

45 pF

Code = 0x80 f = 1 MHz, measured to GND,

60 pF

Code = 0x80 VDD = 5.5 V 0.01 1 µA

= VB = VDD/2 1 nA

A

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 µA

IN

= 5 V or VIL = 0 V 3 8 µA

IH

= 5 V or VIL = 0 V, VDD = 5 V 0.2 mW

IH

= +5 V ± 10%,

∆V

DD

±0.02 ±0.05 %/%

Code = Midscale

= 5 V, VB = 0 V, ±1 LSB error

V

A

1 µs

band

Rev. 0 | Page 3 of 20

AD5161

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, V Resistor Integral Nonlinearity2 R-INL RWB, V Nominal Resistor Tolerance3 ∆RAB T Resistance Temperature Coefficient ∆RAB/∆T

Wiper Resistance RW V DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N 8 Bits Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB Integral Nonlinearity4 INL –1 ±0.3 +1 LSB Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C Full-Scale Error V Zero-Scale Error V

Code = 0xFF –3 –1 0 LSB

WFSE

Code = 0x00 0 1 3 LSB

WZSE

RESISTOR TERMINALS Voltage Range5 V Capacitance6 A, B C

GND VDD V

A,B,W

A,B

Capacitance6 W CW

Shutdown Supply Current7 I

DD_SD

Common-Mode Leakage ICM V DIGITAL INPUTS AND OUTPUTS Input Logic High VIH 2.4 V Input Logic Low VIL 0.8 V Input Logic High VIH V Input Logic Low VIL V Input Current IIL V Input Capacitance6 C

5 pF

IL

POWER SUPPLIES Power Supply Range V

2.7 5.5 V

DD RANGE

Supply Current IDD V Power Dissipation8 P

DISS

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth –3dB BW

Total Harmonic Distortion THDW

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS

Resistor Noise Voltage Density e

R

N_WB

= no connect –1 ±0.1 +1 LSB

A

= no connect –2 ±0.25 +2 LSB

A

= 25°C –30 +30 %

A

V

AB

= VDD,

45 ppm/°C

Wiper = no connect

= 5 V 50 120 Ω

DD

f = 1 MHz, measured to

45 pF

GND, Code = 0x80 f = 1 MHz, measured to

60 pF

GND, Code = 0x80 VDD = 5.5 V 0.01 1 µA

= VB = VDD/2 1 nA

A

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 µA

IN

= 5 V or VIL = 0 V 3 8 µA

IH

= 5 V or VIL = 0 V,

V

IH

V

= 5 V

DD

= +5 V ± 10%,

∆V

DD

0.2 mW

±0.02 ±0.05 %/%

Code = Midscale

= 10 kΩ/50 kΩ/100 kΩ,

R

AB

600/100/40 kHz

Code = 0x80

=1 V rms, VB = 0 V,

V

A

f = 1 kHz, R

= 5 V, VB = 0 V,

V

A

= 10 kΩ

AB

0.05 %

2 µs

±1 LSB error band

= 5 kΩ, RS = 0 9 nV/√Hz

WB

Rev. 0 | Page 4 of 20

AD5161

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)

Table 3.

Parameter Symbol Conditions Min Typ1 Max Unit

SPI INTERFACE TIMING CHARACTERISTICS Clock Frequency f Input Clock Pulsewidth tCH, tCL Clock level high or low 20 ns Data Setup Time tDS 5 ns Data Hold Time tDH 5 ns

CS Setup Time CS High Pulsewidth CLK Fall to CS Fall Hold Time CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f t

Bus Free Time between STOP and START t1 1.3 µs

BUF

t

t t t t t

Hold Time (Repeated START) t2

HD;STA

Low Period of SCL Clock t3 1.3 µs

LOW

High Period of SCL Clock t4 0.6 50 µs

HIGH

Setup Time for Repeated START Condition t5 0.6 µs

SU;STA

Data Hold Time t6 0.9 µs

HD;DAT

Data Setup Time t7 100 ns

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8 300 ns tR Rise Time of Both SDA and SCL Signals t9 300 ns t

Setup Time for STOP Condition t10 0.6 µs

SU;STO

NOTES

1

Typical specifications represent average readings at +25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V.

10

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage

level of 1.5 V.

11

See timing diagrams for locations of measured values.

6, 10

(Specifications Apply to All Parts)

CLK

t

15 ns

CSS

40 ns

t

CSW

t

0 ns

CSH0

t

0 ns

CSH1

t

10 ns

CS1

6, 11

(Specifications Apply to All Parts)

400 kHz

SCL

After this period, the first clock pulse is

0.6 µs

25 MHz

generated.

Rev. 0 | Page 5 of 20

AD5161

ABSOLUTE MAXIMUM RATINGS1

(TA = +25°C, unless otherwise noted.)

Table 4

Parameter Value

VDD to GND –0.3 V to +7 V VA, VB, VW to GND VDD

1

I

±20 mA

MAX

Digital Inputs and Output Voltage to GND 0 V to +7 V Operating Temperature Range –40°C to +125°C Maximum Junction Temperature (T

) 150°C

JMAX

Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Thermal Resistance2 θJA: MSOP-10 200°C/W

NOTES

1

Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.

2

Package power dissipation = (T

JMAX

– TA)/θJA.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. 0 | Page 6 of 20

AD5161

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE INL (LSB)

–0.6

–0.8

–1.0

3209664 128 160 192 224 256

Figure 3. R-INL vs. Code vs. Supply Voltages

CODE (Decimal)

5V

3V

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE DNL (LSB)

–0.8

–1.0

64

32096

Figure 6. DNL vs. Code, V

128 160 192 224 256

CODE (Decimal)

= 5 V

DD

–40°C +25°C +85°C

+125°C

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE DNL (LSB)

–0.6

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal)

5V 3V

Figure 4. R-DNL vs. Code vs. Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE INL (LSB)

–0.8

–1.0

3209664 128 160 192 224 256

Figure 5. INL vs. Code, V

CODE (Decimal)

DD

= 5 V

_

40°C +25°C +85°C

+125°C

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE INL (LSB)

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal)

5V 3V

Figure 7. INL vs. Code vs. Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE DNL(LSB)

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal)

5V

3V

Figure 8. DNL vs. Code vs. Supply Voltages

Rev. 0 | Page 7 of 20

AD5161

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE INL (LSB)

–0.6

–0.8

–1.0

–40

°C

+25°C

+85°C

+125°C

3209664 128 160 192 224 256

Figure 9. R-INL vs. Code, V

CODE (Decimal)

DD

= 5 V

2.5

2.0

1.5

1.0

ZSE, ZERO-SCALE ERROR (µA)

0.5

0

0 40 80 120–40

VDD = 5.5V

VDD = 2.7V

TEMPERATURE (°C)

Figure 12. Zero-Scale Error vs. Temperature

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE DNL (LSB)

–0.6

–0.8

–1.0

FSE, FULL-SCALE ERROR (LSB)

2.5

2.0

1.5

1.0

0.5

64

32096

Figure 10. R-DNL vs. Code, V

128 160 192 224 256

CODE (Decimal)

= 5 V

DD

_

40°C +25°C +85°C

+125°C

= 2.7V

V

DD

= 5.5V

V

DD

10

1

SUPPLY CURRENT (µA)

DD

I

0.1

70

60

50

40

30

20

SHUTDOWN CURRENT (nA)

A

I

10

VDD = 5.5V

V

= 2.7V

DD

0 40 80 120–40

TEMPERATURE (°C)

Figure 13. Supply Current vs. Temperature

VDD = 5V

0

0 40 80 120–40

TEMPERATURE (°C)

Figure 11. Full-Scale Error vs. Temperature

Rev. 0 | Page 8 of 20

0

40 80 120–40

TEMPERATURE (°C)

Figure 14. Shutdown Current vs. Temperature

AD5161

g

/

g

VWB/

200

150

100

50

0

RHEOSTAT MODE TEMPCO (ppm/°C)

–50

3209664 128 160 192 224 256

ure 15. Rheostat Mode Tempco ∆R

Fi

CODE (Decimal)

∆T vs. Code

WB

160

140

120

100

80

60

40

20

0

POTENTIOMETER MODE TEMPCO (ppm/°C)

–20

3209664 128 160 192 224 256

ure 16. Potentiometer Mode Tempco ∆

Fi

CODE (Decimal)

∆T vs. Code

REF LEVEL

0.000dB 0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 17. Gain vs. Frequency vs. Code, R

/DIV

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02 0x01

10k 100k 1M

MARKER 1 000 000.000Hz MAG (A/R) –8.918dB

= 5 kΩ

AB

REF LEVEL

0.000dB 0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k 10k 100k 1M

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 18. Gain vs. Frequency vs. Code, R

REF LEVEL

0.000dB 0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 19. Gain vs. Frequency vs. Code, R

REF LEVEL

0.000dB 0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 20. Gain vs. Frequency vs. Code, R

/DIV

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

/DIV

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k 100k 1M

/DIV

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k 100k 1M

MARKER 510 634.725Hz MAG (A/R) –9.049dB

= 10 kΩ

AB

MARKER 100 885.289Hz MAG (A/R) –9.014dB

= 50 kΩ

AB

MARKER 54 089.173Hz MAG (A/R) –9.052dB

= 100 kΩ

AB

Rev. 0 | Page 9 of 20

AD5161

REF LEVEL –5.000dB

–5.5

–6.0

–6.5

–7.0

–7.5

–8.0

–8.5

–9.0

R = 100kΩ

–9.5

–10.0

–10.5

10k 100k 1M 10M

START 1 000.000Hz STOP 1 000 000.000Hz

60

40

PSRR (dB)

20

/DIV

0.500dB

R = 50kΩ

R = 10kΩ

Figure 21. –3 dB Bandwidth @ Code = 0x80

CODE = 0x80, VA= VDD, VB = 0V

PSRR @ VDD = 3V DC ± 10% p-p AC

5kΩ – 1.026 MHz 10kΩ – 511 MHz 50kΩ – 101 MHz 100kΩ – 54 MHz

R = 5kΩ

1

2

Ch 1 200mV

B

Ch 2 5.00 V

W

B

M 100ns A CH2 3.00 V

W

VW

CLK

Figure 24. Digital Feedthrough

VA = 5V VB = 0V

1

2

VW

CS

PSRR @ VDD = 5V DC ± 10% p-p AC

0

Figure 22. PSRR v s. Frequency

900

800

700

600

500

(µA)

400

DD

I

300

200

100

0 10k

Figure 23. I

10k100 100k 1M1k

FREQUENCY (Hz)

VDD= 5V

CODE = 0x55

CODE = 0xFF

100k 1M 10M

FREQUENCY (Hz)

vs. Frequency

DD

Ch 1 100mV

B

Ch 2 5.00 V

W

B

M 200ns A CH1 152mV

W

Figure 25. Midscale Glitch, Code 0x80–0x7F

VA = 5V V

= 0V

B

1

2

Ch 1 5.00V

B

Ch 2 5.00 V

W

B

M 200ns A CH1 3.00 V

W

VW

CS

Figure 26. Large Signal Settling Time, Code 0xFF–0x00

Rev. 0 | Page 10 of 20

AD5161

TEST CIRCUITS

A

OFFSET BIAS

DUT

NC

A

B

W

DUT

A

W

B

RSW=

CODE = 0x00

I

SW

VSS TO V

W

OP279

B

5V

AD8610

0.1V I

SW

DD

I

CM

+15V

–15V

0.1V

V

OUT

V

OUT

V

CM

Figure 27 to Figure 35 illustrate the test circuits that define the test conditions used in the product specification tables.

DUT

A

V+

W

B

Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

NO CONNECT

DUT

A

W

B

Figure 28. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

V

MS2

A

B

V

W

Figure 29. Test Circuit for Wiper Resistance

V

A

V

DD

A

V+

W

B

V+ = V 1LSB = V+/2

V

IW= VDD/R

W

V

RW= [V

MS1

V+ = V

PSRR (dB) = 20 LOG

PSS (%/ %) =

V

MS

DD

N

V

MS

I

W

MS

NOMINAL

– V

]/I

MS2

W

MS1

10%

DD

∆V

MS

( )

∆V

DD

%

∆V

MS

%

∆V

DD

V

IN

OFFSET

GND

Figure 32. Test Circuit for Noninverting Gain

V

IN

OFFSET

GND

2.5V

Figure 33. Test Circuit for Gain vs. Frequency

DUT

W

B

Figure 34. Test Circuit for Incremental ON Resistance

V

DUT

DD

V

GND

SS

Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

DUT

OFFSET BIAS

B

5V

W

OP279

OFFSET

GND

A

V

IN

Figure 31. Test Circuit for Inverting Gain

NC

NC = NO CONNECT

Figure 35. Test Circuit for Common-Mode Leakage current

V

OUT

Rev. 0 | Page 11 of 20

AD5161

V

SPI INTERFACE

Table 5. AD5161 Serial Data-Word Format

B7 B6 B5 B4 B3 B2 B1 B0

D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB

7

2

0

1

SDI

0

1

CLK

0

1

CS

0

1

OUT

0

Figure 36. AD5161 SPI Interface Timing Diagram

D6 D5 D4 D3 D2 D1 D0

D7

RDAC REGISTER LOAD

= 5 V, VB = 0 V, VW = V

(V

A

OUT

)

1

SDI

(DATA IN)

CLK

VOUT

0

1

0

t

1

CS

0

V

DD

0

Figure 37. SPI Interface Detailed Timing Diagram (V

Dx Dx

CSHO

t

CSS

t

CH

DS

t

CL

t

CH

t

CSH1

t

CS1

t

CSW

t

S

±1LSB

= 5 V, VB = 0 V, VW = V

A

OUT

)

Rev. 0 | Page 12 of 20

AD5161

A

Y

I2C INTERFACE

Table 6. Write Mode

S 0 1 0 1 1 0 AD0

Slave Address Byte Instruction Byte Data Byte

Table 7. Read Mode

S 0 1 0 1 1 0 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P

Slave Address Byte Data Byte

A X RS SD X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P

W

S = Start Condition

P = Stop Condition

A = Acknowledge

X = Don’t Care

W

= Write

SCL

SD

PS

SCL

0 1 0 1 1 0 AD0 R/W

SDA

START BY

MASTER

t

8

t

2

t

1

t

3

t

9

t

8

Figure 38. I

ACK BY

FRAME 1 FRAME 2

SLAVE ADDRESS BYTE

AD5161

Figure 39

1 919

SCL

0 1 0 1 1 0 AD0 R/W

SDA

START B

MASTER

FRAME 1

SLAVE ADDRESS BYTE

t

6

t

2

C Interface Detailed Timing Diagram

1 919

XRS X X X X X

. Writing to the RDAC Register

Figure 40. Reading Data from a Previously Selected RDAC Register in Write Mode

9

4

SD

INSTRUCTION BYTE

ACK BY AD5161

R = Read

RS = Reset wiper to Midscale 80

H

SD = Shutdown connects wiper to B terminal and open circuits A terminal. It does not change contents of wiper register.

D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits

t

2

t

7

D7 D6 D5 D4 D3 D2 D1 D0

t

5

19

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY AD5161

FRAME 2

RDAC REGISTER

FRAME 3

DATA BYTE

NO ACK BY MASTER

STOP B MASTER

PS

ACK BY AD5161

t

10

STOP BY MASTER

Rev. 0 | Page 13 of 20

AD5161

−

OPERATION

The AD5161 is a 256-position digitally controlled variable resistor (VR) device.

The general equation determining the digitally programmed output resistance between W and B is

An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between terminals A and B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two or three digits of the part number determine the nominal resistance value, e.g., 10 kΩ = 10; 50 kΩ = 50. The nominal resistance (R the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a 10 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Since there is a 60 Ω wiper contact resistance, such connection yields a minimum of 60 Ω resistance between terminals W and B. The second connection is the first tap point, which corresponds to 99 Ω (R The third connection is the next tap point, representing 177 Ω (2 × 39 Ω + 60 Ω) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 9961 Ω (R a simplified diagram of the equivalent RDAC circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance.

) of the VR has 256 contact points accessed by

AB

= RAB/256 + RW = 39 Ω + 60 Ω) for data 0x01.

WB

– 1 LSB + RW). Figure 41 shows

AB

A

SD BIT

R

S

D7 D6 D5 D4 D3 D2 D1 D0

DECODER

Figure 41. AD5161 Equivalent RDAC Circuit

RDAC

LATCH

AND

R

S

R

S

W

R

S

B

D

DR

)(

where

WB

D

is the decimal equivalent of the binary code loaded in

256

AB

the 8-bit RDAC register,

R

is the wiper resistance contributed by the on resistance of

W

(1)

RR

+×=

W

R

is the end-to-end resistance, and

AB

the internal switch.

In summary, if R circuited, the following output resistance R

= 10 kΩ and the A terminal is open

AB

will be set for the

WB

indicated RDAC latch codes.

Table 8. Codes and Corresponding R

Resistance

WB

D (Dec.) RWB (Ω) Output State

255 9,961 Full Scale (RAB – 1 LSB + RW) 128 5,060 Midscale 1 99 1 LSB 0 60 Zero Scale (Wiper Contact Resistance)

Note that in the zero-scale condition a finite wiper resistance of 60 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementar y resistance R

. When these

WA

terminals are used, the B terminal can be opened. Setting the resistance value for R

starts at a maximum value of resistance

WA

and decreases as the data loaded in the latch increases in value. The general equation for this operation is

256

DR

)(

= 10 kΩ and the B terminal open circuited, the

For R

AB

D

=

256

ABWA

following output resistance R

(2)

RR

+×

W

will be set for the indicated

WA

RDAC latch codes.

Table 9. Codes and Corresponding R

Resistance

WA

D (Dec.) RWA (Ω) Output State

255 99 Full Scale 128 5,060 Midscale 1 9,961 1 LSB 0 10,060 Zero Scale

Typical device to device matching is process lot dependent and may vary by up to ±30%. Since the resistance element is processed in thin film technology, the change in R

AB

with

temperature has a very low 45 ppm/°C temperature coefficient.

Rev. 0 | Page 14 of 20

AD5161

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A-to-B. Unlike the polarity of V positive, voltage across A-B, W-A, and W-B can be at either polarity.

If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at V

with respect to ground for any valid input

W

voltage applied to terminals A and B is

W

256

D

DV

)(

256

V

+=

A

For a more accurate calculation, which includes the effect of wiper resistance, V

)( += (4)

DV

W

, can be found as

W

)(

DR

WB

V

256

A

Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors R absolute values. Therefore, the temperature drift reduces to 15 ppm/°C.

to GND, which must be

DD

D

−

(3)

V

B

256

)(

DR

WA

V

256

B

and RWB and not the

WA

internal RDAC register when the Extra MSB bits are ignored.

Daisy-Chain Operation

The serial data output (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor in order to transfer data to the next package’s SDI pin. This allows for daisy-chaining several RDACs from a single processor serial data line. The pull-up resistor termination voltage can be larger than the V

supply voltage. It is recommended to increase the

DD

clock period when using a pull-up resistor to the SDI pin of the following device because capacitive loading at the daisy-chain node SDO-SDI between devices may induce time delay to subsequent devices. Users should be aware of this potential problem to achieve data transfer successfully (see Figure 42). If two AD5161s are daisy-chained, a total of at least 16 bits of data is required. The first eight bits, complying with the format shown in Table 5, go to U2 and the second eight bits with the same format go to U1.

CS

clocked into their respective serial registers. After this, pulled high to complete the operation and load the RDAC latch. If the data word during the bits, any additional MSBs will be discarded.

µC

MOSI SC

AD5161 AD5161

U1

SDI

CS

line returns to logic high.

should be kept low until all 16 bits are

CS

is

CS

low period is greater than 16

V

DD

R

P

2.2k

Ω

CLKCLK

SDISDO

CS CLK

U2

SDO

PIN SELECTABLE DIGITAL INTERFACE

The AD5161 provides the flexibility of a selectable interface. When the digital interface select (DIS) pin is tied low, the SPI

2

mode is engaged. When the DIS pin is tied high, the I

C mode is

engaged.

SPI Compatible 3-W re Serial Bus (DIS = 0) i

The AD5161 contains a 3-wire SPI compatible digital interface

CS

(SDI, first. The format of the word is shown in Table 5.

The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. When loads data into the serial register on each positive clock edge (see Figure 36).

The data setup and data hold times in the specification table determine the valid timing requirements. The AD5161 uses an 8-bit serial input data register word that is transferred to the

, and CLK). The 8-bit s erial word must be loaded MSB

CS

is low, the clock

Rev. 0 | Page 15 of 20

Figure 42. Daisy-Chain Configuration

I2C Compatible 2-W re Serial Bus (DIS = 1) i

The AD5161 can also be controlled via an I2C compatible serial bus with DIS tied high. The RDACs are connected to this bus as slave devices.

The first byte of the AD5161 is a slave address byte (see Table 6

W

and Table 7). It has a 7-bit slave address and a R/ MSBs of the slave address are 010110, and the following bit is determined by the state of the AD0 pin of the device. AD0

2

allows the user to place up to two of the I

C compatible devices

on one bus.

2

The 2-wire I

C serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 39). The following byte is the slave address byte, which consists of

bit. The six

AD5161

the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device).

The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from

W

its serial register. If the R/ from the slave device. On the other hand, if the R/ low, the master will write to the slave device.

2. A write operation contains an extra instruction byte that a read operation does not contain. Such an instruction byte in write mode follows the slave address byte. The first bit (MSB) of the instruction byte is a don’t care.

The second MSB, RS, is the midscale reset. A logic high on this bit moves the wiper to the center tap where R This feature effectively writes over the contents of the register, and thus, when taken out of reset mode, the RDAC will remain at midscale.

The third MSB, SD, is a shutdown bit. A logic high causes an open circuit at terminal A while shorting the wiper to terminal B. This operation yields almost 0 Ω in rheostat mode or 0 V in potentiometer mode. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting will be applied to the RDAC. Also, during shutdown, new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting will be applied to the RDAC.

The remainder of the bits in the instruction byte are don’t cares (see Table 6).

3. After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Table 6).

4. In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 40).

bit is high, the master will read

W

bit is

= RWB.

WA

5. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 39). In read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse which goes high to establish a STOP condition (see Figure 40).

A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the write cycle, each data byte will update the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output will update after these two bytes. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. If different instructions are needed, the write mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed.

Readback RDAC Value

The AD5161 allows the user to read back the RDAC values in the read mode. Refer to Table 6 and Table 7 for the programming format.

Multiple Devices on One Bus

Figure 43 shows two AD5161 devices on the same serial bus. Each has a different slave address since the states of their AD0 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device

2

output bus line drivers are open-drain pull-downs in a fully I

C

compatible interface.

+5V

R

MASTER

Figure 43. Multiple AD5161 Devices on One I

R

P

+5V

SDA SCL

AD0 AD0

AD5161

SDA SCL

AD5161

2

C Bus

SDA

SCL

Rev. 0 | Page 16 of 20

AD5161

D

LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE

While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V

2

PROM to interface with a 5 V digital potentiometer. A level

E shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer

2

can be stored to and retrieved from the E

PROM. Figure 44 shows one of the implementations. M1 and M2 can be any N-channel signal FETs, or if V

falls below 2.5 V, low threshold

DD

FETs such as the FDV301N.

= 3.3V V

V

DD1

R

SDA1

SCL1

P

3.3V

E2PROM

R

P

G

S

D

M1

R

P

G

S

D

M2

AD5161

Figure 44. Level Shifting for Operation at Different Potentials

=

5V

DD2

R

P

SDA2

SCL2

5V

ESD PROTECTION

All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 45 and Figure 46. This applies to the digital input pins SDI/SDA, CLK/SCL, and CS

/AD0.

340Ω

Figure 45. ESD Protection of Digital Pins

A,B,W

Figure 46. ESD Protection of Resistor Terminals

LOGIC

V

ss

V

SS

TERMINAL VOLTAGE OPERATING RANGE

The AD5161 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed V

or GND will be clamped by the internal forward

DD

biased diodes (see Figure 47).

V

D

A

W

B

V

SS

Figure 47. Maximum Terminal Voltages Set by V

DD

and V

SS

POWER-UP SEQUENCE

Since the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 47), it is important to power

/GND before applying any voltage to terminals A, B, and W;

V

DD

otherwise, the diode will be forward biased such that V

will be

DD

powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, V powering V

, digital inputs, and then V

DD

, VB, VW, and the digital inputs is not important as

A

long as they are powered after V

DD

. The relative order of

A/B/W

/GND.

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 48). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.

V

DD

+

C1C3

10

µ

F 0.1µF

V

DD

AD5161

GND

Figure 48. Power Supply Bypassing

Rev. 0 | Page 17 of 20

AD5161

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN CONFIGURATION

1

A

2

B

3

CS/ADO

4

SDO/NC

5

SDI/SD

AD5161

TOP VIEW

(Not to Scale)

Figure 49.

10

9

8

7

6

W

V

DD

DIS

GND

CLK/SCL

PIN FUNCTION DESCRIPTIONS

Table 10.

Pin Name Description

1 A A Terminal. 2 B B Terminal. 3

CS

/AD0

CS

: Chip Select Input, Active Low. When CS returns high, data will be loaded into the DAC register.

AD0: Programmable address bit 0 for multiple package decoding.

4 SDO/NC

SDO: Serial Data Output. Open-drain transistor requires pull-up resistor.

NC: No Connect.

5 SDI/SDA SDI: Serial Data Input.

SDA: Serial Data Input/Output.

6 CLK/SCL Serial Clock Input. Positive edge triggered. 7 GND Digital Ground. 8 DIS

9 V

DD

10 W

Digital Interface Select (SPI/I SPI when DIS = 0, I

2

C when DIS = 1. Positive Power Supply. W Terminal.

2

C Select).

Rev. 0 | Page 18 of 20

AD5161

3

OUTLINE DIMENSIONS

.00 BSC

6

10

3.00 BSC

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.00

0.27

0.17

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 50. 10-Lead Mini Small Outline Package [MSOP]

4.90 BSC

5

1.10 MAX

SEATING PLANE

0.23

0.20

0.17 8°

0°

(RM-10)

Dimensions shown in millimeters

0.80

0.40

ORDERING GUIDE

Model RAB (Ω) Temperature Package Description Package Option Branding

AD5161BRM5 5k –40°C to +125°C MSOP-10 RM-10 D0C AD5161BRM5-RL7 5k –40°C to +125°C MSOP-10 RM-10 D0C AD5161BRM10 10k –40°C to +125°C MSOP-10 RM-10 D0D AD5161BRM10-RL7 10k –40°C to +125°C MSOP-10 RM-10 D0D AD5161BRM50 50k –40°C to +125°C MSOP-10 RM-10 D0E AD5161BRM50-RL7 50k –40°C to +125°C MSOP-10 RM-10 D0E AD5161BRM100 100k –40°C to +125°C MSOP-10 RM-10 D0F AD5161BRM100-RL7 100k –40°C to +125°C MSOP-10 RM-10 D0F AD5161EVAL See Note 1 Evaluation Board

1

The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

The AD5161 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2358 sq. mil.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 19 of 20

AD5161

NOTES

C03435–0–5/03(0)

Rev. 0 | Page 20 of 20

Datasheet AD5161 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL OVERVIEW

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

TABLE OF CONTENTS

ABSOLUTE MAXIMUM RATINGS1

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

SPI INTERFACE

I2C INTERFACE

OPERATION

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

Daisy-Chain Operation

PIN SELECTABLE DIGITAL INTERFACE

Readback RDAC Value

Multiple Devices on One Bus

LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE

ESD PROTECTION

TERMINAL VOLTAGE OPERATING RANGE

POWER-UP SEQUENCE

LAYOUT AND POWER SUPPLY BYPASSING

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

OUTLINE DIMENSIONS

ORDERING GUIDE

ESD CAUTION