Datasheet AD5160 Datasheet (Analog Devices)

W

B

256-Position SPI Compatible

FEATURES

256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
SPI compatible interface
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, I
Wide operating temperature –40°C
Evaluation board available

APPLICATIONS

Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

GENERAL OVERVIEW

The AD5160 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.

The wiper settings are controllable through an SPI compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.

= 8 µA

DD

to +125°C

Digital Potentiometer

AD5160

FUNCTIONAL BLOCK DIAGRAM

V

DD

CS

SDI

CLK

SPI INTERFACE

WIPER

REGISTER

GND

Figure 1.

PIN CONFIGURATION

V

GND

CLK

W

DD

1

2

AD5160

3

TOP VIEW

(Not to Scale)

4

Figure 2.

A

8

B

7

6

CS

5

SDI

A

Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5160

TABLE OF CONTENTS

Electrical Characteristics—5 kΩ Version ...................................... 3

ESD Protection ........................................................................... 13

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4

Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions 5

Absolute Maximum Ratings ...........................................................5

Typical Performance Characteristics ............................................. 6

Test Circuits..................................................................................... 10

SPI Interface .................................................................................... 11

Operation......................................................................................... 12

Programming the Variable Resistor......................................... 12

Programming the Potentiometer Divider............................... 13

SPI Compatible 3-Wire Serial Bus ........................................... 13

REVISION HISTORY

Revision 0: Initial Version

Terminal Voltage Operating Range.......................................... 13

Power-Up Sequence ................................................................... 13

Layout and Power Supply Bypassing ....................................... 14

Pin Configuration and Function Descriptions........................... 15

Pin Configuration ...................................................................... 15

Pin Function Descriptions ........................................................ 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 16

ESD Caution................................................................................ 16

Rev. 0 | Page 2 of 16

AD5160

ELECTRICAL CHARACTERISTICS—5 kΩ VERSION

(VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, V
Resistor Integral Nonlinearity2 R-INL RWB, V
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient ∆RAB/∆T VAB = VDD, Wiper = no connect 45 ppm/°C
Wiper Resistance RW 50 120 Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1.5 ±0.1 +1.5 LSB
Integral Nonlinearity4 INL –1.5 ±0.6 +1.5 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF –6 –2.5 0 LSB

WFSE

Code = 0x00 0 +2 +6 LSB

WZSE

RESISTOR TERMINALS
Voltage Range5 V
Capacitance6 A, B C

GND VDD V

A,B,W

A,B

Capacitance6 W CW

Shutdown Supply Current7 I

DD_SD

Common-Mode Leakage ICM V
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C

5 pF

IL

POWER SUPPLIES
Power Supply Range V

2.7 5.5 V

DD RANGE

Supply Current IDD V
Power Dissipation8 P

V

DISS

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth –3dB BW_5K RAB = 5 kΩ, Code = 0x80 1.2 MHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS

Resistor Noise Voltage Density e

RWB = 2.5 kΩ, RS = 0 6 nV/√Hz

N_WB

= no connect –1.5 ±0.1 +1.5 LSB

A

= no connect –4 ±0.75 +4 LSB

A

= 25°C –30 +30 %

A

f = 1 MHz, measured to GND,

45 pF

Code = 0x80
f = 1 MHz, measured to GND,

60 pF

Code = 0x80
VDD = 5.5 V 0.01 1 µA

= VB = VDD/2 1 nA

A

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 µA

IN

= 5 V or VIL = 0 V 3 8 µA

IH

= 5 V or VIL = 0 V, VDD = 5 V 0.2 mW

IH

= +5 V ± 10%,

∆V

DD

±0.02 ±0.05 %/%

Code = Midscale

= 5 V, VB = 0 V, ±1 LSB error

V

A

1 µs

band

Rev. 0 | Page 3 of 16

AD5160

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, V
Resistor Integral Nonlinearity2 R-INL RWB, V
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient ∆RAB/∆T

Wiper Resistance RW V
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB
Integral Nonlinearity4 INL –1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF –3 –1 0 LSB

WFSE

Code = 0x00 0 1 3 LSB

WZSE

RESISTOR TERMINALS
Voltage Range5 V
Capacitance6 A, B C

GND VDD V

A,B,W

A,B

Capacitance6 W CW

Shutdown Supply Current7 I

DD_SD

Common-Mode Leakage ICM V
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C

5 pF

IL

POWER SUPPLIES
Power Supply Range V

2.7 5.5 V

DD RANGE

Supply Current IDD V
Power Dissipation8 P

DISS

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth –3dB BW

Total Harmonic Distortion THDW

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS

Resistor Noise Voltage Density e

R

N_WB

= no connect –1 ±0.1 +1 LSB

A

= no connect –2 ±0.25 +2 LSB

A

= 25°C –30 +30 %

A

V

AB

= VDD,

45 ppm/°C

Wiper = no connect

= 5 V 50 120 Ω

DD

f = 1 MHz, measured to

45 pF

GND, Code = 0x80
f = 1 MHz, measured to

60 pF

GND, Code = 0x80
VDD = 5.5 V 0.01 1 µA

= VB = VDD/2 1 nA

A

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 µA

IN

= 5 V or VIL = 0 V 3 8 µA

IH

= 5 V or VIL = 0 V,

V

IH

V

= 5 V

DD

= +5 V ± 10%,

∆V

DD

0.2 mW

±0.02 ±0.05 %/%

Code = Midscale

= 10 kΩ/50 kΩ/100 kΩ,

R

AB

600/100/40 kHz

Code = 0x80

=1 V rms, VB = 0 V,

V

A

f = 1 kHz, R

= 5 V, VB = 0 V,

V

A

= 10 kΩ

AB

0.05 %

2 µs

±1 LSB error band

= 5 kΩ, RS = 0 9 nV/√Hz

WB

Rev. 0 | Page 4 of 16

AD5160

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)

Table 3.

Parameter Symbol Conditions Min Typ1 Max Unit

SPI INTERFACE TIMING CHARACTERISTICS
Clock Frequency f
Input Clock Pulsewidth tCH, tCL Clock level high or low 20 ns
Data Setup Time tDS 5 ns
Data Hold Time tDH 5 ns

CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup

NOTES

1

Typical specifications represent average readings at +25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V.

10

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage

level of 1.5 V.

6, 10

(Specifications Apply to All Parts)

CLK

t

15 ns

CSS

40 ns

t

CSW

t

0 ns

CSH0

t

0 ns

CSH1

t

10 ns

CS1

25 MHz

ABSOLUTE MAXIMUM RATINGS1

(TA = +25°C, unless otherwise noted.)

Table 4.

Parameter Value

VDD to GND –0.3 V to +7 V
VA, VB, VW to GND VDD

1

I

±20 mA

MAX

Digital Inputs and Output Voltage to GND 0 V to +7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T

) 150°C

JMAX

Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2 θJA: MSOP-10 230°C/W

NOTES

1

Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

– TA)/θJA.

JMAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 5 of 16

AD5160

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE INL (LSB)

–0.6

–0.8

–1.0

3209664 128 160 192 224 256

Figure 3. R-INL vs. Code vs. Supply Voltages

CODE (Decimal)

5V

3V

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE DNL (LSB)

–0.8

–1.0

64

32096

Figure 6. DNL vs. Code, V

128 160 192 224 256

CODE (Decimal)

= 5 V

DD

–40°C
+25°C
+85°C

+125°C

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE DNL (LSB)

–0.6

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal)

5V
3V

Figure 4. R-DNL vs. Code vs. Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE INL (LSB)

–0.8

–1.0

3209664 128 160 192 224 256

Figure 5. INL vs. Code, V

CODE (Decimal)

DD

= 5 V

_

40°C

+25°C

+85°C

+125°C

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE INL (LSB)

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal)

5V
3V

Figure 7. INL vs. Code vs. Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE DNL(LSB)

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal)

5V

3V

Figure 8. DNL vs. Code vs. Supply Voltages

Rev. 0 | Page 6 of 16

AD5160

6

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE INL (LSB)

–0.6

–0.8

–1.0

64

32096

Figure 9. R-INL vs. Code, V

128 160 192 224 25

CODE (Decimal)

= 5 V

DD

–40

°C
+25°C
+85°C

+125°C

2.5

2.0

1.5

1.0

ZSE, ZERO-SCALE ERROR (µA)

0.5

0

0 40 80 120–40

0 40 80 120–40

TEMPERATURE (°C)

Figure 12. Zero-Scale Error vs. Temperature

VDD = 5.5V

VDD = 2.7V

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE DNL (LSB)

–0.6

–0.8

–1.0

FSE, FULL-SCALE ERROR (LSB)

3209664 128 160 192 224 256

Figure 10. R-DNL vs. Code, V

2.5

2.0

1.5

1.0

0.5

CODE (Decimal)

DD

= 5 V

_

40°C
+25°C
+85°C

+125°C

= 2.7V

V

DD

= 5.5V

V

DD

10

1

SUPPLY CURRENT (µA)

DD

I

0.1

70

60

50

40

30

20

SHUTDOWN CURRENT (nA)

A

I

10

VDD = 5.5V

V

= 2.7V

DD

0 40 80 120–40

TEMPERATURE (°C)

Figure 13. Supply Current vs. Temperature

VDD = 5V

0

0 40 80 120–40

0 40 80 120–40

TEMPERATURE (°C)

Figure 11. Full-Scale Error vs. Temperature

0

0

40 80 120–40

TEMPERATURE (°C)

Figure 14. Shutdown Current vs. Temperature

Rev. 0 | Page 7 of 16

AD5160

g

/

g

VWB/

200

150

100

50

0

RHEOSTAT MODE TEMPCO (ppm/°C)

–50

160

140

120

100

80

60

40

20

POTENTIOMETER MODE TEMPCO (ppm/°C)

–20

REF LEVEL

0.000dB
0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

START 1 000.000Hz STOP 1 000 000.000Hz

3209664 128 160 192 224 256

ure 15. Rheostat Mode Tempco ∆R

Fi

CODE (Decimal)

0

3209664 128 160 192 224 256

ure 16. Potentiometer Mode Tempco ∆

Fi

CODE (Decimal)

/DIV

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02
0x01

1k

10k 100k 1M

MARKER 1 000 000.000Hz
MAG (A/R) –8.918dB

Figure 17. Gain vs. Frequency vs. Code, R

∆T vs. Code

WB

∆T vs. Code

= 5 kΩ

AB

REF LEVEL

0.000dB
0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k 10k 100k 1M

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 18. Gain vs. Frequency vs. Code, R

REF LEVEL

0.000dB
0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 19. Gain vs. Frequency vs. Code, R

REF LEVEL

0.000dB
0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 20. Gain vs. Frequency vs. Code, R

/DIV

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

/DIV

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k 100k 1M

/DIV

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k 100k 1M

MARKER 510 634.725Hz
MAG (A/R) –9.049dB

= 10 kΩ

AB

MARKER 100 885.289Hz
MAG (A/R) –9.014dB

= 50 kΩ

AB

MARKER 54 089.173Hz
MAG (A/R) –9.052dB

= 100 kΩ

AB

Rev. 0 | Page 8 of 16

AD5160

REF LEVEL
–5.000dB

–5.5

–6.0

–6.5

–7.0

–7.5

–8.0

–8.5

–9.0

R = 100kΩ

–9.5

–10.0

–10.5

10k 100k 1M 10M

START 1 000.000Hz STOP 1 000 000.000Hz

60

40

PSRR (dB)

20

/DIV

0.500dB

5kΩ – 1.026 MHz
10kΩ – 511 MHz
50kΩ – 101 MHz
100kΩ – 54 MHz

R = 50kΩ

R = 10kΩ

R = 5kΩ

Figure 21. –3 dB Bandwidth @ Code = 0x80

CODE = 0x80, VA= VDD, VB = 0V

PSRR @ VDD = 3V DC ± 10% p-p AC

1

2

Ch 1 200mV

B

Ch 2 5.00 V

W

B

M 100ns A CH2 3.00 V

W

VW

CLK

Figure 24. Digital Feedthrough

VA = 5V
VB = 0V

1

2

VW

CS

PSRR @ VDD = 5V DC ± 10% p-p AC

0

Figure 22. PSRR v s. Frequency

900

800

700

600

500

(µA)

400

DD

I

300

200

100

0
10k

Figure 23. I

10k100 100k 1M1k

FREQUENCY (Hz)

VDD= 5V

CODE = 0x55

CODE = 0xFF

100k 1M 10M

FREQUENCY (Hz)

vs. Frequency

DD

Ch 1 100mV

B

Ch 2 5.00 V

W

B

M 200ns A CH1 152mV

W

Figure 25. Midscale Glitch, Code 0x80–0x7F

VA = 5V
V

= 0V

B

1

2

Ch 1 5.00V

B

Ch 2 5.00 V

W

B

M 200ns A CH1 3.00 V

W

VW

CS

Figure 26. Large Signal Settling Time, Code 0xFF–0x00

Rev. 0 | Page 9 of 16

AD5160

TEST CIRCUITS

Figure 27 to Figure 35 illustrate the test circuits that define the
test conditions used in the product specification tables.

DUT

A

V+

W

B

Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

NO CONNECT

DUT

A

W

B

Figure 28. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

V

MS2

A

B

V

W

Figure 29. Test Circuit for Wiper Resistance

V

A

V

DD

A

V+

W

B

V+ = V
1LSB = V+/2

V

IW= VDD/R

W

V

RW= [V

MS1

V+ = V

PSRR (dB) = 20 LOG

PSS (%/ %) =

V

MS

DD

N

V

MS

I

W

MS

NOMINAL

– V

]/I

MS2

W

MS1

10%

DD

∆V

MS

( )

∆V

DD

%

∆V

MS

%

∆V

DD

5V

OFFSET

GND

V

IN

A

OFFSET
BIAS

DUT

OP279

W

B

Figure 32. Test Circuit for Noninverting Gain

OFFSET

GND

A

V

DUT

IN

2.5V

B

+15V

W

AD8610

–15V

Figure 33. Test Circuit for Gain vs. Frequency

0.1V

RSW=

I

DUT

B

W

I

SW

CODE = 0x00

VSS TO V

DD

SW

0.1V

Figure 34. Test Circuit for Incremental ON Resistance

NC

V

DD

V

SS

DUT

GND

A

W

B

I

CM

V

OUT

V

OUT

V

CM

Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

DUT

OFFSET
BIAS

B

5V

W

OP279

V

OUT

OFFSET

GND

A

V

IN

Figure 31. Test Circuit for Inverting Gain

Rev. 0 | Page 10 of 16

NC

NC = NO CONNECT

Figure 35. Test Circuit for Common-Mode Leakage current

AD5160

V

SPI INTERFACE

Table 5. AD5160 Serial Data-Word Format

B7 B6 B5 B4 B3 B2 B1 B0

D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB

7

2

2

0

1

SDI

0

1

CLK

0

1

CS

0

1

OUT

0

Figure 36. AD5160 SPI Interface Timing Diagram

D6 D5 D4 D3 D2 D1 D0

D7

RDAC REGISTER LOAD

= 5 V, VB = 0 V, VW = V

(V

A

OUT

)

1

SDI

(DATA IN)

CLK

CS

VOUT

0

1

0

t

1

0

V

DD

0

Figure 37. SPI Interface Detailed Timing Diagram (V

Dx Dx

CSHO

t

CSS

t

t

CH

DS

t

CL

t

CH

t

CSH1

t

CS1

t

CSW

t

S

±1LSB

= 5 V, VB = 0 V, VW = V

A

OUT

)

Rev. 0 | Page 11 of 16

AD5160

−

OPERATION

The AD5160 is a 256-position digitally controlled variable
resistor (VR) device.

The general equation determining the digitally programmed
output resistance between W and B is

An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between terminals A and
B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two
or three digits of the part number determine the nominal
resistance value, e.g., 10 kΩ = 10; 50 kΩ = 50. The nominal
resistance (R
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings. Assume a 10 kΩ part is used, the wiper’s first
connection starts at the B terminal for data 0x00. Since there is a
60 Ω wiper contact resistance, such connection yields a
minimum of 60 Ω resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
99 Ω (R
The third connection is the next tap point, representing 177 Ω
(2 × 39 Ω + 60 Ω) for data 0x02, and so on. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 9961 Ω (R
a simplified diagram of the equivalent RDAC circuit where the
last resistor string will not be accessed; therefore, there is 1 LSB
less of the nominal resistance at full scale in addition to the
wiper resistance.

) of the VR has 256 contact points accessed by

AB

= RAB/256 + RW = 39 Ω + 60 Ω) for data 0x01.

WB

– 1 LSB + RW). Figure 38 shows

AB

A

R

S

D7
D6
D5
D4
D3
D2
D1
D0

DECODER

Figure 38. AD5160 Equivalent RDAC Circuit

RDAC

LATCH

AND

R

S

R

S

W

R

S

B

D

DR

)(

where

WB

D

is the decimal equivalent of the binary code loaded in

256

AB

the 8-bit RDAC register,

R

is the wiper resistance contributed by the on resistance of

W

(1)

RR

+×=

W

R

is the end-to-end resistance, and

AB

the internal switch.

In summary, if R
circuited, the following output resistance R

= 10 kΩ and the A terminal is open

AB

will be set for the

WB

indicated RDAC latch codes.

Table 6. Codes and Corresponding R

Resistance

WB

D (Dec.) RWB (Ω) Output State

255 9,961 Full Scale (RAB – 1 LSB + RW)
128 5,060 Midscale
1 99 1 LSB
0 60 Zero Scale (Wiper Contact Resistance)

Note that in the zero-scale condition a finite wiper resistance of
60 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementar y resistance R

. When these

WA

terminals are used, the B terminal can be opened. Setting the
resistance value for R

starts at a maximum value of resistance

WA

and decreases as the data loaded in the latch increases in value.
The general equation for this operation is

256

256

D

ABWA

DR

=

)(

= 10 kΩ and the B terminal open circuited, the

For R

AB

following output resistance R

(2)

RR

+×

W

will be set for the indicated

WA

RDAC latch codes.

Table 7. Codes and Corresponding R

Resistance

WA

D (Dec.) RWA (Ω) Output State

255 99 Full Scale
128 5,060 Midscale
1 9,961 1 LSB
0 10,060 Zero Scale

Typical device to device matching is process lot dependent and
may vary by up to ±30%. Since the resistance element is
processed in thin film technology, the change in R

AB

with

temperature has a very low 45 ppm/°C temperature coefficient.

Rev. 0 | Page 12 of 16

AD5160

D

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of V

to GND, which must be

DD

positive, voltage across A-B, W-A, and W-B can be at either
polarity.

If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at V

with respect to ground for any valid input

W

voltage applied to terminals A and B is

D

DV

W

V

)(

256

A

D

256

−

(3)

256

V

B

+=

For a more accurate calculation, which includes the effect of
wiper resistance, V

)( += (4)

DV

W

, can be found as

W

)(

DR

WB

V

256

A

WA

256

)(

DR

V

B

Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R

and RWB and not the

WA

absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.

SPI COMPATIBLE 3-WIRE SERIAL BUS

The AD5160 contains a 3-wire SPI compatible digital interface

CS

(SDI,
first. The format of the word is shown in Table 5.

The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When
loads data into the serial register on each positive clock edge
(see Figure 36).

The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5160 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the
Extra MSB bits are ignored.

, and CLK). The 8-bit s erial word must be loaded MSB

CS

is low, the clock

CS

line returns to logic high.

ESD PROTECTION

All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 39 and Figure 40.

CS

This applies to the digital input pins SDI, CLK, and

340Ω

Figure 39. ESD Protection of Digital Pins

A,B,W

Figure 40. ESD Protection of Resistor Terminals

LOGIC

V

SS

V

SS

.

TERMINAL VOLTAGE OPERATING RANGE

The AD5160 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed V

or GND will be clamped by the internal forward

DD

biased diodes (see Figure 41).

V

D

A

W

B

V

SS

Figure 41. Maximum Terminal Voltages Set by V

DD

and V

SS

POWER-UP SEQUENCE

Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 41), it is important to power

/GND before applying any voltage to terminals A, B, and W;

V

DD

otherwise, the diode will be forward biased such that V
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
powering V

, digital inputs, and then V

DD

, VB, VW, and the digital inputs is not important as

A

long as they are powered after V

DD

. The relative order of

A/B/W

/GND.

will be

DD

Rev. 0 | Page 13 of 16

AD5160

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.

V

DD

+

C1C3

10

µ

F 0.1µF

V

DD

AD5160

Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disc or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 42). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.

GND

Figure 42. Power Supply Bypassing

Rev. 0 | Page 14 of 16

AD5160

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN CONFIGURATION

1

W

2

V

DD

3

GND

4

CLK

AD5160

TOP VIEW

(Not to Scale)

Figure 43.

PIN FUNCTION DESCRIPTIONS

A

8

B

7

6

CS

5

SDI

Table 8.

Pin Name Description

1 W W Terminal.
2 VDD Positive Power Supply.
3 GND Digital Ground.
4 CLK Serial Clock Input. Positive edge triggered.
5 SDI Serial Data Input.
6

CS

Chip Select Input, Active Low. When

high, data will be loaded into the DAC register.
7 B B Terminal.
8 A A Terminal.

CS

returns

Rev. 0 | Page 15 of 16

AD5160

OUTLINE DIMENSIONS

2.90 BSC

847

1.60 BSC

PIN 1

1.30

1.15

0.90

0.15 MAX

1 3562

1.95
BSC

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178BA

2.80 BSC

0.65 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08

Figure 44. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

8°
4°
0°

0.60

0.45

0.30

ORDERING GUIDE

Model RAB (Ω) Temperature Package Description Package Option Branding

AD5160BRJ5-R2 5k –40°C to +125°C SOT-23-8 RJ-8 D08
AD5160BRJ5-RL7 5k –40°C to +125°C SOT-23-8 RJ-8 D08
AD5160BRJ10-R2 10k –40°C to +125°C SOT-23-8 RJ-8 D09
AD5160BRJ10-RL7 10k –40°C to +125°C SOT-23-8 RJ-8 D09
AD5160BRJ50-R2 50k –40°C to +125°C SOT-23-8 RJ-8 D0A
AD5160BRJ50-RL7 50k –40°C to +125°C SOT-23-8 RJ-8 D0A
AD5160BRJ100-R2 100k –40°C to +125°C SOT-23-8 RJ-8 D0B
AD5160BRJ100-RL7 100k –40°C to +125°C SOT-23-8 RJ-8 D0B
AD5160EVAL See Note 1 Evaluation Board

1

The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

The AD5160 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2,358 sq. mil.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.

C03434–0–5/03(0)

Rev. 0 | Page 16 of 16