Datasheet AD5061 Datasheet (ANALOG DEVICES)

16-Bit V

A

nanoDAC

OUT

™

SPI Interface 2.7 V to 5.5 V, in an SOT-23

FEATURES

Single 16-bit DAC, 4 LSB INL
Power-on reset to midscale or zero-scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Small 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically

2.7 V to 5.5 V power supply
Low glitch on power-up

interrupt facility

SYNC

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5061, a member of ADI’s nanoDAC family, is a low
power, single 16-bit buffered voltage-out DAC that operates
from a single 2.7 V to 5.5 V supply. The part offers a relative
accuracy specification of ±4 LSB and operation is guaranteed
monotonic with a ±1 LSB DNL specification. The part uses a
versatile 3-wire serial interface that operates at clock rates
up to 30 MHz, and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards. The reference for
the AD5061 is supplied from an external V
buffer is also provided on-chip. The part incorporates a power­on reset circuit that ensures the DAC output powers up to mid­scale or zero scale and remains there until a valid write takes
place to the device. The part contains a power-down feature
that reduces the current consumption of the device to typically
330 nA at 5 V and provides software-selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface. Total unadjusted error for the
part is <3 mV. This part exhibits very low glitch on power-up.

pin. A reference

REF

AD5061

FUNCTIONAL BLOCK DIAGRAM

V

REF

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

SCLK DIN

SYNC DACGND

BUF

REF(+)

DAC

POWER-DOWN

CONTROL LO GIC

Figure 1.

Table 1. Related Devices

Part No. Description

AD5062

2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, SOT-23

AD5063

2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, MSOP

AD5040/AD5060

2.7 V to 5.5 V, 14-bit/16-bit nanoDAC D/A,
1 LSB INL, SOT-23

PRODUCT HIGHLIGHTS

1. Available in a small 8-lead SOT-23 package.

2. 16-bit resolution, 4 LSB INL.

3. Low glitch on power-up.

4. High speed serial interface with clock speeds up to 30 MHz.

5. Three power-down modes available to the user.

6. Reset to known output voltage (midscale or zero scale).

V

DD

OUTPUT
BUFFER

AD5061

RESISTOR
NETWORK

V

OUT

GND

04762-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2011 Analog Devices, Inc. All rights reserved.

AD5061

TABLE OF CONTENTS

Features.............................................................................................. 1

Reference Buffer ......................................................................... 15

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 14

Theory of Operation ......................................................................15

DAC Architecture....................................................................... 15

Serial Interface............................................................................ 15

Input Shift Register .................................................................... 15

SYNC

Interrupt ..........................................................................15

Power-On to Zero-Scale or Midscale ...................................... 16

Software Reset............................................................................. 16

Power-Down Modes .................................................................. 16

Microprocessor Interfacing....................................................... 16

Applications..................................................................................... 18

Choosing a Reference ................................................................18

Bipolar Operation....................................................................... 18

Using a Galvanically-Isolated Interface Chip......................... 19

Power Supply Bypassing and Grounding................................ 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

5/11—Rev. A to Rev. B

Changes to Data Sheet Title and Product Highlights Section.... 1

Changes to Ordering Guide.......................................................... 20

1/06—Rev. 0 to Rev. A

Changes to General Description .................................................... 1

Changes to Table 2............................................................................ 3

Changes to Figure 19 Caption....................................................... 10

Added Figure 28 to Figure 36........................................................12

Changes to Serial Interface Section.............................................. 15

Changes to Power-Down Modes Section.................................... 16

Changes to Ordering Guide.......................................................... 20

7/05—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD5061

SPECIFICATIONS

VDD = 5.5 V, V

Table 2.

B Grade1
Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution 16 Bits
Relative Accuracy (INL)2 ±0.5 ±4 LSB −40°C to +85°C, B grade
±0.5 ±4 −40°C to +125°C, Y grade
Total Unadjusted Error (TUE) ±0.5 ±3.0 mV −40°C to +85°C, B grade
±0.5 ±3.0 −40°C to +125°C, Y grade
Differential Nonlinearity (DNL) ±0.5 ±1 LSB Guaranteed monotonic, −40°C to +85°C, B grade
±0.5 ±1

Gain Error ±0.01 ±0.05 % of FSR TA = −40°C to +85°C, B grade
±0.01 ±0.05 TA = −40°C to +125°C , Y grade
Gain Error Temperature Coefficient 1 ppm of FSR/°C
Offset Error ±0.02 ±3.0 mV TA = −40°C to + 85°C, B grade
±0.02 ±3.0 TA = −40°C to + 125°C, Y grade
Offset Error Temperature Coefficient 0.5 µV/°C
Full-Scale Error ±0.05 ±3.0 mV

±0.05 ±3.0

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 V
Output Voltage Settling Time 4 µs

Output Noise Spectral Density 64
Output Voltage Noise 6 µV p-p DAC code = midscale , 0.1 Hz to 10 Hz bandwidth

Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, RL = 5 KΩ
Digital Feedthrough 0.003 nV-s DAC code = full-scale
DC Output Impedance (Normal) 0.015 Ω Output impedance tolerance ±10%
DC Output Impedance (Power-Down)

(Output Connected to 1 kΩ Network) 1 kΩ Output impedance tolerance ±400 Ω
(Output Connected to 100 kΩ Network) 100 kΩ Output impedance tolerance ±20 kΩ

Capacitive Load Stability 1 nF Loads used: RL = 5 kΩ, RL = 100 kΩ, RL = ∞
Output Slew Rate 1.2 V/s

Short-Circuit Current 60 mA

45 mA

DAC Power-Up Time

DC Power Supply Rejection Ratio −92 dB VDD ±10%, DAC code = full-scale
Wideband Spurious-Free Dynamic Range −67 dB Output frequency = 10 kHz

REFERENCE INPUT/OUTPUT

V

Input Range4 2 V

REF

Input Current (Power-Down) ±0.1 µA Zero-scale loaded
Input Current (Normal) ±0.5 µA
DC Input Impedance 1 MΩ

= 4.096 V, RL = unloaded, CL= unloaded, T

REF

MIN

to T

, unless otherwise specified.

MAX

V

REF

nV/√Hz

− 50 mV

DD

Guaranteed monotonic, −40°C to +125°C,
Y grade

All 1s loaded to DAC register,
TA = −40°C to +85°C, B grade

All 1s loaded to DAC register,

= −40°C to +125°C , Y grade

T

A

¼ scale to ¾ scale code transition to ±1LSB,

= 5 KΩ

R

L

DAC code = midscale, 1 kHz

¼ scale to ¾ scale code transition to ±1 LSB,
R

= 5 kΩ, CL = 200 pF

L

DAC code = full-scale, output shorted to GND,

= 25°C

T

A

DAC code = zero-scale, output shorted to V

= 25°C

T

A

Time to exit power-down mode to normal
mode of AD5061, 24

th

clock edge to 90% of

DD

DAC final value, output unloaded

,

Rev. B | Page 3 of 20

AD5061

B Grade1
Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

Input Current5 ±1 ±5 μA
Input Low Voltage (VIL) 0.8 V VDD = 4.5 V to 5.5 V

0.8 VDD = 2.7 V to 3.6 V
Input High Voltage (VIH) 2.0 V VDD = 2.7 V to 5.5 V

1.8 VDD = 2.7 V to 3.6 V
Pin Capacitance 4 pF

POWER REQUIREMENTS

VDD 2.7 5.5 V All digital inputs at 0 V or VDD
IDD (Normal Mode) DAC active and excluding load current
VDD = 2.7 V to 5.5 V 1.0 1.2 mA

0.89

IDD (All Power-Down Modes)

VDD = 2.5 V to 5.5 V 1 μA

0.265

1

Temperature range for B grade: −40°C to +85°C, typical at 25°C; temperature range for Y grade: −40°C to +125°C.

2

Linearity calculated using a reduced code range (160 to 65535).

3

Guaranteed by design and characterization, not production tested.

4

The typical output supply headroom performance for various reference voltages at −40°C can be seen in Figure 27.

5

Total current flowing into all pins.

= VDD and VIL = GND, VDD = 5.5 V,

V

IN

V

= 4.096 V, code = midscale

REF

= VDD and VIL = GND, VDD = 3.0 V,

V

IN

= 4.096 V, code = midscale

V

REF

= VDD and VIL = GND, VDD = 5.5 V,

V

IH

= 4.096 V, code = midscale

V

REF

= VDD and VIL = GND, VDD = 3.0 V,

V

IH

V

= 4.096 V, code = midscale

REF

Rev. B | Page 4 of 20

AD5061

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V, all specifications T

Table 3.

Parameter Limit1 Unit Test Conditions/Comments

2

t

33 ns min SCLK cycle time

1

t2
t

3

t

4

t5
t

6

t

7

t8
t9

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 30 MHz.

5 ns min
3 ns min
10 ns min
3 ns min
2 ns min
0 ns min
12 ns min
9 ns min

SCLK

SYNC

DIN

t

8

MIN

to T

unless otherwise specified.

MAX

,

SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore

t

4

t

t

2

1

t

3

t

6

t

5

t

9

t

7

D0D1D2D22D23

D23 D22

04762-002

Figure 2. Timing Diagram

Rev. B | Page 5 of 20

AD5061

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Operating Temperature Range

Industrial (B Grade) −40°C to + 85°C
Extended Automotive Temperature

Range (Y Grade) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
SOT-23 Package

Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance 206°C/W
θJC Thermal Impedance 44°C/W

Reflow Soldering (Pb-Free)

Peak Temperature 260°C
Time-at-Peak Temperature 10 sec to 40 sec

ESD 1.5 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance integrated circuit with an
ESD rating of <2 kV, and is ESD-sensitive. Proper precautions
should be taken for handling and assembly.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 6 of 20

AD5061

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

18

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.
2
3 V
4 V
5 AGND
6 DACGND
7

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and VDD should be decoupled to GND.

V

DD

Reference Voltage Input.

REF

Analog Output Voltage from DAC.

OUT

Ground Reference Point for Analog Circuitry.

Ground Input to the DAC.

SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.

The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the

rising edge of SYNC
8 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz.

DIN

V

V

REF

OUT

AD5061

27

TOP VIEW

DD

(Not to Scale)

36

45

Figure 3. Pin Configuration

acts as an interrupt and the write sequence is ignored by the DAC.

SCLK

SYNC

DACGND

AGND

04762-003

Rev. B | Page 7 of 20

AD5061

TYPICAL PERFORMANCE CHARACTERISTICS

1.6
TA = 25°C

1.4

= 5V, V

V

DD

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

INL ERRO R (LSB)

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

160

= 4.096V

REF

DAC CODE

Figure 4. Typical INL Plot

601605016040160301602016010160

04762-004

1.2
VDD = 5.5V, V

1.0

= 2.7V, V

V

DD

0.8

0.6

MAX DNL ERROR @ V

0.4

0.2

0

–0.2

–0.4

DNL ERROR (LSB)

–0.6

–0.8

MIN DNL ERROR @ VDD = 5.5V

–1.0

–1.2

–40 –20 0 20 40 60 80 100 120

= 4.096V

REF

= 2.0V

REF

= 2.7V

DD

MAX DNL E RROR @ VDD = 5.5V

MIN DNL ERROR @ VDD = 2.7V

TEMPERATURE (°C)

Figure 7. DNL vs. Temperature

04762-007

140

TUE ERROR (mV)

DNL ERROR (LSB)

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

–0.14

–0.16

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

TA = 25°C
V

0

160

TA = 25°C
V

0

160

DD

DD

= 5V, V

REF

= 4.096V

Figure 5. Typical TUE Plot

= 5V, V

REF

= 4.096V

Figure 6. Typical DNL Plot

DAC CODE

DAC CODE

1.2
VDD = 5.5V, V

1.0

= 2.7V, V

V

DD

0.8

0.6

0.4

0.2

MIN TUE ERROR @ VDD = 5.5V

0

–0.2

TUE ERROR (mV)

–0.4

–0.6

–0.8

–1.0

601605016040160301602016010160

04762-005

–1.2

–40 –20 0 20 40 60 80 100 120

= 4.096V

REF

= 2.0V

REF

MAX TUE ERROR @ V

MIN TUE ERROR @ VDD = 2.7V

TEMPERATURE (°C)

= 2.7V

DD

MAX TUE ERROR @ VDD = 5.5V

04762-008

140

Figure 8. TUE vs. Temperature

1.6
VDD = 5.5V, V

1.4

= 2.7V, V

V

DD

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

INL ERRO R (LSB)

–0.6

–0.8

–1.0

–1.2

601605016040160301602016010160

04762-006

–1.4

–1.6

MIN INL ERROR @ VDD = 5.5V

–40 –20 0 20 40 60 80 100 120

= 4.096V

REF

= 2.0V

REF

MAX INL ERROR @ V

MAX INL ERROR @ VDD = 5.5V

MIN INL ERROR @ VDD = 2.7V

TEMPERATURE (°C)

DD

= 2.7V

04762-090

140

Figure 9. INL vs. Temperature

Rev. B | Page 8 of 20

AD5061

1.6
TA = 25°C

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

DNL ERROR (LSB)

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

2.0

MAX DNL E RROR @ VDD = 5.5V

MIN DNL E RROR @ VDD = 5.5V

REFERENCE VO LTAGE (V)

04762-010

5.55.04.54.03.53.02.5

Figure 10. DNL vs. Reference Input Voltage

1.5
VDD = 5.5V, V

1.4
V

1.3
CODE = FULL -SCALE

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

SUPPLY CURRENT (mA)

0.4

0.3

0.2

0.1

0
–40

= 2.7V, V

DD

= 2.0V

REF

TEMPERATURE (°C)

VDD = 5.5V

= 2.7V

V

DD

= 4.096V

REF

Figure 13. Supply Current vs. Temperature

04762-013

140120100806040200–20

1.2
TA = 25°C

1.0

0.8

0.6

0.4

0.2

0

–0.2

TUE ERROR (mV)

–0.4

–0.6

–0.8

–1.0

–1.2

2.0

MAX TUE ERROR @ VDD = 5.5V

MIN TUE ERROR @ VDD = 5.5V

REFERENCE VO LTAGE (V)

04762-011

5.55.04.54.03.53.02.5

Figure 11. TUE vs. Reference Input Voltage

1.6
TA = 25°C

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

INL ERRO R (LSB)

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

2.0

MAX INL ERROR @ VDD = 5.5V

MIN INL E RROR @ VDD = 5.5V

REFERENCE VO LTAGE (V)

04762-009

5.55.04.54.03.53.02.5

Figure 12. INL vs. Reference Input Voltage

3.00
TA = 25°C

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

SUPPLY CURRENT (mA)

0.75

0.50

0.25

0

0

VDD = 5.5V, V

VDD = 3.0V, V

DAC CODE

Figure 14. Supply Current vs. Digital Input Code

2.0
V

= 2.5V

REF

1.8

= 25°C

T

A

CODE = MIDSCALE

1.6

1.4

1.2

1.0

0.8

0.6

SUPPLY CURRENT (mA)

0.4

0.2

0

2.5

SUPPLY VOLTAGE (V)

Figure 15. Supply Current vs. Supply Voltage

REF

REF

= 4.096V

= 2.5V

04762-014

70000600005000040000300002000010000

04762-015

6.05.55.04.54.03.53.0

Rev. B | Page 9 of 20

AD5061

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

OFFSET ERROR (mV)

0

–0.2

–0.4

–0.6

–40

VDD = 5.5V, V

= 2.7V, V

V

DD

OFFSET ERROR @ VDD = 5.5V

= 4.096V

REF

= 2.0V

REF

OFFSET ERROR @ V

TEMPERATURE (°C)

Figure 16. Offset vs. Temperature

DD

= 2.7V

CH3 = SCLK

CH2 = V

OUT

CH1 = TRIGG ER

04762-012

140120100806040200–20

CH2 2V/DIVCH1 2V/DIV TIME BASE = 5.00µsCH3 2V

04762-019

Figure 19. Exiting Power-Down Time to Midscale

24TH CLOCK FALLI NG

CH1 = SCLK

CH2 = V

OUT

CH2 50mV/DIV CH1 2V/DIV TIME BASE 400ns/ DIV

Figure 17. Digital-to-Analog Glitch Impulse; See Figure 21

300

VDD = 5V
T

= 25°C

A

V

= 4.096V

REF

250

200

150

FULL-SCALE

100

50

NOISE SPECT RAL DENSITY (n V/ Hz)

MIDSCALE

ZERO-SCALE

VDD = 3V
DAC = FULL-SCALE
V

= 2.7V

REF

T

= 25°C

A

Y AXIS = 2µV/DIV

04762-017

X AXIS = 4s/DIV

04762-020

Figure 20. 0.1 Hz to 10 Hz Noise Plot

VDD = 5V

V

= 4.096V

REF

T

= 25°C

A

10ns/SAMPL E

AMPLITUDE (200µV/DIV )

0

100

1000 10000 100000 1000000

FREQUENCY ( Hz)

Figure 18. Output Noise Spectral Density

04762-018

Rev. B | Page 10 of 20

50 100 150 200 250 300 350 400 450 5000

SAMPLES

04762-021

Figure 21. Glitch Energy

AD5061

0.10

GAIN ERROR (%F SR)

–0.02

–0.04

–0.06

–0.08

–0.10

0.08

0.06

0.04

0.02

0

–40 –20

VDD = 5.5V, V
V

= 2.7V, V

DD

= 4.096V

REF

= 2.0V

REF

GAIN ERROR @ V

TEMPERATURE (°C)

= 2.7V

DD

GAIN ERROR @ V

Figure 22. Gain Error vs. Temperature

DD

= 5.5V

CH1 = V

DD

CH2 = V

OUT

VDD = 5V V
RAMP RATE = 200µs
T

= 25°C

04762-022

140120100806040200

A

CH1 2V/DIV CH2 1V/DIV TIME BASE = 100µs

REF

= 4.096V

DD

04762-025

Figure 25. Hardware Power-Down Glitch

16

14

12

10

8

FREQUENCY

6

4

2

0

0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0 .91

Figure 23. I

14

12

10

8

6

FREQUENCY

4

2

0

1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11

Figure 24. I

BIN

Histogram @ VDD = 3 V

DD

BIN

Histogram @ VDD = 5 V

DD

MORE

MORE

CH1 = SCLK

CH2 = SYNC

CH3 = V

OUT

VDD = 5V V
TA = 25°C

04762-023

CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV
TIME BASE 1µs/ DIV

REF

= 4.096V

DD

CH4 = TRIG GER

04762-026

Figure 26. Exiting Software Power-Down Glitch

0.50

0.45

0.40

0.35

0.30

0.25

0.20

HEADROOM (V)

0.15

0.10

0.05

04762-024

0

2.72.93.13.33.53.73.94.14.34.54.74.95.1

Figure 27. V

REFERENCE VO LTAGE (V)

Headroom vs. Reference Voltage.

DD

04762-091

5.55.3

Rev. B | Page 11 of 20

AD5061

5.05

5.00

4.95

4.90

4.85

4.80

4.75

DAC OUTPUT (V)

4.70

4.65

4.60

4.55

Figure 28. Typical Output Voltage vs. Reference Voltage

5.005

5.000

VDD = 5.0V

= 25°C

T

A

DAC = FULL-SCAL E

4.70 4. 72 4.74 4.76 4. 78 4.80 4.82 4. 84 4.86 4.88 4.90 4. 92 4.94 4.96 4.98 5. 00

V

(V)

REF

V

= 5V

REF

T

= 25°C

A

1kΩ TO GND ZERO-SCALE

04762-042

CH4 20.0mV M1.00µs CH1 1.64V

C4 = 50mV p-p

04762-048

Figure 31. Typical Glitch upon Exiting Software Power-Down to Zero-Scale

C2
25mV p-p

4.995

4.990

DAC OUTPUT (V)

4.985

4.980

4.975

5.50 5.005.055.105.155.205.255.305.355.405. 45

VDD (V)

04762-065

Figure 29. Typical Output Voltage vs. Supply Voltage

C4 = 143mV p-p

1kΩ TO GNDZERO-SCALE

CH4 50.0mV M4.00µs CH1 1.64V

04762-047

Figure 30. Typical Glitch upon Entering Software Power-Down to Zero-Scale

2

3

CH3 2.00V CH2 50mV M1.00ms CH3 1.36V

T

T

C3

4.96V p-p

C3 FALL

935.0µs

C3 RISE
∞s
NO VALID
EDGE

04762-049

Figure 32. Typical Glitch upon Exiting Hardware Power-Down to Three State

C2
30mV p-p

2

3

CH3 2.00V CH2 50mV M1.00ms CH3 1.36V

T

T

C3

4.96V p-p

C3 FALL
∞s
NO VALID
EDGE

C3 RISE

946.2µs

04762-050

Figure 33. Typical Glitch upon Entering Hardware Power-Down to Zero-Scale

Rev. B | Page 12 of 20

AD5061

0.0010
CODE = MIDSCAL E

= 5V, V

V

0.0008

DD

= 3V, V

V

DD

0.0006

0.0004

0.0002

0

∆ VOLTAGE (V)

–0.0002

VDD = 5.5V

–0.0004

–0.0006

–0.0008

–25 –20 –15 –10 –5 0 5 10 15 20 25 30

= 4.096V

REF

= 2.5V

REF

VDD = 3V

CURRENT (mA)

Figure 34. Typical Output Load Regulation

04762-051

2.1

VDD = 5.5V
V

= 4.096V

2.0

REF

10% TO 90% RISE TIME = 0.688µs
SLEW RATE = 1.16 V/µs

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0
–10µs 9.96µs8µs6µs4µs2µs0–2µs–4µs–6µ s–8µs

Figure 36. Typical Output Slew Rate

DAC

OUTPUT

1.04V

2.04V

04762-052

0.10
CODE = MIDSCAL E

= 5V, V

V

0.08

DD

= 3V, V

V

DD

0.06

0.04

0.02

(V)

0

OUT

∆ V

–0.02

–0.04

–0.06

–0.08

–0.10

–25 –20 –15 –10 –5 0 5 10 15 20 25 30

= 4.096V

REF

= 2.5V

REF

VDD = 5V, V

REF

= 4.096V

I

OUT

VDD = 3V, V

(mA)

REF

= 2.5V

04762-063

Figure 35. Typical Current Limiting Plot

Rev. B | Page 13 of 20

AD5061

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 4.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design. A
typical AD5061 DNL vs. code plot is shown in Figure 6.

Zero-Code Error

Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5061 because the output of the DAC cannot go below 0 V.
This is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in mV.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be V
of full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.

− 1 LSB. Full-scale error is expressed in percent

DD

Tot a l Un a dj us t ed Er ro r (T UE )

Total unadjusted error is a measure of the output error taking
all the various errors into account. A typical TUE vs. code plot
is shown in Figure 5.

Zero-Code Error Drift

This is a measure of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition; see Figure 17 and Figure 21.
The expanded view in Figure 17 shows the glitch generated
following completion of the calibration routine; Figure 21
zooms in on this glitch.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus; that is, from all 0s to all 1s, and vice versa.

Rev. B | Page 14 of 20

AD5061

V

THEORY OF OPERATION

The AD5061 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of 2.7 V to 5.5 V. Data is writ­ten to the AD5061 in a 24-bit word format, via a 3-wire serial
interface.

The AD5061 incorporates a power-on reset circuit that ensures
the DAC output powers up to zero-scale or midscale. The
device also has a software power-down mode pin that reduces
the typical current consumption to less than 1 μA.

DAC ARCHITECTURE

The DAC architecture of the AD5061 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 37. The four MSBs of the 16-bit data word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either DACGND or V

output.

The remaining 12 bits of the data word drive switches

buffer

REF

S0 to S11 of a 12-bit voltage mode R-2R ladder network.

OUT

2R

2R

2R

2R

S1

S0

V

REF

12-BIT R-2R L ADDER FOUR MSBs DECODED INTO

Figure 37. DAC Ladder Structure

2R

2R

E1

S11

15 EQUAL SEGMENTS

E2

2R

E15

REFERENCE BUFFER

The AD5061 operates with an external reference. The reference
input (V

) has an input range of 2 V to VDD − 50 mV. This

REF

input voltage is then used to provide a buffered reference for the
DAC core.

SERIAL INTERFACE

The AD5061 has a 3-wire serial interface (
DIN), which is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See for a
timing diagram of a typical write sequence.

SYNC

, SCLK, and

Figure 2

DB15 (MSB) DB0 (LSB)

The write sequence begins by bringing the
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making these parts compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in the DAC register contents and/or a change in the mode of
operation).

At this stage, the

SYNC

line may be kept low or be brought
high. In either case, it must be brought high for a minimum of
12 ns before the next write sequence so that a falling edge of
SYNC

can initiate the next write sequence. Because the
buffer draws more current when V
V

= 0.8 V,

IH

should be idled low between write sequences

SYNC

IH

for an even lower power operation of the part. As previously
indicated, however, it must be brought high again just before
the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide; see Figure 38. PD1 and
PD0 are control bits that control which mode of operation the
part is in (normal mode or any one of three power-down
modes). There is a more complete description of the various

047762-027

modes in the Power-Down Modes section. The next 16 bits are
the data bits. These are transferred to the DAC register on the
24th falling edge of SCLK.

SYNC INTERRUPT

In a normal write sequence, the
least 24 falling edges of SCLK and the DAC is updated on the

24th falling edge. However, if
24th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs; see . Figure 41

SYNC

SYNC

SYNC

line low. Data

SYNC

= 1.8 V than it does when

line is kept low for at

is brought high before the

0000 00PD1PD0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

0
0

1

1

NORMAL O PERATION

0

3-STATE

1

100kΩ TO GND

0

1

1kΩ TO GND

Figure 38. Input Register Contents

Rev. B | Page 15 of 20

POWER-DOW N MODES

04762-028

AD5061

POWER-ON TO ZERO-SCALE OR MIDSCALE

The AD5061 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
the zero-scale or midscale code and the output voltage is zero­scale or midscale. It remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up.

SOFTWARE RESET

The device can be put into software reset by setting all bits in
the DAC register to 1; this includes writing 1s to Bit D23 to
Bit D16, which is not the normal mode of operation. Note that
the

interrupt command cannot be performed if a

SYNC

software reset command is started.

POWER-DOWN MODES

The AD5061 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 6 shows how the state
of the bits corresponds to the mode of operation of the device.

Table 6. Modes of Operation

DB17 DB16 Operating Mode

0 0 Normal operation
Power-down mode:
0 1 3-state
1 0 100 kΩ to GND
1 1 1 kΩ to GND

When both bits are set to 0, the part works normally with its
normal power consumption. However, for the three power­down modes, the supply current falls to less than 1 A at 5 V
(265 nA at 3 V). Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through a
1 kΩ resistor or a 100 kΩ resistor, or it is left open-circuited
(3-state). The output stage is illustrated in Figure 39.

OUTPUT

AD5061

DAC

Figure 39. Output Stage During Power-Down

BUFFER

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

V

OUT

04762-029

The bias generator, the DAC core and other associated linear
circuitry are all shut down when the power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 2.5 µs for V

= 5 V, and 5 µs for VDD = 3 V;

DD

see Figure 19.

MICROPROCESSOR INTERFACING

AD5061-to-ADSP-2101/ADSP-2103 Interface

Figure 40 shows a serial interface between the AD5061 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.

ADSP-2101/
ADSP-2103

1

ADDITIONAL PINS OMIT TED FOR CLARI TY

1

TFS

DT

SCLK

Figure 40. AD5061-to-ADSP-2101/ADSP-2103 Interface

AD5061

SYNC
DIN
SCLK

04762-030

SCLK

SYNC

DIN

DB23 DB23 DB0DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEF ORE 24

TH

FALLING EDGE

Figure 41.

SYNC

Rev. B | Page 16 of 20

VALID WRITE SEQUENCE, OUTP UT UPDATES

Interrupt Facility

ON THE 24THFALLING EDGE

04762-031

AD5061

AD5061-to-68HC11/68L11 Interface

Figure 42 shows a serial interface between the AD5061 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK pin of the AD5061, while the MOSI output
drives the serial data line of the DAC. The

SYNC

signal is
derived from a port line (PC7). The set-up conditions for
correct operation of this interface require that the 68HC11/
68L11 be configured so that its CPOL bit is 0 and its CPHA bit
is 1. When data is being transmitted to the DAC, the

SYNC

line
is taken low (PC7). When the 68HC11/68L11 is configured
where its CPOL bit is 0 and its CPHA bit is 1, data appearing on
the MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5061, PC7 is left
low after the first eight bits are transferred, a second serial write
operation is performed to the DAC, and PC7 is taken high at
the end of this procedure.

AD5061-to-80C51/80L51 Interface

Figure 44 shows a serial interface between the AD5061 and the
80C51/80L51 microcontroller. The setup for the interface is:
TxD of the 80C51/80L51 drives SCLK of the AD5061 while
RxD drives the serial data line of the part. The

SYNC

signal is
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to
the AD5061, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 out­puts the serial data in a format that has the LSB first. The
AD5061 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine should take this into account.

80C51/80L51

1

AD5061

1

68HC11/

1

68L11

PC7

SCK

MOSI

1

ADDITIONAL PI NS OMITTED FOR CLARI TY

SYNC

SCLK

DIN

AD5061

1

Figure 42. AD5061-to-68HC11/68L11 Interface

AD5061-to-Blackfin® ADSP-BF53x Interface

Figure 43 shows a serial interface between the AD5061 and the
Blackfin ADSP-53x microprocessor. The ADSP-BF53x proces­sor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5061,
the setup for the interface is: DT0PRI drives the DIN pin of
the AD5061, while TSCLK0 drives the SCLK of the part; the
SYNC

is driven from TFS0.

ADSP-BF53x

1

ADDITIONAL PI NS OMITTED FOR CLARI TY

1

DT0PRI

TSCLK0

TFS0

Figure 43. AD5061-to-Blackfin ADSP-BF53x Interface

DIN

SCLK

SYNC

AD5061

1

P3.3

TxD

RxD

1

ADDITIONAL PI NS OMITTED FOR CLARI TY

04762-032

AD5061-to-MICROWIRE Interface

Figure 44. AD5061-to-80C51/80L51 Interface

SYNC

SCLK

DIN

04762-034

Figure 45 shows an interface between the AD5061 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5061 on the rising edge of the SK.

MICROWIRE

1

ADDITIONAL PI NS OMITTED FOR CLARI TY

1

CS

SK

SO

Figure 45. AD5061-to-MICROWIRE Interface

AD5061

SYNC

SCLK

DIN

1

04762-035

04762-033

Rev. B | Page 17 of 20

AD5061

Ω

APPLICATIONS

CHOOSING A REFERENCE

To achieve the optimum performance from the AD5061,
thought should be given to the choice of a precision voltage
reference. The AD5061 has just one reference input, V
voltage on the reference input is used to supply the positive
input to the DAC. Therefore, any error in the reference is
reflected in the DAC.

There are four possible sources of error when choosing a vol­tage reference for high accuracy applications: initial accuracy,
ppm drift, long-term drift, and output voltage noise. Initial
accuracy on the output voltage of the DAC leads to a full-scale
error in the DAC. To minimize these errors, a reference with
high initial accuracy is preferred. Also, choosing a reference
with an output trim adjustment, such as the ADR43x family,
allows a system designer to trim out system errors by setting a
reference voltage to a voltage other than the nominal. The trim
adjustment can also be used at the operating temperature to
trim out any errors.

REF

. The

Table 7 shows examples of recommended precision references
for use as a supply to the AD5061.

Table 7. Precision References Part List for the AD5061

Part No.

Initial
Accuracy
(mV max)

Temperature Drift
(ppm/°C max)

0.1 Hz to
10 Hz Noise
(μV p-p typ)

ADR435 ±2 3 (SO-8) 8
ADR425 ±2 3 (SO-8) 3.4
ADR02 ±3 3 (SO-8) 10
ADR02 ±3 3 (SC70) 10
ADR395 ±5 9 (TSOT-23) 8

BIPOLAR OPERATION

The AD5061 has been designed for single-supply operation, but
a bipolar output range is also possible using the circuit shown in
Figure 47. The circuit shown yields an output voltage range of
±5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD8675/AD820/AD8032 or an OP196/OP295.

Because the supply current required by the AD5061 is
extremely low, the parts are ideal for low supply applications.
The ADR395 voltage reference is recommended. This requires
less than 100 μA of quiescent current and can, therefore, drive
multiple DACs in one system, if required. It also provides very
good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range.

7V

5V

AD5061

V

OUT

= 0V TO 5V

3-WIRE

SERIAL

INTERFACE

ADR395

SYNC

SCLK

DIN

Figure 46. ADR395 as Reference to the AD5061

Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification
ensures that the overall solution remains relatively stable during
its entire lifetime. The temperature coefficient of a reference’s
output voltage affects INL, DNL, and TUE. A reference with a
tight temperature coefficient specification should be chosen to
reduce temperature dependence of the DAC output voltage on
ambient conditions.

In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references, such as the ADR435, produce low
output noise in the 0.1 Hz to 10 Hz region.

The output voltage for any input code can be calculated as
follows:

+

⎡

⎛

×=

VV

O

⎜

⎢

⎝

⎣

65536

⎞

×

⎟
⎠

2R1RD

⎛
⎜
⎝

⎞

V

⎟

1R

⎠

2R

⎤

⎞

⎛

×−

DDDD

⎟

⎜

⎥

1R

⎠

⎝

⎦

where D represents the input code in decimal (0 to 65536).

With V

= 5 V, R1 = R2 = 10 kΩ,

REF

10

×=D

65536

⎞

−

⎟
⎠

⎛

V

⎜

O

⎝

V5

This is an output voltage range of ±5 V with 0x0000 correspond­ing to a −5 V output and 0xFFFF corresponding to a +5 V output.

04762-036

+5V

10µF

0.1µF

Figure 47. Bipolar Operation with the AD5061

R1 = 10kΩ

V

REF

AD5061

3-WIRE

SERIAL

INTERFACE

V

BF

V

OUT

R2 = 10k

–
AD820/
OP295

+

+5V

–5V

±5V

04762-037

Rev. B | Page 18 of 20

AD5061

USING A GALVANICALLY-ISOLATED INTERFACE CHIP

In process control applications in industrial environments, it is
often necessary to use a galvanically-isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that may occur in the area where the

DAC is functioning. iCoupler

2.5 kV. Because the AD5061 uses a 3-wire serial logic interface,
the ADuM130x family provides an ideal digital solution for the
DAC interface.

The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates.
They operate across the full range from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems and enabling a voltage
translation functionality across the isolation barrier.

Figure 48 shows a typical galvanically-isolated configuration
using the AD5061. The power supply to the part also needs to
be isolated; this is accomplished by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5061.

POWER

ADuM130x

® provides isolation in excess of

5V

REGULATOR

SCLKV0AV1ASCLK

SYNCV0BV1BSDI

V

DD

AD5061

V

OUT

0.1µF10µ F

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5061 should
have separate analog and digital sections, each having its own
area of the board. If the AD5061 is in a system where other
devices require an AGND-to-DGND connection, then the
connection should be made at one point only. This ground
point should be as close as possible to the AD5061.

The power supply to the AD5061 should be bypassed with
10 μF and 0.1 μF capacitors. The capacitors should be physically
as close as possible to the device with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and effective series
inductance (ESI), as do common ceramic types of capacitors.
This 0.1 μF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents due to internal
logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.

DINV0CV1CDATA

GND

Figure 48. AD5061 with a Galvanically-Isolated Interface

04762-038

Rev. B | Page 19 of 20

AD5061

0

0

OUTLINE DIMENSIONS

INDICATOR

.15 MAX
.05 MIN

1.70

1.60

1.50

1.30

1.15

0.90

PIN 1

3.00

2.90

2.80

76

8

1234

1.95
BSC

5

0.38 MAX

0.22 MIN

0.65 BSC

1.45 MAX

0.95 MIN

3.00

2.80

2.60

SEATING
PLANE

0.22 MAX

0.08 MIN

8°

0.60

4°

BSC

0°

0.60

0.45

0.30

COMPLIANT TO JEDEC STANDARDS MO-178-BA

12-16-2008-A

Figure 49. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model1

AD5061BRJZ-1REEL7

Range INL Description

−40°C to +85°C 4 LSB 2.7 V to 5.5 V, Reset to 0 V 8-Lead SOT-23 RJ-8 D43
AD5061BRJZ-1500RL7 −40°C to +85°C 4 LSB 2.7 V to 5.5 V, Reset to 0 V 8-Lead SOT-23 RJ-8 D43
AD5061BRJZ-2REEL7

−40°C to +85°C 4 LSB 2.7 V to 5.5 V, Reset to Midscale 8-Lead SOT-23 RJ-8 D44
AD5061BRJZ-2500RL7 −40°C to +85°C 4 LSB 2.7 V to 5.5 V, Reset to Midscale 8-Lead SOT-23 RJ-8 D44
AD5061YRJZ-1500RL7 −40°C to +125°C 4 LSB 2.7 V to 5.5 V, Reset to 0 V 8-Lead SOT-23 RJ-8 D6G
AD5061YRJZ-1REEL7 −40°C to +125°C 4 LSB 2.7 V to 5.5 V, Reset to 0 V 8-Lead SOT-23 RJ-8 D6G
EVAL-AD5061EBZ

1

Z = RoHS Compliant Part.

Evaluation Board

Package
Description

Package
Option Branding

©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04762-0-5/11(B)

Rev. B | Page 20 of 20