Fully Accurate, 12-/14-/16-Bit, Dual, V
V
V
V
A
nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
OUT
FEATURES
Low power dual 12-/14-/16-bit DAC, ±1 LSB INL
Individual voltage reference pins
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
Power down to 400 nA @ 5 V
3 power-down functions
Per channel power-down
Low glitch upon power-up
Hardware power-down lockout capability
Hardware
function to programmable code
CLR
SDO daisy-chaining option
14-lead TSSOP
APPLICATIONS
Process controls
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit
buffered voltage output nanoDAC® DACs offering relative accuracy
specifications of ±1 LSB INL with individual reference pins, and
can operate from a single 4.5 V to 5.5 V supply. The AD5025/
AD5045/AD5065 also offer a differential accuracy specification of
±1 LSB. The parts use a versatile 3-wire, low power Schmitt
trigger serial interface that operates at clock rates up to 50 MHz
and is compatible with standard SPI®, QSPI™, MICROWIRE™,
and DSP interface standards. The reference for the AD5025/
AD5045/AD5065 are supplied from an external pin and a refer-
with software
LDAC
override function
LDAC
POR
FUNCTIONAL BLOCK DIAGRAM
AD5025/AD5045/AD5065
ence buffer is provided on chip. The AD5025/AD5045/AD5065
incorporate a power-on reset circuit that ensures the DAC output
powers up zero scale or midscale and remains there until a valid
write takes place to the device. The AD5025/AD5045/AD5065
contain a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides software
selectable output loads while in power-down mode. The parts are
put into power-down mode over the serial interface. Total unadjusted error for the parts is <2.5 mV. The parts exhibit very low
glitch on power-up. The outputs of all DACs can be updated
simultaneously using the
functionality of user-selectable DAC channels to simultaneously
update. There is also an asynchronous
to a software-selectable code—0 V, midscale, or full scale. The
parts also feature a power-down lockout pin,
used to prevent the DAC from entering power-down under any
circumstances over the serial interface.
PRODUCT HIGHLIGHTS
1. Dual channel available in a 14-lead TSSOP package with
individual voltage reference pins.
2. 12-/14-/16-bit accurate, ±1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (zero scale or midscale).
7. Power-down lockout capability.
Table 1. Related Devices
Part No. Description
AD5666 Quad,16-bit buffered DAC, 16 LSB INL, TSSOP
AD5024/AD5044/AD5064 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
AD5062/AD5063 16-bit nanoDAC, 1 LSB INL, MSOP
AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23
AD5040/AD5060 14-/16-bit nanoDAC, 1 LSB INL, SOT-23
DD
REF
REF
B
LDAC
function, with the added
CLR
that clears all DACs
PDL
, which can be
LDAC
SCLK
SYNC
DIN
LDAC
SDO
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
INTERFACE
LOGIC
CLR
PDL
INPUT
REGISTER
INPUT
REGISTER
AD5025/AD5045/AD5065
DAC
REGISTER
DAC
REGISTER
Figure 1.
DAC A
DAC B
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
BUFFER
BUFFER
POWER-DOW N
LOGIC
GND
A
V
OUT
V
B
OUT
06844-001
AD5025/AD5045/AD5065
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 17
Digital-to-Analog Converter .................................................... 17
DAC Architecture ....................................................................... 17
Reference Buffer ......................................................................... 17
Output Amplifier ........................................................................ 17
Serial Interface ............................................................................ 17
Input Register .............................................................................. 17
Standalone Mode ........................................................................ 19
Interrupt .......................................................................... 19
SYNC
Daisy-Chaining ........................................................................... 19
Power-On Reset and Software Reset ....................................... 20
Power-Down Modes .................................................................. 20
Clear Code Register ................................................................... 21
Function ........................................................................... 21
LDAC
Power-Down Lockout ................................................................ 22
Power Supply Bypassing and Grounding ................................ 22
Microprocessor Interfacing ....................................................... 23
Applications Information .............................................................. 24
Using a Reference as a Power Supply for the
AD5025/AD5045/AD5065 ....................................................... 24
Bipolar Operation Using the AD5025/AD5045/AD5065 ..... 24
Using the AD5025/AD5045/AD5065 with a
Galvanically Isolated Interface ................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5025/AD5045/AD5065
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ V
T
, unless otherwise noted.
MAX
≤ VDD, unless otherwise specified. All specifications T
REFIN
MIN
to
Table 2.
1
A Grade
Parameter
STATIC PERFORMANCE
B Grade
Min Typ Max Min Typ Max
3
Resolution
AD5065 16 16 Bits
AD5045 14
AD5025 12
Relative Accuracy
AD5065 ±0.4 ±1 ±0.5 ±4 LSB TA = −40°C to +105°C
AD5065 +0.4 ±2 ±0.5 ±4 TA = −40°C to +125°C
AD5045 ±0.1 ±0.5 LSB TA = −40°C to +105°C
AD5045 ±0.1 ±1 TA = −40°C to +125°C
AD5025 ±0.05 ±0.25 LSB TA = −40°C to +105°C
AD5025 ±0.05 ±0.5 TA = −40°C to +125°C
Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB
Total Unadjusted Error ±0.2 ±2.5 ±0.2 ±2.5 mV V
Offset Error ±0.2 ±1.8 ±0.2 ±1.8 mV Code 512 (AD5065), Code 128 (AD5045),
Offset Error Drift4 ±2 ±2 µV/°C
Full-Scale Error ±0.01 ±0.07 ±0.01 ±0.07 % FSR
Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR
Gain Temperature Coefficient4 ±1 ±1 ppm Of FSR/°C
DC Crosstalk4 40 40 µV Due to single channel full-scale output
40 40 µV/mA Due to load current change
40 40 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS4
Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 1 1 nF RL = 5 kΩ, RL = 100 kΩ, and RL = ∞
DC Output Impedance
Normal Mode 0.5 0.5 Ω
Power-Down Mode
Output Connected to
100 100 kΩ Output impedance tolerance ± 400 Ω
100 kΩ Network
Output Connected to
1 1 kΩ Output impedance tolerance ± 20 Ω
1 kΩ Network
Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND
45 45 mA DAC = zero-scale, output shorted to VDD
Power-Up Time 4.5 4.5 µs Time to exit power-down mode to
DC PSRR −92 −92 dB VDD ± 10%, DAC = full scale, V
REFERENCE INPUTS
Reference Input Range 2.2 VDD 2.2 VDD V
Reference Current 35 50 35 50 µA Per DAC channel
Reference Input Impedance 120 120 kΩ
1, 2
Unit Conditions/Comments
= 2.5 V; VDD = 5.5 V
REF
Code 32 (AD5025) loaded to DAC register
All 1s loaded to DAC register, V
change, R
normal mode of AD5024/AD5044/
AD5064, 32
= 5 kΩ to GND or VDD
L
nd
clock edge to 90% of DAC
REF
< VDD
midscale value, output unloaded
<VDD
REF
Rev. 0 | Page 3 of 28
AD5025/AD5045/AD5065
Parameter
1
B Grade
A Grade
Min Typ Max Min Typ Max
1, 2
Unit Conditions/Comments
LOGIC INPUTS
Input Current5 ±1 ±1 µA
Input Low Voltage, V
Input High Voltage, V
0.8 0.8 V
INL
2.2 2.2 V
INH
Pin Capacitance4 4 4 pF
LOGIC OUTPUTS (SDO)
Output Low Voltage, VOL 0.4 0.4 V I
Output High Voltage, VOH V
High Impedance Leakage
Current
4
High Impedance Output
3, 4
= 2 mA
SINK
− 1 VDD − 1 I
DD
SOURCE
±0.002 ±1 ±0.002 ±1 A
7 7 pF
= 2 mA
Capacitance
POWER REQUIREMENTS
VDD 4.5 5.5 4.5 5.5 V
6
I
DAC active, excludes load current
DD
Normal Mode 2.2 2.7 2.2 2.7 mA VIH = VDD and VIL = GND
All Power-Down Modes7 0.4 2 0.4 2 µA TA = −40°C to +105°C
30 30 µA TA = −40°C to +125°C
1
Temperature range is −40°C to +125°C, typical at 25°C.
2
A grade offered in AD5065 only.
3
Linearity calculated using a reduced code range—AD5065: Code 512 to Code 65,024; AD5045: Code 128 to Code 16,256; AD5025: Code 32 to Code 4064. Output
unloaded.
4
Guaranteed by design and characterization; not production tested.
5
Current flowing into or out of individual digital pins.
6
Interface inactive. All DACs active. DAC outputs unloaded.
7
Both DACs powered down.
AC CHARACTERISTICS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ V
Table 3.
Parameter
1
Min Typ Max Unit Conditions/Comments2
Output Voltage Settling Time 5.8 8 µs
Output Voltage Settling Time 10.7 13 µs
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse3 4 nV-sec 1 LSB change around major carry
Reference Feedthrough3 −90 dB V
SDO Feedthrough 0.07 nV-sec Daisy-chain mode; SDO load is 10 pF
Digital Feedthrough3 0.1 nV-sec
Digital Crosstalk3 1.9 nV-sec
Analog Crosstalk3 1.2 nV-sec
DAC-to-DAC Crosstalk3 2.1 nV-sec
Multiplying Bandwidth3 340 kHz V
Total Harmonic Distortion3 −80 dB V
Output Noise Spectral Density 64 nV/√Hz DAC code = 0x8400, 1 kHz
60 nV/√Hz DAC code = 0x8400, 10 kHz
Output Noise 6 V p-p 0.1 Hz to 10 Hz
1
Guaranteed by design and characterization; not production tested.
2
Temperature range is −40°C to + 125°C, typical at 25°C.
3
See the Terminology section.
≤ VDD. All specifications T
REFIN
¼ to ¾ scale settling to ±1 LSB, R
to T
MIN
= 5 kΩ single-channel update
L
including DAC calibration sequence
¼ to ¾ scale settling to ±1 LSB, R
= 5 kΩ all channel update including
L
DAC calibration sequence
= 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz
REF
= 3 V ± 0.86 V p-p
REF
= 3 V ± 0.86 V p-p, frequency = 10 kHz
REF
, unless otherwise noted.
MAX
Rev. 0 | Page 4 of 28
AD5025/AD5045/AD5065
T
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. V
Table 4.
Parameter Symbol Min Typ Max Un it
SCLK Cycle Time t
SCLK High Time t2 10 ns
SCLK Low Time t3 10 ns
SYNC to SCLK Falling Edge Setup Time
Data Setup Time t5 5 ns
Data Hold Time t6 5 ns
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single Channel Update)
Minimum SYNC High Time (All Channel Update)
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
SCLK Rising Edge to SDO Valid t
SCLK Falling Edge to SYNC Rising Edge
SYNC Rising Edge to SCLK Rising Edge
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update)
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update)
PDL Minimum Pulse Width
1
Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2
Daisy-chain mode only.
3
Measured with the load circuit of Figure 2. t15 determines the maximum SCLK frequency in daisy-chain mode.
Circuit and Timing Diagrams
= 4.5 V to 5.5 V. All specifications T
DD
MIN
to T
, unless otherwise noted.
MAX
1
20 ns
1
t
16.5 ns
4
t
0 30 ns
7
t
2 µs
8
t
4 µs
8
t
17 ns
9
t
20 ns
10
t
20 ns
11
t
10 ns
12
t
10 ns
13
t
10.6 µs
14
2, 3
15
2
t
5 30 ns
16
2
t
8 ns
17
2
t
2 µs
18
2
t
4 µs
18
t
19
22 ns
20 ns
2mA I
OL
O OUTPUT
PIN
50pF
C
L
2mA I
OH
VOH (MIN) + VOL (MAX)
2
06844-002
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. 0 | Page 5 of 28
AD5025/AD5045/AD5065
SCLK
t
8
SYNC
DIN
1
LDAC
2
LDAC
CLR
V
OUT
PDL
1
ASYNCHRONOUS LDAC UPDAT E MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
DB31
t
4
t
6
t
5
t
12
t
14
t
1
t
t
3
2
DB0
t
9
t
7
t
10
t
13
t
11
t
19
06844-003
Figure 3. Serial Write Operation
SCLK
t8t
4
SYNC
t
5
t
6
DIN
INPUT WORD FOR DAC N
SDO
UNDEFINED
1
LDAC
CLR
PDL
1
IF IN DAIS Y-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY.
32 64
t
16
DB0DB31
DB31
INPUT WORD FOR DAC N + 1
t
15
DB31
INPUT WORD FOR DAC N
t
t
t
DB0
18
18
18
DB0
t
17
t
10
t
12
t
19
06844-004
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 6 of 28
AD5025/AD5045/AD5065
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V
A or V
OUT
V
A or V
REF
Operating Temperature Range, Industrial −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ
Power Dissipation (TJ
θJA Thermal Impedance 150.4°C/W
Reflow Soldering Peak Temperature
SnPb 240°C
Pb-Free 260°C
B to GND −0.3 V to VDD + 0.3 V
OUT
B to GND −0.3 V to VDD + 0.3 V
REF
) 150°C
MAX
− TA)/θJA
MAX
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 7 of 28
AD5025/AD5045/AD5065
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC
SYNC
V
REF
V
OUT
POR
SDO
V
DD
A
A
1
2
AD5025/
3
AD5045/
4
AD5065
TOP VIEW
5
(Not to Scale)
6
7
14
SCLK
13
DIN
12
PDL
11
GND
V
B
10
OUT
9
V
B
REF
8
CLR
06844-005
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
LDAC
allows all DAC outputs to simultaneously update. This pin can be tied permanently low in standalone
mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low. The LDAC
be used in asynchronous LDAC update mode, as shown in Figure 3, and the LDAC pin must be brought
high after pulsing. This allows all DAC outputs to simultaneously update.
2
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
SYNC
low, it powers on the SCLK and DIN buffers and enables the input register. Data is transferred in on the
3 VDD
falling edges of the next 32 clocks. If SYNC
SYNC
acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
is taken high before the 32nd falling edge, the rising edge of
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 V
5 V
6 POR
A DAC A Reference Input. This is the reference voltage input pin for DAC A.
REF
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
OUT
Power-On Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to V
the part to midscale.
7 SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading
back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising
edge of SCLK and is valid on the falling edge of the clock.
8
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
CLR
ignored. When CLR
is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
9 V
10 V
B DAC B Reference Input. This is the reference voltage input pin for DAC B.
REF
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
OUT
11 GND Ground Reference Point for All Circuitry on the Part.
12
The PDL pin is used to ensure hardware shutdown lockout of the device under any circumstance. A
PDL
Logic 1 at the PLO
pin causes the device to behave as normal. The user may successfully enter
software power-down over the serial interface while Logic 1 is applied to the PDL
If a Logic 0 is applied to this pin, it ensures that the device cannot enter software power-down under
any circumstances. If the device had previously been placed in software power-down mode, a high-to-
low transition at the PDL pin causes the DAC(s) to exit power-down and output a voltage corresponding to
the previous code in the DAC register before the device entered software power-down.
13 DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
14 SCLK
Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
pin.
pin should
powers up
DD
Rev. 0 | Page 8 of 28
AD5025/AD5045/AD5065
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
512 16,640 32,768 48,896 65,024
DAC CODE
Figure 6. AD5065 INL
06844-019
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
512 16,640 32,768 48,896 65,024
DAC CODE
Figure 9. AD5065 DNL
06844-022
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 153 6 2048 2560 3072 35 84 4096
DAC CODE
Figure 7. AD5045 INL
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 153 6 2048 2560 3072 35 84 4096
DAC CODE
Figure 8. AD5025 INL
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 4096 8192 12,288 16,384
06844-020
DAC CODE
06844-023
Figure 10. AD5045 DNL
1.00
0.75
0.50
0.25
0
DNL (LSB)
–0.25
–0.50
–0.75
–1.00
0 4096 8192 12,288 16,384
06844-021
DAC CODE
06844-024
Figure 11. AD5025 DNL
Rev. 0 | Page 9 of 28
AD5025/AD5045/AD5065
0.20
0.15
0.10
0.05
0
TUE (mV)
–0.05
–0.10
–0.15
–0.20
512 16,640 32,768 48,896 65,024
DAC CODE
Figure 12. Total Unadjusted Error (TUE) vs. DAC Code
06844-025
1.2
TA = 25°C
1.0
0.8
0.6
0.4
0.2
0
–0.2
TUE ERROR (mV)
–0.4
–0.6
–0.8
–1.0
–1.2
2.0
MAX TUE ERROR @ VDD = 5.5V
MIN TUE ERROR @ VDD = 5.5V
5.55. 04. 54.03.53.02.5
REFERENCE VO LTAGE (V)
Figure 15. Total Unadjusted Error (TUE) vs. Reference Input Voltage
06844-028
1.6
TA = 25°C
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
INL ERRO R (LSB)
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
2.0
MAX INL ERROR @ VDD = 5.5V
MIN INL ERROR @ VDD = 5.5V
REFERENCE VOLTAGE (V)
5.55. 04.54.03.53.02.5
06844-026
Figure 13. INL vs. Reference Input Voltage
1.6
TA = 25°C
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
DNL ERROR (LSB)
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
2.0
MAX DNL ERROR @ VDD = 5.5V
MIN DNL ERROR @ V
REFERENCE VOL TAGE (V)
DD
= 5.5V
5.55. 04.54.03. 53.02.5
06844-027
Figure 14. DNL vs. Reference Input Voltage
0.015
0.010
0.005
0
–0.005
GAIN ERROR (%F SR)
–0.010
–0.015
–60 –20 40 80 140
DAC A
DAC B
VDD= 5.5V
= 4.096V
V
REF
–40 0 20 60 100
TEMPERATURE ( °C)
Figure 16. Gain Error vs. Temperature
0.6
0.5
0.4
0.3
0.2
DAC B
0.1
0
–0.1
OFFSET ERROR (mV)
DAC A
–0.2
–0.3
–0.4
–60 0 40 80 140
–40 20–20 60 100 120
TEMPERATURE ( ºC)
VDD= 5.5V
V
Figure 17. Offset Error vs. Temperature
REF
120
= 4.096V
06844-029
6844-030
Rev. 0 | Page 10 of 28
AD5025/AD5045/AD5065
0.2
0.1
0
ERROR (%FSR)
–0.1
–0.2
4.50 4.75 5.00 5.25 5.50
GAIN ERROR
FULL-SCAL E ERROR
VDD (V)
Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage
0.12
0.09
06844-031
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
OUTPUT VOLTAGE (V)
1.0
0.5
0
02468101214
VDD = 5V, V
T
= 25ºC
A
1/4 SCALE TO 3/ 4 SCALE
3/4 SCALE TO 1/ 4 SCALE
OUTPUT L OADED WIT H 5kΩ
AND 200pF TO GND
TIME (µs)
REF
= 4.096V
Figure 21. Settling Time and Typical Output Slew Rate
POR
06844-038
0.06
OFFSET ERROR (mV)
0.03
0
4.50 4.75 5.00 5.25 5.50
VDD (V)
Figure 19. Offset Error Voltage vs. Supply Voltage
16
14
12
10
8
HITS
6
4
2
0
0 1.0 1.1 1.2 1.3 1.4 1.5
IDD POWER UP (mA)
Figure 20. IDD Histogram, VDD = 5.0 V
1
V
3
CH1 2V CH3 2V M2ms A CH1 2.52V
06844-032
OUT
T 20.4%
06844-039
Figure 22. Power-On Reset to 0 V
1
3
CH1 2V CH3 2V M2ms A CH1 2.52V
06844-064
T 20.4%
06844-040
Figure 23. Power-On Reset to Midscale
Rev. 0 | Page 11 of 28
AD5025/AD5045/AD5065
V
CH1 = SCLK
1
CH2 = V
OUT
2
CH1 5V CH2 500mV M2µs A CH2 1.2V
VDD = 5V
POWER-UP TO MIDSCALE
T 55%
Figure 24. Exiting Power-Down to Midscale
6
5
4
3
2
1
0
GLITCH AMPLITUDE (mV)
–1
–2
–3
0 2.5 5.0 7.5 10.0
TIME (μs)
Figure 25. Digital-to-Analog Glitch Impulse
6844-041
06844-042
7
6
5
4
3
2
1
0
–1
GLITCH AMP LITUDE (mV )
–2
–3
–4
0 2 .5 5.0 7.5 10.0
TIME (μs)
VDD = 5V, V
T
= 25°C
A
Figure 27. DAC-to-DAC Crosstalk
VDD = 5V, V
= 25ºC
T
A
DAC LOADED WITH MIDSCALE
1μV/DI
REF
= 4.096V
4s/DIV
Figure 28. 0.1 Hz to 10 Hz Output Noise Plot
REF
= 4.096V
06844-044
06844-045
7
VDD = 5V, V
6
= 25ºC
T
A
5
4
3
2
1
0
–1
GLITCH AMP LITUDE (mV )
–2
–3
–4
0 2.5 5.0 7.5 10.0
REF
= 4.096V
TIME (μs)
Figure 26. Analog Crosstalk
6844-043
0
–10
–20
–30
–40
–50
LEVEL (dB)
–60
OUT
V
–70
–80
–90
–100
5 10 30 40 55
20 50
VDD= 5V,
T
= 25ºC
A
DAC LOADED WITH MIDSCALE
V
= 3.0V ± 200mV p -p
REF
FREQUENCY (kHz)
Figure 29. Total Harmonic Distortion
06844-046
Rev. 0 | Page 12 of 28
AD5025/AD5045/AD5065
24
VDD = 5V, V
= 25°C
T
22
A
20
18
16
14
12
SETTLING TIME (μs)
10
8
6
4
01 5 7 10
= 3.0V
REF
3924
CAPACITANCE (nF )
6
Figure 30. Settling Time vs. Capacitive Load
CLR
CLR
V
OUT
1
2
CH1 5V CH2 2V M2µs A CH1 2.5V
T 11 %
Figure 31. Hardware
8
06844-047
6844-048
0.0010
CODE = MIDSCALE
V
= 5V, V
DD
0.0008
0.0006
0.0004
0.0002
0
ΔVOLTAGE (V)
–0.0002
VDD = 5.5V
–0.0004
–0.0006
–0.0008
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
REF
= 4.096V
CURRENT (mA)
Figure 33. Typical Output Load Regulation
0.10
CODE = MIDSCAL E
= 5V, V
V
0.08
DD
0.06
0.04
0.02
(V)
0
OUT
ΔV
–0.02
–0.04
–0.06
–0.08
–0.10
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
REF
= 4.096V
I
OUT
(mA)
Figure 34. Typical Current Limiting Plot
06844-051
06844-052
10
0
–10
–20
–30
ATTENUATION (dB)
–40
CH A
CH B
–50
CH C
CH D
3dB POINT
–60
10 100 1000 10 000
FREQUENCY (kHz)
Figure 32. Multiplying Bandwidth
06844-049
Figure 35. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
Rev. 0 | Page 13 of 28
V
OUT
SCLK
CH1 50mV CH2 5V M4µs A CH2 1.2V
T 8.6%
CH1 295mV p-p
No Load
06844-053
AD5025/AD5045/AD5065
V
OUT
SCLK
CH1 50mV CH2 5V M4µs A CH2 1.2V
T 8.6%
CH1 200mV p-p
06844-054
Figure 36. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
5 kΩ/200 pF Load
V
OUT
CH1 129mV p-p
V
OUT
SCLK
CH1 20mV CH2 5V M4µs A CH2 1.2V
T 8.6%
CH1 170mV p-p
6844-056
Figure 38. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,
5 kΩ/200 pF Load
1
PDL
2
VOUT
SCLK
CH1 20mV CH2 5V M4µs A CH2 1.2V
T 8.6%
06844-055
Figure 37. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No
Load
CH1 5.00V CH2 1V M1µs A CH1 2.5V
Figure 39.
PDL
Activation Time
06844-068
Rev. 0 | Page 14 of 28
AD5025/AD5045/AD5065
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer
function. Figure 6, Figure 7, and Figure 8 show plots of typical
INL vs. code.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 9, Figure 10, and Figure 11 show plots of
typical DNL vs. code.
Offset Error
Offset error is a measure of the difference between the actual
V
and the ideal V
OUT
, expressed in millivolts in the linear
OUT
region of the transfer function. Offset error is measured on the
part with Code 512 (AD5065), Code 128 (AD5045), and Code 32
(AD5025) loaded into the DAC register. It can be negative or
positive and is expressed in millivolts.
Offset Error Drift
Offset error drift is a measure of the change in offset error with
a change in temperature. It is expressed in microvolts per degree
Celsius.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Gain Temperature Coefficient
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in parts per million of
full-scale range per degree Celsius. Measured with V
< VDD.
REF
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be V
− 1 LSB. Full-scale error is expressed as a
DD
percentage of the full-scale range.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nanovoltseconds and is measured when the digital input code is changed
by 1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 25.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in decibels. V
Measured with V
for full-scale output of the DAC. It is measured
DD
is held at 2.5 V, and VDD is varied ±10%.
REF
< VDD.
REF
OUT
to
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is,
LDAC
is high). It is expressed in
decibels.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to
SYNC
(
held high). It is specified in nanovolt-seconds. It is
measured with one simultaneous data and clock pulse loaded
to the DAC.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nanovolt-seconds.
Rev. 0 | Page 15 of 28
AD5025/AD5045/AD5065
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping
LDAC
high, and then pulsing
the DAC whose digital code has not changed. The area of the
glitch is expressed in nanovolt-seconds.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nanovolt-seconds.
low and monitoring the output of
LDAC
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
Rev. 0 | Page 16 of 28
AD5025/AD5045/AD5065
V
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5025/AD5045/AD5065 are single 12-/14-/16-bit, serial
input, voltage output DACs. The parts operate from supply voltages
of 4.5 V to 5.5 V. Data is written to the AD5025/AD5045/AD5065
in a 32-bit word format via a 3-wire serial interface. The AD5025/
AD5045/AD5065 incorporate a power-on reset circuit that ensures
the DAC output powers up to a known output state. The devices
also have a software power-down mode that reduces the typical
current consumption to typically 400 nA.
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
OUT
VV
REFIN
N
2
D
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535 for the 16-bit AD5065).
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture of the AD5025/AD5045/AD5065 consists
of two matched DAC sections. A simplified circuit diagram is
shown in Figure 40. The four MSBs of the 16-bit data-word are
decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either GND or a V
REF
buffer output. The remaining 12 bits of the data-word drive
Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder
network.
OUT
2R
2R
2R
2R
S1
S0
V
REF
12-BIT R-2R L ADDER FOUR MSBs DECO DED INTO
Figure 40. DAC Ladder Structure
2R
2R
E1
S11
15 EQUAL SEGMENTS
E2
2R
E15
REFERENCE BUFFER
The AD5025/AD5045/AD5065 operate with an external reference.
Each DAC has a dedicated voltage reference pin and an on-chip
reference buffer. The reference input pin has an input range of
2.5 V to V
buffered reference for the DAC core.
. This input voltage is then used to provide a
DD
06844-006
OUTPUT AMPLIFIER
The on-chip output buffer amplifier can generate rail-to-rail
voltages on its output, which gives an output range of 0 V to
. The amplifier is capable of driving a load of 5 kΩ in
V
DD
parallel with 200 pF to GND. The slew rate is 1.5 V/μs with a ¼
to ¾ scale settling time of 13 μs.
SERIAL INTERFACE
The AD5025/AD5045/AD5065 have a 3-wire serial interface
SYNC
, SCLK, and DIN) that is compatible with SPI, QSPI, and
(
MICROWIRE interface standards as well as most DSPs. See
Figure 3 for a timing diagram of a typical write sequence.
INPUT REGISTER
The AD5025/AD5045/AD5065 input register is 32 bits wide
(see Figure 41). The first four bits are don’t cares. The next four
bits are the command bits, C3 to C0 (see Table 8), followed by
the 4-bit DAC address bits, A3 to A0 (see Table 7) and finally
the data bits. These data bits comprise the 12-bit, 14-bit, or 16-bit
input code, followed by eight, six, or four don’t care bits for the
AD5025/AD5045/AD5065, respectively (see Figure 41, Figure 42,
and Figure 43). These data bits are transferred to the DAC
register on the 32
Table 7. Address Commands
A3 A2 A1 A0
0 0 0 0 DAC A
0 0 1 1 DAC B
0 0 0 1 Reserved
0 0 1 0 Reserved
1 1 1 1 Both DACs
Table 8. Command Definitions
Command
C3 C2 C1 C0 Description
0 0 0 0 Write to Input Register n1
0 0 0 1 Update DAC Register n1
0 0 1 0
0 0 1 1 Write to and update DAC Channel n1
0 1 0 0 Power down/power up DAC
0 1 0 1 Load clear code register
0 1 1 0
0 1 1 1 Reset (power-on reset)
1 0 0 0 Set up DCEN register (daisy-chain enable)
1 0 0 1 Reserved
1 1 1 1 Reserved
1
See Table 7.
nd
falling edge of SCLK.
Address (n)
Write to Input Register n, update all
(software LDAC
Load LDAC
)
register
Selected DAC
Channel
Rev. 0 | Page 17 of 28
AD5025/AD5045/AD5065
DB31 (MSB) DB0 (LSB)
X
XXX
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
DATA BITS
ADDRESS BITSCOMMAND BITS
Figure 41. AD5065 Input Register Content
DB31 (MSB) DB0 (LSB)
X
XXX
C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X XXX X
DATA BITS
ADDRESS BITSCOMMAND BITS
Figure 42. AD5045 Input Register Content
DB31 (MSB) DB0 (LSB)
X
XXX
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X XXXXX
DATA BIT S
ADDRESS BITSCOMMAND BITS
Figure 43. AD5025 Input Register Content
06844-007
06844-008
06844-009
Rev. 0 | Page 18 of 28
AD5025/AD5045/AD5065
STANDALONE MODE
The write sequence begins by bringing the
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5025/AD5045/AD5065 compatible
nd
with high speed DSPs. On the 32
falling clock edge, the last
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
SYNC
the mode of operation. The
within 30 ns of the 32
nd
falling edge of SCLK. In either case, it
line must be brought high
must be brought high for a minimum of 1.9 μs before the next
write sequence so that a falling edge of
write sequence. Because the
when V
= VDD than it does when VIN = 0 V,
IN
SYNC
buffer draws more current
idled low between write sequences for even lower power
operation of the part. As mentioned previously, however,
must be brought high again just before the next write sequence.
INTERRUPT
SYNC
In a normal write sequence, the
SYNC
least 32 falling edges of SCLK, and the DAC is updated on the
nd
falling edge. However, if
32
nd
32
falling edge, this acts as an interrupt to the write sequence.
SYNC
The input register is reset, and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operating mode occurs (see Figure 44).
SYNC
line low. Data
SYNC
can initiate the next
SYNC
should be
SYNC
line is kept low for at
is brought high before the
DAISY-CHAINING
For systems that contain several DACs, or where the user wishes to
read back the DAC contents for diagnostic purposes, the SDO
pin can be used to daisy-chain several devices together and
provide serial readback.
The daisy-chain mode is enabled through a software executable
daisy-chain enable (DCEN) command. Command 1000 is
reserved for this DCEN function (see Table 8). The daisy-chain
mode is enabled by setting a bit (DB1) in the DCEN register.
The default setting is standalone mode, where DB1 = 0.
Table 9 shows how the state of the bit corresponds to the mode
of operation of the device.
Table 9. DCEN (Daisy-Chain Enable) Register
DB1 DB0 Description
0 X Standalone mode (default)
1 X DCEN mode
The SCLK is continuously applied to the input register when
SYNC
is low. If more than 32 clock pulses are applied, the data
ripples out of the input shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next DAC in the chain, a multiDAC interface is
constructed. Each DAC in the system requires 32 clock pulses;
therefore, the total number of clock cycles must equal 32N,
where N is the total number of devices in the chain.
SYNC
If
is taken high before 32N clocks are clocked into the
part, it is considered an invalid frame and the data is discarded.
SYNC
When the serial transfer to all devices is complete,
is
taken high. This prevents any further data from being clocked
into the input register.
The serial clock can be continuous or a gated clock. A continuous
SCLK source can be used only if
SYNC
can be held low for the
correct number of clock cycles. In gated clock mode, a burst
clock containing the exact number of clock cycles must be used,
SYNC
and
In daisy-chain mode, the
low. The
mode, as shown in Figure 3. The
must be taken high after the final clock to latch the data.
LDAC
pin cannot be tied permanently
LDAC
pin must be used in asynchronous
LDAC
pin must be brought
LDAC
update
high after pulsing. This allows all DAC outputs to simultaneously
update.
SCLK
SYNC
DIN
SYNC HIGH BEFO RE 32
DB31 DB0
INVALID WRITE SEQUENCE:
ND
FALLING EDGE
Figure 44.
SYNC
Interrupt Facility
DB31 DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32
ND
FALLING EDGE
06844-010
Table 10. 32-Bit Input Register Contents for Daisy-Chain Enable
MSB
LSB
DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0
X 1 0 0 0 X X X X X 1/0 X
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares DCEN register
Rev. 0 | Page 19 of 28
AD5025/AD5045/AD5065
POWER-ON RESET AND SOFTWARE RESET
The AD5025/AD5045/AD5065 contain a power-on reset (POR)
circuit that controls the output voltage during power-up. By
connecting the POR pin low, the AD5025/AD5045/AD5065
output powers up to zero scale. Note that this is outside the
linear region of the DAC; by connecting the POR pin high, the
AD5025/AD5045/AD5065 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code selected by the POR pin. Command 0111 is reserved
for this reset function (see Table 8).
POWER-DOWN MODES
The AD5025/AD5045/AD5065 contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the input register (see
Table 12). Table 11 shows how the state of the bits corresponds
to the mode of operation of the device.
Table 11. Modes of Operation
DB9 DB8 Operating Mode
0 0 Normal operation, power-down modes
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state
When both Bit DB9 and Bit DB8 in the input register are set to 0,
the part works normally with its normal power consumption of
2.2 mA at 5 V. However, for the three power-down modes, the
supply current falls to 0.4 μV at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different options. The output is connected internally to GND
through either a 1 kΩ or a 100 kΩ resistor, or it is left opencircuited (three-state). The output stage is illustrated in Figure 45.
DAC
Figure 45. Output Stage During Power-Down
AMPLIFIER
POWER-DOW N
CIRCUITRY
RESISTOR
NETWORK
V
OUT
06844-011
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 4.5 μs for V
= 5 V (see Figure 24).
DD
Either or both DACs (DAC A and DAC B) can be powered down
to the selected mode by setting the corresponding bits (DB3 and
DB0) to 1. See Table 12 for the contents of the input register
during power-down/power-up operation.
Any combination of DACs can be powered up by setting PD1 = 0
and PD0 = 0 (normal operation). The output powers up to the
LDAC
value in the input register (
DAC register before powering down (
low) or to the value in the
LDAC
high).
Table 12. 32-Bit Input Register Contents for Power-Up/Power-Down Function
MSB LSB
DB31
to
DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20
X 0 1 0 0 X X X X X PD1 PD0 X DAC B DAC B DAC A DAC A
Don’t
cares
Command bits (C2 to C0) Address bits (A3 to A0)—don’t
cares
DB10
to
DB19 DB9 DB8
Don’t
cares
Power-down
mode
DB4
to
DB7 DB3 DB2 DB1 DB0
Don’t
cares
Power-down/power-up channel
selection—set bits to 1 to select
Rev. 0 | Page 20 of 28
AD5025/AD5045/AD5065
CLEAR CODE REGISTER
The AD5025/AD5045/AD5065 have a hardware
is an asynchronous clear input. The
CLR
tive. Bringing the
line low clears the contents of the input
CLR
input is falling edge sensi-
register and the DAC registers to the data contained in the userconfigurable
CLR
register, and sets the analog outputs accordingly
(see Table 13). This function can be used in system calibration
to load zero scale, midscale, or full scale to all channels together.
These clear code values are user-programmable by setting two
bits, Bit DB1 and Bit DB0, in the input register (see Table 13).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 8).
Table 13. Clear Code Register
Clear Code Register
DB1 (CR1) DB0 (CR0) Clears to Code
0 0 0x0000
0 1 0x8000
1 0 0xFFFF
1 1 No operation
The part exits clear code mode on the 32nd falling edge of the
CLR
next write to the part. If
is activated during a write sequence,
the write is aborted.
CLR
The
pulse activation time, the falling edge of
the output starts to change, is typically 10.6 μs (see Figure 31).
See Table 14 for contents of the input register during the
loading clear code register operation.
CLR
CLR
pin that
to when
FUNCTION
LDAC
Hardware
LDAC
Pin
The outputs of all DACs can be updated simultaneously using
the hardware
LDAC
pin. The
LDAC
pin can be used in
synchronous or asynchronous mode, as shown in Figure 3.
LDAC
LDAC
:
Synchronous
the DAC registers are updated on the falling edge of the 32
LDAC
SCLK pulse.
standalone mode.
can be permanently low or pulsed in
LDAC
is held low. After new data is read,
cannot be tied permanently low in
nd
daisy-chain mode.
LDAC
Asynchronous
LDAC
:
is held high and pulsed. The outputs
are not updated at the same time that the input registers are
LDAC
written to. When
goes low, the DAC registers are updated
with the contents of the input register.
Software
LDAC
Function
Alternatively, the outputs of all DACs can be updated simulta-
LDAC
neously using the software
function by writing to Input
Register n (see Table 7) and updating all DAC registers.
LDAC
Command 0010 is reserved for this software
LDAC
The
over the hardware
register gives the user extra flexibility and control
LDAC
pin (see Table 16). Setting the
function.
LDAC
bit register (DB0 to DB3) to 0 for a DAC channel means that
LDAC
this channel update is controlled by the hardware
pin.
If DB0 or DB3 is set to 1, this channel updates synchronously.
LDAC
The part effectively sees the hardware
low (see Table 15 for the
LDAC
register mode of operation).
pin as being tied
This flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
Table 14. 32-Bit Input Register Contents for Clear Code Function
MSB
DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0
X 0 1 0 1 X X X X X 1/0 1/0
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares
Table 15.
LDAC
0 1, 0
1 X1
1
X = don’t care.
LDAC
Bits (DB3 and DB0)
Table 16. 32-Bit Input Register Contents for
MSB
DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB4 to DB19 DB3 DB2 DB1 DB0
X 0 1 1 0 X X X X X DAC B X X DAC A
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares
Clear code register
Overwrite Definitions
Load DAC Register
Pin
LDAC
Operation
LDAC
Determined by LDAC
DAC channels update, overrides the LDAC
Overwrite Function
LDAC
Rev. 0 | Page 21 of 28
pin.
pin. DAC channels see LDAC as 0.
LDAC
Set
bits to 1 to override
(CR1 to CR0)
LDAC
LSB
LSB
pin
AD5025/AD5045/AD5065
POWER-DOWN LOCKOUT
The AD5025/AD5045/AD5065 contain a digital input pin,
PDL
PDL
PDL
features.
PDL
remains active,
CLR
.
When activated, the power-down lockout pin (
software shutdown under any circumstances. The user should
PDL
hardwire the
software power-down) or logic high (the part can be placed in
power-down mode over the serial interface). If the user transitions
PDL
the
sequence, the device responds immediately and the current
write sequence is aborted. Note the following
PDL
If a
valid write sequence is ongoing, the write is aborted. The user
must rewrite the current write command again.
PDL
If a
mode, the DAC(s) come out of power-down (that is, all powerdown bits are reset to 0000) to the last voltage output corresponding to the last valid stored DAC value. While
software power-down is disabled.
PDL
After
remain in normal mode, and the user must reissue a software
power-down command to the control register to power down
the required channels.
Tr an si ti o ni ng
immediately.
If
causes the DAC register to change as per the clear code register,
and the DACs come out of power-down.
If
has higher precedence over
pin from logic high to a logic low during a valid write
During a Write Sequence
PDL
is generated (that is, a high-to-low transition) while a
While DACs in Power-Down Mode
PDL
is generated while the DAC(s) are in power-down
Low to High Transition
PDL
PDL
and
CLR
PDL
,
pin to a logic low (thus preventing subsequent
is taken from a low to a high state, all DAC channels
PDL
from a low to a high disables the feature
CLR
are generated at the same time, the
LDAC
, and
are generated at the same time,
LDAC
and
PDL
) disables
signal
CLR
.
The user is recommended to hardwire the pin to a logic high or
low, thereby either enabling or disabling the feature.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board (PCB) containing the AD5025/AD5045/
AD5065 should have separate analog and digital sections. If the
AD5025/AD5045/AD5065 are in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5025/AD5045/AD5065.
Bypass the power supply to the AD5025/AD5045/AD5065 with
10 μF and 0.1 μF capacitors. The capacitors should physically be
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), which is typical of common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield clocks and other fast switching digital signals
from other parts of the board by digital ground. Avoid crossover
of digital and analog signals if possible. When traces cross on
opposite sides of the board, ensure that they run at right angles
to each other to reduce feedthrough effects through the board.
The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the
ground plane only and the signal traces are placed on the solder
side. However, this is not always possible with a 2-layer board.
Rev. 0 | Page 22 of 28
AD5025/AD5045/AD5065
MICROPROCESSOR INTERFACING
AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x Interface
Figure 46 shows a serial interface between the AD5025/AD5045/
AD5065 and the Blackfin® ADSP-BF53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5025/AD5045/AD5065, the setup for the interface is
as follows: DT0PRI drives the DIN pin of the AD5025/AD5045/
SYNC
AD5065, and TSCLK0 drives the SCLK of the parts. The
driven from TFS0.
ADSP-BF53x*
*ADDITIONAL P INS OMIT TED FOR CL ARITY.
Figure 46. AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x Interface
AD5025/
AD5045/
AD5065
SYNCTFS0
DINDT0PRI
SCLKTSCLK0
*
06844-012
AD5025/AD5045/AD5065 to 68HC11/68L11 Interface
Figure 47 shows a serial interface between the AD5025/AD5045/
AD5065 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5025/AD5045/AD5065,
and the MOSI output drives the serial data line of the DAC.
68HC11/68L11*
*ADDITIONAL P INS OMIT TED FOR CL ARITY.
Figure 47. AD5025/AD5045/AD5065 to 68HC11/68L11 Interface
SYNC
The
signal is derived from a port line (PC7). The setup
AD5025/
AD5045/
AD5065
SYNCPC7
SCLKSCK
DINMOSI
*
06844-013
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC
line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5025/AD5045/
AD5065, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
is
AD5025/AD5045/AD5065 to 80C51/80L51 Interface
Figure 48 shows a serial interface between the AD5025/AD5045/
AD5065 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5025/AD5045/AD5065, and RxD drives the serial
SYNC
data line of the part. The
signal is again derived from a
bit-programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5025/AD5045/
AD5065, P3.3 is taken low. The 80C51/80L51 transmits data in
8-bit bytes only; thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is lept low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data in LSB-first format. The AD5025/AD5045/AD5065
must receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 48. AD5025/AD5045/AD5065 to 80C51/80L51 Interface
AD5025/
AD5045/
AD5065
SYNCP3.3
SCLKTxD
DINRxD
*
06844-014
AD5025/AD5045/AD5065 to MICROWIRE Interface
Figure 49 shows an interface between the AD5025/AD5045/
AD5065 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked into
the AD5025/AD5045/AD5065 on the rising edge of SCLK.
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 49. AD5025/AD5045/AD5065 to MICROWIRE Interface
AD5025/
AD5045/
AD5065
SYNCCS
DINSK
SCLKSO
*
06844-015
Rev. 0 | Page 23 of 28
AD5025/AD5045/AD5065
V
V
APPLICATIONS INFORMATION
USING A REFERENCE AS A POWER SUPPLY FOR THE AD5025/AD5045/AD5065
Because the supply current required by the AD5025/AD5045/
AD5065 is extremely low, an alternative option is to use a voltage
reference to supply the required voltage to the parts (see Figure 50).
This is especially useful if the power supply is quite noisy or if
the system supply voltages are at some value other than 5 V or
3 V, for example, 15 V. The voltage reference outputs a steady
supply voltage for the AD5025/AD5045/AD5065. If the low
dropout REF195 is used, it must supply 500 μA of current to
the AD5025/AD5045/AD5065 with no load on the output of
the DAC. When the DAC output is loaded, the REF195 also needs
to supply the current to the load. The total current required
(with a 5 kΩ load on the DAC output) is
500 μA + (5 V/5 kΩ) = 1.5 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 μV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.196 LSB error.
15
REF195
3-WIRE
SERIAL
INTERFACE
Figure 50. REF195 as Power Supply to the AD5025/AD5045/AD5065
SYNC
SCLK
DIN
5V
V
AD5025/
AD5045/
AD5065
DD
x = 0V TO 5V
V
OUT
06844-016
BIPOLAR OPERATION USING THE AD5025/AD5045/AD5065
The AD5025/AD5045/AD5065 is designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 51. The circuit gives an output voltage range of
±5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
R2 = 10kΩ
+5
0.1µF
10µF
Figure 51. Bipolar Operation with the AD5025/AD5045/AD5065
R1 = 10kΩ
V
V
DD
OUT
AD5025/
AD5045/
AD5065
3-WIRE
SERIAL INT ERFACE
+5V
AD820/
OP295
–5V
±5V
USING THE AD5025/AD5045/AD5065 WITH A GALVANICALLY ISOLATED INTERFACE
In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous commonmode voltages that can occur in the area where the DAC is
functioning. iCoupler® provides isolation in excess of 2.5 kV.
The AD5025/AD5045/AD5065 use a 3-wire serial logic interface,
so the ADuM1300 three-channel digital isolator provides the
required isolation (see Figure 52). The power supply to the part
also needs to be isolated, which is achieved by using a transformer.
On the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5025/AD5045/AD5065.
5V
POWER
SCLK
SDI
V
IA
ADuM1300
V
IB
V
OA
V
OB
REGULATOR
SCLK
SYNC
V
DD
AD5025/
AD5045/
AD5065
10µF
V
OUT
0.1µF
x
6844-017
O
VV
536,65
R2R1D
R1
V
where D represents the input code in decimal (0 to 65,535).
With V
= 5 V, R1 = R2 = 10 kΩ,
DD
10
D
V
O
536,65
V5
R2
DDDD
R1
Rev. 0 | Page 24 of 28
DATA
Figure 52. AD5025/AD5045/AD5065 with a Galvanically Isolated Interface
V
IC
V
OC
DIN
GND
06844-018
AD5025/AD5045/AD5065
OUTLINE DIMENSIONS
5.10
5.00
4.90
4.50
4.40
4.30
PIN 1
1.05
1.00
0.80
0.15
0.05
COPLANARITY
0.10
14
1
0.65 BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
8
6.40
BSC
7
1.20
0.20
MAX
SEATING
PLANE
0.09
8°
0°
0.75
0.60
0.45
061908-A
Figure 53. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model Temperature Range Package Description
AD5025BRUZ1 −40°C to +125°C 14-Lead TSSOP RU-14 ±0.25 LSB INL 12 bits
AD5025BRUZ-REEL71 −40°C to +125°C 14-Lead TSSOP RU-14 ±0.25 LSB INL 12 bits
AD5045BRUZ1 −40°C to +125°C 14-Lead TSSOP RU-14 ±0.5 LSB INL 14 bits
AD5045BRUZ-REEL71 −40°C to +125°C 14-Lead TSSOP RU-14 ±0.5 LSB INL 14 bits
AD5065ARUZ1 −40°C to +125°C 14-Lead TSSOP RU-14 ±4 LSB INL 16 bits
AD5065ARUZ-REEL71 −40°C to +125°C 14-Lead TSSOP RU-14 ±4 LSB INL 16 bits
AD5065BRUZ1 −40°C to +125°C 14-Lead TSSOP RU-14 ±1 LSB INL 16 bits
AD5065BRUZ-REEL71 −40°C to +125°C 14-Lead TSSOP RU-14 ±1 LSB INL 16 bits
1
Z = RoHS Compliant Part.
Option Accuracy Resolution
Rev. 0 | Page 25 of 28
AD5025/AD5045/AD5065
NOTES
Rev. 0 | Page 26 of 28
AD5025/AD5045/AD5065
NOTES
Rev. 0 | Page 27 of 28
AD5025/AD5045/AD5065
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06844-0-10/08(0)
Rev. 0 | Page 28 of 28
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