Page 1
PRELIMINARY TECHNICAL DA TA
2 Pair/1 Pair ETSI Compatible
a
HDSL Analog Front End
Preliminary Technical Data AD5011
FEATURES
Integrated front End for Single Pair or Two Pair HDSL
Systems
Meets ETSI Specifications
Supports 1168 kbps and 2.32 Mbps
Programmable Filtering Supports Adaptive HDSL
Transmit and Receive Signal Path Functions
Receive Hybrid Amplifier, PGA, ADC and Adaptable
Filter
Transmit DAC, Adaptable Filter and Differential
Outputs
Normal Loopback
Serial Interface to Digital Transceivers
Single 3 V Power Supply
FUNCTIONAL BLOCK DIAGRAM
VDRIVE
TxDATA
TxSYNC
TxCLK
Tx-DECOUP
14-Bit DAC
GENERAL DESCRIPTION
The AD5011 is an analog front end for two pair or single
pair HDSL applications that use 1168 kbps or 2.32 Mbps
data rates. The device integrates all the transmit and receive
functional blocks. A standard serial interface is used to
communicate with the DAC and ADC. The filters in both
the transmit and receive paths are programmable which
allows adaptive HDSL to be performed also. The part is
available in a 48-pin LQFP package and is specified for a
temperature range of -40
6 Pole Adaptive
Be s s el Filt e r
PGA
0 dB
-6 dB
o
C to +85 oC.
Line
Driver
DRV-OUTP
DRV-OUTN
ADCCLK
SCLK
SDO
DR
CAP-T
CAP-B
REF-COM
VREF
CM-LVL
SPICLK
TFS
DT
DR
RESETB
PWRDOW NB
12-Bit ADC
SPI
Control/
Configuration
ADC
Buffer
ADCINN
ADCINP
4 Pole Adaptive
Butterworth Filter
FILOUTP
FILOUTN
-6 dB
-3 dB
0 dB
+3 dB
+6 dB
HYBIN-2B
HybridPGA
HYBIN-2A
HYBIN-1A
HYBIN-1B
REV PrA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 Fax: 781/326-8703
World Wide Web Site: hppt://www.analog.com
Page 2
PRELIMINARY TECHNICAL DA TA
AD5011–SPECIFICATIONS
(VDD = +3.15 V to +3.45 V; AGND = DGND = 0 V; TA = T
1
noted)
MIN
to T
unless otherwise
MAX
Parameter AD5011B Units Test Conditions/Comments
Min Typ Max
TRANSMIT CHANNEL
Signal to Noise
Total Harmonic Distortion
2
2
68 71 dB F
66 71 dB F
= 73 kHz
OUT
= 73 kHz
OUT
TRANSMIT DAC
Resolution 14 Bits
Clock Frequency 18.688 MH z
Coding 2s Complement
Output Update Rate
3
1168 kHz
Output Voltage 1 Vpp Diff
TRANSMIT FILTER
Cutoff Frequency
4
49 - 120.8 kHz Bottom Range (8 kHz steps)
108 - 265 kHz Mid Range (18 kHz steps)
235 - 580 kHz Top Range (40.5 kHz steps)
Corner Frequency Accuracy
+5 +10 %
Adjacent Corner Step +40 % nom
LINE DRIVER
5
VCM 1.5 V
Common Mode Voltage Error
+100 mV
Output Power 13.5 dB m
Output Voltage 4 Vpp Diff Tx-GAIN = 0
2 Vpp Diff Tx-GAIN = 1
Channel Gain Accuracy +1 dB
RECEIVE CHANNEL
Signal to (Noise + Distortion)
6
66 68 dB FIN = 73 kHz
Total Harmonic Distortion 68 71 d B FIN = 73 kHz
HYBRID INTERFACE
Input Voltage Range 5 Vpp Diff PGA = 0 dB
Common Mode Input Voltage 1.5 V
Input Impedance 10 k W
Input Offset Voltage 80 m V PGA = 0 dB
PROGRAMMABLE GAIN AMPLIFIER
Overall Gain Accuracy
7
For all Gain Settings from -6 dB to +9 dB
+1 dB
Gain Step 3 d B
Gain Step Accuracy +0.25 dB
RECEIVE FILTER
Cutoff Frequency
4
49 - 120.8 kHz Bottom Range (8 kHz steps)
108 - 265 kHz Mid Range (18 kHz steps)
235 - 580 kHz Top Range (40.5 kHz steps)
Accuracy
Adjacent Corner Step
+5 +10 %
+40 % nom
Output Load Capacitance 20 p F
Output Load Resistance T BD W
RECEIVE ADC
Resolution 12 Bits
Coding 2s Complement
Sample Rate 2.32 MHz
LOGIC INPUTS
Input Logic High, V
Input Logic Low, V
I
, Input Current +10 m AV
IN
INH
INL
8
23 V
0 0.2 V
= 0 V to DVDD
IN
CIN, Input Capacitance 10 pF
–2–
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PRELIMINARY TECHNICAL DA TA
AD5011
Parameter AD7346B Units Test Conditions/Comments
Min Typ Max
LOGIC OUTPUTS
Output Logic High, V
Output Logic Low, V
OH
OL
9
VDD - 0.3 V I
0.3 V I
OUT
OUT
= 200 mA
= 200 mA
POWER SUPPLIES
AVDD, DVDD 3.15 3.3 3.45 V
IDD
Normal Mode (excluding Driver) 32 m A
Line Driver 75 mA 33 W Differential Load
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The complete transmit path spectrum and pulse shape comply with ETSI requirements. SNR and THD are measured within a 547 kHz bandwidth. Noise and Spurious
tones beyong 540 kHz are therefore excluded.
3
The transmit DAC maximum update rate is half the maximum output data rate i.e. 1168 kHz. The maximum transmit clock is 16 x 1168 = 18.688 MHz.
4
There are three ranges (bottom range, mid range, top range), each range being divided into eight steps. The transmit filter corner frequency can be set independently from
the receive filter corner frequency. the filter tuning circuit requires a continuous 16.384 MHz clock applied to the Fclk pin.
5
Transformer turns ratio = 1:2:3 at 50 kHz when loaded by ETSI (RTR/TM3036) HDSL test loops.
6
With 547 kHz filter snd 0 dB PGA gain selected.
7
The PGA gain is set by setting the PGA-GC bits in the control register.
8
The input switching threshold voltage is approximately 1.2 V to allow interfacing to 2.5 V and 3.3 V logic.
9
The output level is determined by the voltage on the logic supply pin V
Specifications subject to change without notice.
DRIVE
.
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–3–
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AD5011
PRELIMINARY TECHNICAL DATA
TIMING CHARACTERISTICS
(VDD = +2.7 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)
Limit at
T
to T
MIN
MAX
Parameter (B Version) Units Test Conditions/Comments
ADCCLK <= 1160kHz
t
1
t
2
t
3
t
4
t
5
1.5*t
2*t
3
2.5*t
3*t
3
3
3
ns min ADCCLK Rising Edge to SCLK Rising Edge Delay
ns typ
ns min SCLK Rising Edge to ADCCLK Falling Edge Delay
ns typ
26.939 ns min SCLK Period (1/32*ADCCLK Period)
5 ns min Data Setup Time Before SCLK Falling Edge
10 ns min Data Hold Time After SCLK Falling Edge
1160 kHz < ADCCLK <= 2320 kHz
t
6
t
7
t
8
t
9
t
10
20 ns min ADCCLK Rising Edge to SCLK Rising Edge Delay
1*t
8
ns typ
1.5*t8 ns min SCLK Rising Edge to ADCCLK Falling Edge Delay
2*t
8
ns typ
26.939 ns min SCLK Period (1/16*ADCCLK Period)
5 ns min Data Setup Time Before SCLK Falling Edge
10 ns min Data Hold Time After SCLK Falling Edge
TRANSMIT DAC
t
11
t
12
t
13
t
14
t
15
53.5 ns min TxCLK Period (1/18.688 MHz)
12 ns min Data Setup Time Before TxCLK Rising Edge
10 ns min Data Hold Time After TxCLK Rising Edge
t
11
ns min TxSYNC Low Time
3 ns min TxCLK Rising Edge to TxSYNC Falling Edge Delay
t11/2 ns max
CONTROL REGISTER
t
16
50 ns min SPICLK Period
76 ns typ
t
17
t
18
t
19
t
20
t
21
t
22
t
23
Guaranteed by design but not production tested.
15 ns min TFS Setup Time Before SPICLK Falling Edge
t
- 15 ns max
16
15 ns min TFS Hold Time After SPICLK Falling Edge
t
- 15 ns max
16
t
16
7 ns min DT Setup Time Before SPICLK Falling Edge
10 ns min DT Hold Time After SPICLK Falling Edge
7 ns min DR Setup Time Before SPICLK Falling Edge (R/W = 1)
10 ns min DR Hold Time After SPICLK Falling Edge (R/W = 1)
t
1
ADCCLK
SCLK
t
4
SDO
D11
ns typ TFS High Time
t
3
D10 D1
t
2
t
5
D0
D11 D10 D9
SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges
Figure 1. ADC Timing (ADCCLK <= 1160 kHz)
–4–
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PRELIMINARY TECHNICAL DA TA
t
t
6
ADCCLK
t
8
SCLK
t
9
SDO
D11
D10 D1
SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges
Figure 2. ADC Timing (1160 kHz < ADCCLK <= 2320 kHz)
TxCLK
t
14
TxSYNC
7
t
10
D0
t
13
t
15
D11
D10 D1
D0
D11 D10 D9
AD5011
t
12
t
11
TxDATA
D13
D11
D12 D1 D0
D2
X
X
D13 D12
The rising edge of TxSYNC can occur anywhere as long at the TxSYNC low time exceeds one TxCLK period. The TxSYNC falling edge
must occur after the TxCLK rising edge which captures the LSB of the previous word. This ensures correct loading into the DAC. The
first 14 bits are loaded into the DAC, the 2 LSBs being don't cares.
Figure 3. DAC Timing
t
16
SPICLK
t
TFS
DR
(R/W = 1 )
17
DT
t
R/W
t
18
19
t
20
SEL2
SEL1
SEL0
D11
D10
D11
t
21
D1
DO
t
23
D1
DO
D10
t
22
DR
(R/W = 0
If R/W = 1, the selected register's contents will be output on DR. If R/W = 0, no data will be output on DR. The SEL bits identify
which of the four register banks is being written to. The 12 LSBs contain the word. When the AD5011 is reset using RESETB, the
registers are reset to zero.
Figure 4. Control Interface
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–5–
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PRELIMINARY TECHNICAL DATA
AD5011
PIN DESCRIPTION
Mnemonic Function
POWER SUPPLY
VDRIVE Digital output drive level.
AGND Analog power supply.
AGND Analog Ground.
DVDD Positive power supply for the digital section.
DGND Digital Ground.
TRANSMIT CHANNEL
TxDATA Transmit data input.
TxSYNC Transmit data frame synchronization, logic input.
TxCLK Transmit serial clock, logic input.
TxDECOUP Transmit DAC reference decoupling pin. The reference which supplies the DAC needs some
external decoupling.
DRV-OUTP Differential line driver positive output.
DRV-OUTN Differential line driver negative output.
EXTERNAL INTERFACE
SPICLK Serial interface clock, logic input.
TFS Serial Interface frame synchronisation, logic input.
DT Serial interface data input.
DR Serial interface data output.
RESETB Master Reset. This is an active low logic input.
PWRDWNB Master powerdown. When PWRDWNB is taken low, the complete AD5011 device is placed in a
sleep mode.
FCLK Filter tuning clock. The clock for the filter tuning circuit in both the transmit and receive paths is
supplied to FCLK. A 16.384 MHz should be connected to this pin to obtain the specified
frequencies.
TEST Test Mode. When TEST is tied to DVDD, the AD5011 is placed in a test mode. For normal
operation, this pin should be tied to DGND.
RECEIVE CHANNEL
HYBIN-2B Hybrid non-inverting input.
HYBIN-2A Hybrid inverting input.
HYBIN-1B Hybrid inverting input.
HYBIN-1A Hybrid non-inverting input.
FILTOUTP Positive differential output of the antialiasing filter.
FILTOUTN Negative differential output of the antialiasing filter.
ADCINP Positive differential input to the ADC.
ADCINN Negative differential input to the ADC.
CAP-T Receive ADC reference decoupling pin. The reference which supplies the ADC needs some external
decoupling.
CAP-B Receive ADC reference decoupling pin. The reference which supplies the ADC needs some external
decoupling.
VREF Voltage Reference. The external reference is applied to this pin.
REF-COM Reference common.
COM-LVL Common mode level.
ADCCLK ADC Sample clock, logic input. This clock also operates as the frame synchronization.
SCLK ADC serial interface clock, logic input.
SDO ADC serial data out.
–6–
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PRELIMINARY TECHNICAL DA TA
Table 1. Control Register
Serial Register SEL[2:0]=000 SEL[2:0]=001 SEL[2:0]=010 SEL[2:0]=011
Control Reg Tx Prog Filt Reg Rx Prog Filt Reg Test Purposes Only
D[15] R/W = 0 R/W = 0 R/W = 0 R/W = 0
D[14] SEL[2] = 0 SEL[2] = 0 SEL[2] = 0 SEL[2] = 0
D[13] SEL[1] = 0 SEL[1] = 0 SEL[1] = 1 SEL[1] = 1
D[12] SEL[0] = 0 SEL[0] = 1 SEL[0] = 0 SEL[0] = 1
D[11]
D[10]
D[9] LOOPBACK TPFD[9] RPFD[9] Reserved
D[8] AA-BUF-BP TFPD[8] RPFD[8] Reserved
D[7] AA-FLTR-BP TFPD[7] RFPD[7] Reserved
D[6] Tx-GAIN-SEL TFPD[6] RFPD[6] Reserved
D[5] Tx-DACOUT TFPD[5] RFPD[5] Reserved
D[4] Tx-LPF-BP TFPD[4] RFPD[4] Reserved
D[3] Tx-DRVR-BP TFPD[3] RFPD[3] Reserved
D[2] PGA-GC2 TFPD[2] RFPD[2] Reserved
D[1] PGA-GC1 TFPD[1] RFPD[1] Reserved
D[0] PGA-GC0 TFPD[0] RFPD[0] Reserved
PWDN-Tx WRBOTH WRBOTH Reserved
PWDN-Rx TPFD[10] RPFD[10] Reserved
AD5011
Control Register Functions
Mnemonic Function
R/
W When R/W is high, the register bank addressed by SEL[2:0] is loaded into the output shift register.
Serial data will subsequently be output onto the DR pin. If R/
at D[11:0] will be written into the register bank addressed by SEL[2:0].
PWDN-Tx When PWDN-Tx is low, the entire transmit channel is powered down. The line driver output is
high impedance when the transmit channel is powered down.
PWDN-Rx When this bit is low, the entire receive channel is powered down.
LOOPBACK When this bit is high, analog loopback is selected.
AA-BUF-BP When this bit equals 1, the ADC buffer is bypassed.
AA-FLTR-BP When this bit equals 1, the receive filter is bypassed.
Tx-GAIN-SEL When Tx-GAIN-SEL equals 1, the output of the transmit filter is attenuated by 6 dB.
WRBOTH The transmit and receive programmable filter corner frequencies are addressed by the 11-bits words
TPFD and RPFD respectively. TPFD data is loaded from the serial input register to the transmit
filter register if SEL[2:0] = 010. RPFD data is written to the receive filter register if SEL[2:0] =
010. If WRBOTH equals 1 during either of the above conditions, the word in the serial input
register is loaded into both the TFPD and RFPD registers.
Configuring the Transmit Channel
Tx-DACOUT Tx-FILT-BP Tx-DRVR-BP Configuration
0 0 0 Default. All Components in the Tx channel are used.
1 0 0 The DAC output is seen at the line driver output pins. The line driver
amplifier output is in a high impedance state.
0 1 0 The Tx filter is bypassed. The DACOUT is fed to the PGA. The
filter amplifier output is in a high impedance state.
0 0 1 The filter output is seen at the line driver output pins. The line driver
amplifier output is in a high impedance state.
W is low, the serial input data located
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–7–
Page 8
AD5011
PRELIMINARY TECHNICAL DATA
Programmable Gain Amplifier Gain Settings (Receive Signal)
GGA-GC2 PGA-GC1 PGA-GC0 Gain (dB)
000 -6
001 -3
010 0
011 3
100 6
101 9
110 9
111 9
Transmit and Receive Filter Corner Frequency (kHz)
TPFD [7:0] TPFD[8] TPFD[9] TPFD[10]
RPFD[0:7] RPFD[8] RPFD[9] RPFD[10]
TBD 49 108 235
TBD 52 114 250
TBD 59.8 131 287
TBD 67.5 148 324
TBD 75.3 165 361
TBD 83 182 399
TBD 90.8 199 436
TBD 98.5 216 473
TBD 106.3 233 510
TBD 114 250 547
TBD 120.8 265 580
–8–
REV PrA
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