Datasheet AD420AR-32, AD420AN-32 Datasheet (Analog Devices)

AD420

V

CC

4kV

40V

BOOST

I

OUT

V

OUT

FAULT
DETECT

GNDCAP 1

OFFSET

TRIM

V

LL

REF OUT

REF IN

DATA OUT

CLEAR

LATCH

CLOCK

DATA IN

RANGE

SELECT 1

RANGE

SELECT 2

1.25kV

REFERENCE

CLOCK

16-BIT

DAC

DATA I/P

REGISTER

SWITCHED

CURRENT
SOURCES

AND

FILTERING

CAP 2

Serial Input 16-Bit

a

FEATURES
4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA Current Output
16-Bit Resolution and Monotonicity

ⴞ0.012% Max Integral Nonlinearity
ⴞ0.05% Max Offset (Trimmable)
ⴞ0.15% Max Total Output Error (Trimmable)

Flexible Serial Digital Interface (3.3 MBPS)
On-Chip Loop Fault Detection
On-Chip 5 V Reference (25 ppm/ⴗC Max)
Asynchronous CLEAR Function
Maximum Power Supply Range of 32 V
Output Loop Compliance of 0 V to V
24-Lead SOIC and PDIP Packages

PRODUCT DESCRIPTION

The AD420 is a complete digital to current loop output con­verter, designed to meet the needs of the industrial control
market. It provides a high precision, fully integrated, low cost
single-chip solution for generating current loop signals in a
compact 24-lead SOIC or PDIP package.

The output current range can be programmed to 4 mA–20 mA,
0 mA–20 mA or an overrange function of 0 mA–24 mA. The
AD420 can alternatively provide a voltage output from a sepa­rate pin that can be configured to provide 0 V–5 V, 0 V–10 V,

±5 V or ±10 V with the addition of a single external buffer

amplifier.

The 3.3M Baud serial input logic design minimizes the cost of
galvanic isolation and allows for simple connection to com­monly used microprocessors. It can be used in three-wire or
asynchronous mode and a serial-out pin is provided to allow
daisy chaining of multiple DACs on the current loop side of the
isolation barrier.

The AD420 uses sigma-delta (Σ∆) DAC technology to achieve

16-bit monotonicity at very low cost. Full-scale settling to 0.1%
occurs within 3 ms. The only external components that are re­quired (in addition to normal transient protection circuitry) are
two low cost capacitors which are used in the DAC output filter.

If the AD420 is going to be used at extreme temperatures and
supply voltages, an external output transistor can be used to
minimize power dissipation on the chip via the “BOOST” pin.

The FAULT DETECT pin signals when an open circuit occurs
in the loop. The on-chip voltage reference can be used to supply
a precision +5 V to external components in addition to the
AD420 or, if the user desires temperature stability exceeding

25 ppm/°C, an external precision reference such as the AD586

can be used as the reference.

SPI is a registered trademark of Motorola.
MICROWIRE is a registered trademark of National Semiconductor.

REV. F

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

– 2.5 V

CC

4 mA–20 mA, 0 mA–20 mA DAC

AD420

FUNCTIONAL BLOCK DIAGRAM

The AD420 is available in a 24-lead SOIC and PDIP over the

industrial temperature range of –40°C to +85°C.

PRODUCT HIGHLIGHTS

1. The AD420 is a single chip solution for generating 4 mA–
20 mA or 0 mA–20 mA signals at the “controller end” of the
current loop.

2. The AD420 is specified with a power supply range
from 12 V to 32 V. Output loop compliance is 0 V to
V

– 2.5 V.

CC

3. The flexible serial input can be used in three-wire mode
with SPI
chronous mode which minimizes the number of control
signals required.

4. The serial data out pin can be used to daisy chain any num­ber of AD420s together in three-wire mode.

5. At power-up the AD420 initializes its output to the low end
of the selected range.

6. The AD420 has an asynchronous CLEAR pin which sends
the output to the low end of the selected range (0 mA,
4 mA, or 0 V).

7. The AD420 BOOST pin accommodates an external transis­tor to off-load power dissipation from the chip.

8. The offset of ±0.05% and total output error of ±0.15% can

be trimmed if desired, using two external potentiometers.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

®

or MICROWIRE® microcontrollers, or in asyn-

AD420–SPECIFICATIONS

(TA = T

, VCC = +24 V, unless otherwise noted)

MIN–TMAX

AX-32 Version

1

Parameter Min Typ Max Units Comments

RESOLUTION 16 Bits

CHARACTERISTICS R

I

OUT

= 500 Ω

L

Operating Current Ranges 4 20 mA

020mA

024mA
Current Loop Voltage Compliance 0 V
Settling Time (to 0.1% of FS)

Output Impedance (Current Mode) 25 MΩ

Accuracy

3

2

2.5 3 ms

– 2.5 V V

CC

Monotonicity 16 Bits

Integral Nonlinearity ±0.002 ±0.012 %

Offset (0 mA or 4 mA) (T

= +25°C) ±0.05 %

A

Offset Drift 20 50 ppm/°C

Total Output Error (20 mA or 24 mA) (T

Total Output Error Drift 20 50 ppm/°C

4

PSRR

CHARACTERISTICS

V

OUT

= +25°C) ±0.15 %

A

510 µA/V

FS Output Voltage Range (Pin 17) 0 5 V

VOLTAGE REFERENCE

REF OUT

Output Voltage (T

= +25°C) 4.995 5.0 5.005 V

A

Drift ±25 ppm/°C

Externally Available Current 5 mA
Short Circuit Current 7 mA

REF IN

Resistance 30 kΩ

V

LL

Output Voltage 4.5 V
Externally Available Current 5 mA
Short Circuit Current 20 mA

DIGITAL INPUTS

(Logic 1) 2.4 V

V

IH

(Logic 0) 0.8 V

V

IL

(V

= 5.0 V) ±10 µA

I

IH

IN

I

(V

= 0 V) ±10 µA

IL

IN

Data Input Rate (“3-Wire” Mode) No Minimum 3.3 MBPS
Data Input Rate (“Asynchronous” Mode) No Minimum 150 kBPS

DIGITAL OUTPUTS

FAULT DEFECT

(10 kΩ Pull-Up Resistor to V

V

OH

(10 kΩ Pull-Up Resistor to V

V

OL

V

@ 2.5 mA 0.6 V

OL

) 3.6 4.5 V

LL

)0.20.4V

LL

DATA OUT

(IOH = –0.8 mA) 3.6 4.3 V

V

OH

VOL (IOL = 1.6 mA) 0.3 0.4 V

POWER SUPPLY

Operating Range V

CC

12 32 V
Quiescent Current 4.2 5.5 mA
Quiescent Current (External VLL)3mA

TEMPERATURE RANGE

Specified Performance –40 +85 °C

NOTES

1

X refers to package designator, R or N.

2

External capacitor selection must be as described in Figure 5.

3

Total Output Error includes Offset and Gain Error. Total Output Error and Offset Error are with respect to the Full-Scale Output and are measured with an ideal

+5 V reference. If the internal reference is used, the reference errors must be added to the Offset and Total Output Errors.

4

PSRR is measured by varying VCC from 12 V to its maximum 32 V.

Specifications subject to change without notice.

REV. F–2–

ABSOLUTE MAXIMUM RATINGS*

AD420

V

CC

4kV 40V

BOOST

I

OUT

V

OUT

FAULT
DETECT

GND

CAP 1

OFFSET

TRIM

V

LL

REF OUT

REF IN

DATA OUT

CLEAR
LATCH

CLOCK

DATA IN

RANGE

SELECT 1

RANGE

SELECT 2

1.25kV

REFERENCE

CLOCK

16-BIT

DAC

DATA I/P

REGISTER

19

20

21

23

14

15

16

17

18

6
7
8
9

10

11

2

3

4

5

SWITCHED

CURRENT
SOURCES

AND

FILTERING

CAP 2

VCC to GND

AD420AR/AN-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

I

OUT

CC

Digital Inputs to GND . . . . . . . . . . . . . . . . . . . –0.5 V to +7 V

Digital Output to GND . . . . . . . . . . . . . –0.5 V to V

and REF OUT: Outputs Safe for Indefinite Short to Ground

V

LL

+ 0.3 V

LL

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Thermal Impedance:

SOIC (R) Package . . . . . . . . . . . . . . . . . . . . . .θ

PDIP (N) Package . . . . . . . . . . . . . . . . . . . . . . θ

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

= 75°C/W

JA

= 50°C/W

JA

AD420

Figure 1. Functional Block Diagram

ORDERING GUIDE

Temperature Max Operating Package

Model Range Voltage Options*

AD420AN-32 – 40°C to +85°C 32 V N-24
AD420AR-32 –40°C to +85°C 32 V R-24

*N = Plastic DIP, R = Plastic SOIC.

PIN DESIGNATIONS

NC

V

FAULT DETECT

RANGE SELECT 2
RANGE SELECT 1

CLEAR
LATCH
CLOCK

DATA IN

DATA OUT

GND

NC

LL

AD420

TOP VIEW

(Not to Scale)

NC = NO CONNECT

NC
V

CC

NC
CAP2
CAP1
BOOST
I

OUT

V

OUT

OFFSET TRIM
REF IN
REF OUT
NC

Table I. Truth Table

Inputs

Range Range

CLEAR Select 2 Select 1 Operation

0 X X Normal Operation
1 X X Output at Bottom of Span

X 0 0 0 V–5 V Range
X 0 1 4 mA–20 mA Range
X 1 0 0 mA–20 mA Range
X 1 1 0 mA–24 mA Range

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD420 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. F –3–

WARNING!

ESD SENSITIVE DEVICE

AD420

CLOCK

DATA IN

CLOCK

DATA IN

t

ADH

t

ACK

t

ADW

t

ACL

t

ADS

START

BIT

01 100

BIT 15

BIT 14

BITs

13-1

BIT 0

STOP

BIT

NEXT

START

BIT

(INTERNALLY GENERATED LATCH)

EXPANDED TIME VIEW BELOW

CLOCK COUNTER STARTS HERE

CONFIRM START BIT

SAMPLE BIT 15

0 1 2 8 16 24

START BIT

DATA BIT 15

BIT 14

EXPANDED TIME VIEW BELOW

t

ACH

CLOCK

DATA IN

Timing Requirements

THREE-WIRE INTERFACE

CLOCK

WORD "N" WORD "N + 1"

1

DATA IN

LATCH

DATA OUT

CLOCK

DATA IN

LATCH

DATA OUT

0 1 1 0 0 1

B15

B14

(MSB)

B13

t

B12

CL

t

DS

0 0 1 1 1 0 0 1 1 1

B9B8B7B6B5B4B3B2B1

B11

B10

WORD "N – 1"

t

CK

t

t

DH

t

DW

(TA = –40ⴗC to +85ⴗC, VCC = +12 V to +32 V)

0 0 1

B0

B15

B14

B13

WORD "N"

01 1

B14

B13

B12

B12

(LSB)

1

B15

CH

t

LD

t

LL

t

t

LH

SD

Figure 2. Timing Diagram for Three-Wire Interface

Table II. Timing Specification for Three-Wire Interface

Parameter Label Limit Units

Data Clock Period t
Data Clock Low Time t
Data Clock High Time t
Data Stable Width t
Data Setup Time t
Data Hold Time t
Latch Delay Time t
Latch Low Time t
Latch High Time t
Serial Output Delay Time t
Clear Pulsewidth t

Three-Wire Interface Fast Edges on Digital Input

With a fast rising edge (<10 ns) on one of the serial inputs
(CLOCK, DATA IN, LATCH) while another input is logic
high, the part may be triggered into a test mode and the con­tents of the data register may become corrupted, which may
result in the output being loaded with an incorrect value. If fast
edges are expected on the digital input lines, it is recommended
that the latch line remain at Logic 0 during serial loading of the
DAC. Similarly, the clock line should remain low during updates
of the DAC via the latch pin. Alternatively, the addition of
small value capacitors on the digital lines will slow down the
edge.

CK

CL

CH

DW

DS

DH

LD

LL

LH

SD

CLR

300 ns min
80 ns min
80 ns min
125 ns min
40 ns min
5 ns min
80 ns min
80 ns min
80 ns min
225 ns max
50 ns min

Figure 3. Timing Diagram for Asynchronous Interface

Table III. Timing Specifications for Asynchronous Interface

Parameter Label Limit Units

Asynchronous Clock Period t
Asynchronous Clock Low Time t
Asynchronous Clock High Time t
Data Stable Width (Critical Clock Edge) t
Data Setup Time (Critical Clock Edge) t
Data Hold Time (Critical Clock Edge) t
Clear Pulsewidth t

ACK

ACL

ACH

ADW

ADS

ADH

CLR

400 ns min
50 ns min
150 ns min
300 ns min
50 ns min
20 ns min
50 ns min

ASYNCHRONOUS INTERFACE

Note in the timing diagram for asynchronous mode operation
each data word is “framed” by a START (0) bit and a STOP
(1) bit. The data timing is with respect to the rising edge of the
CLOCK at the center of each bit cell. Bit cells are 16 clocks
long, and the first cell (the START bit) begins at the first clock
following the leading (falling) edge of the START bit. Thus the
MSB (D15) is sampled 24 clock cycles after the beginning of
the START bit, D14 is sampled at clock number 40, and so on.
During any “dead time” before writing the next word the
DATA IN pin must remain at Logic 1.

The DAC output updates when the STOP bit is received. In
the case of a “framing error” (the STOP bit sampled as a 0) the
AD420 will output a pulse at the DATA OUT pin one clock
period wide during the clock period subsequent to sampling the
STOP bit. The DAC output will not update if a “framing error”
is detected.

REV. F–4–

AD420

PIN DESCRIPTION

Pin # Symbol Function

1, 12, 13, 24 NC No Connection. No internal connections inside device.
2V

LL

3 FAULT DETECT FAULT DETECT, connected to a pull-up resistor, is asserted low when the

4 RANGE SELECT 2 Selects the converter’s output operating range. One output voltage range and three
5 RANGE SELECT 1 output current ranges are available.

6 CLEAR Valid V

7 LATCH In the three-wire interface mode a rising edge parallel loads the serial input register

8 CLOCK Data Clock Input. The clock period is equal to the input data bit rate in the three-

9 DATA IN Serial Data Input.
10 DATA OUT Serial Data Output. In the three-wire interface mode, this output can be used for

11 GND Ground (Common).
14 REF OUT +5 V Reference Output.
15 REF IN Reference Input.
16 OFFSET TRIM Offset Adjust.
17 V
18 I

OUT

OUT

19 BOOST Connect to an external transistor to reduce the power dissipated in the AD420

20 CAP 1 These pins are used for internal filtering. Connect capacitors between each of these
21 CAP 2 pins and V
22 NC No Connection. Do not connect anything to this pin.

23 V

CC

Auxiliary buffered +4.5 V digital logic voltage. This pin is the internal supply voltage
for the digital circuitry and can be used as a termination for pull-up resistors. An
external +5 V power supply can be connected to V
voltage, thus reducing the internal power dissipation. The V

. It will override this buffered

LL

pin should be decoupled

LL

to GND with a 0.1 µF capacitor. See Power Supplies and Decoupling section.

output current does not match the DAC’s programmed value, for example, in
case the current loop is broken.

will unconditionally force the output to go to the minimum of its

IH

programmed range. After CLEAR is removed the DAC output will remain at this
value. The data in the input register is unaffected.

data into the DAC. To use the asynchronous mode connect LATCH through a
current limiting resistor to VCC.

wire interface mode and is 16 times the bit rate in asynchronous mode.

daisy-chaining multiple AD420s. In the asynchronous mode a positive pulse will
indicate a framing error after the stop-bit is received.

Voltage Output.
Current Output.

output transistor, if desired.

. Refer to the description of current output operation.

CC

Power Supply Input. The VCC pin should always be decoupled to GND with a

0.1 µF capacitor. See Power Supplies and Decoupling section.

DEFINITIONS OF SPECIFICATIONS

RESOLUTION: For 16-bit resolution, 1 LSB = 0.0015% of the
FSR. In the 4 mA–20 mA range 1 LSB = 244 nA.

INTEGRAL NONLINEARITY: Analog Devices defines inte­gral nonlinearity as the maximum deviation of the actual, ad­justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS – 1 LSB) for any bit combination. This is
also referred to as relative accuracy.

DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with an LSB change in the digital input code.
Monotonic behavior requires that the differential linearity error be
greater than –1 LSB over the temperature range of interest.

MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.

REV. F –5–

GAIN ERROR: Gain error is a measure of the output error
between an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.

OFFSET ERROR: Offset error is the deviation of the output
current from its ideal value expressed as a percentage of the full­scale output with all 0s loaded in the DAC.

DRIFT: Drift is the change in a parameter (such as gain and
offset) over a specified temperature range. The drift temperature

coefficient, specified in ppm/°C, is calculated by measuring the

parameter at T

, 25°C, and T

MIN

and dividing the change in

MAX

the parameter by the corresponding temperature change.

CURRENT LOOP VOLTAGE COMPLIANCE: The voltage
compliance is the maximum voltage at the I

pin for which

OUT

the output current will be equal to the programmed value.

AD420

AD420

V

CC

4kV 40V

BOOST

I

OUT

V

OUT

FAULT
DETECT

GND

CAP 1

OFFSET

TRIM

V

LL

REF OUT

REF IN

DATA OUT

CLEAR
LATCH
CLOCK

DATA IN

RANGE

SELECT 1

RANGE

SELECT 2

1.25kV

REFERENCE

CLOCK

16-BIT

DAC

DATA I/P

REGISTER

19

20

21

23

14

15

16

17

18

6
7
8
9

10

11

2

3

4

5

SWITCHED

CURRENT
SOURCES

AND

FILTERING

CAP 2

THEORY OF OPERATION

The AD420 uses a sigma-delta (Σ∆) architecture to carry out

the digital-to-analog conversion. This architecture is particularly
well suited for the relatively low bandwidth requirements of the
industrial control environment because of its inherent monoto­nicity at high resolution.

In the AD420 a second order modulator is used to keep com­plexity and die size to a minimum. The single bit stream from
the modulator controls a switched current source that is then
filtered by two, continuous time resistor-capacitor sections. The
capacitors are the only external components that have to be
added for standard current-out operation. The filtered current is
amplified and mirrored to the supply rail so that the application
simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA
current source output with respect to ground. The AD420 is
manufactured on a BiCMOS process that is well suited to imple­menting low voltage digital logic with high performance and
high voltage analog circuitry.

The AD420 can also provide a voltage output instead of a cur­rent loop output if desired. The addition of a single external

amplifier allows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or
±10 V.

The AD420 has a loop fault detection circuit that warns if the
voltage at I

attempts to rise above the compliance range, due

OUT

to an open-loop circuit or insufficient power supply voltage. The
FAULT DETECT is an active low open drain signal so that one
can connect several AD420s together to one pull-up resistor for
global error detection. The pull-up resistor can be tied to the

pin, or an external +5 V logic supply.

V

LL

The I

current is controlled by a PMOS transistor and

OUT

internal amplifier as shown in the functional block diagram. The
internal circuitry that develops the fault output avoids using a
comparator with “window limits” since this would require an
actual output error before the FAULT DETECT output becomes
active. Instead, the signal is generated when the internal ampli­fier in the output stage of the AD420 has less than approximately

one volt remaining of drive capability (when the gate of the
output PMOS transistor nearly reaches ground). Thus the
FAULT DETECT output activates slightly before the compli­ance limit is reached. Since the comparison is made within the
feedback loop of the output amplifier, the output accuracy is
maintained by its open-loop gain, and no output error occurs
before the fault detect output becomes active.

The three-wire digital interface, comprising DATA IN, CLOCK,
and LATCH, interfaces to all commonly used serial micropro­cessors without the addition of any external glue logic. Data is
loaded into an input register under control of CLOCK and is
loaded to the DAC when LATCH is strobed. If a user wants to
minimize the number of galvanic isolators in an intrinsically safe
application, the AD420 can be configured to run in “asynchro­nous” mode. This mode is selected by connecting the LATCH
pin to V

through a current limiting resistor. The data must

CC

then be combined with a start and stop bit to “frame” the infor­mation and trigger the internal LATCH signal.

Figure 4. Functional Block Diagram

REV. F–6–

AD420

6
7
8
9

C1 C2

V

CC

20 21

500V

RSPAN

15 11

GND

RANGE

SELECT1

RANGE

SELECT2

CLEAR
LATCH

CLOCK

DATA IN

AD420

19

4

2

V

LL

I

OUT

(4mA–20mA)

R

LOAD

18

5kV
RSPAN2

V

REF

14

23

16

10kV

RZERO

5

BOOST

0.1mF

0.1mF

APPLICATIONS

CURRENT OUTPUT

The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA–
24 mA output without any active external components. Filter
capacitors C1 and C2 can be any type of low cost ceramic ca­pacitors. To meet the specified full-scale settling time of 3 ms,
low dielectric absorption capacitors (NPO) are required. Suit-

able values are C1 = 0.01 µF and C2 = 0.01 µF.

V

CC

0.1mF

RANGE

SELECT 1

RANGE

SELECT 2

CLEAR
LATCH

CLOCK

DATA IN

V

LL

C1 C2

2

REF
OUT

14

20 21 23

AD420

15

REF
IN

5
4

6
7
8
9

0.1mF

I

(4mA–20mA)

OUT

18

R

LOAD

11

GND

Figure 5. Standard Configuration

DRIVING INDUCTIVE LOADS

When driving inductive or poorly defined loads connect a

0.01 µF capacitor between I

(Pin 18) and GND (Pin 11).

OUT

This will ensure stability of the AD420 with loads beyond
50 mH. There is no maximum capacitance limit. The capacitive
component of the load may cause slower settling, though this
may be masked by the settling time of the AD420. A pro­grammed change in the current may cause a back EMF voltage
on the output that may exceed the compliance of the AD420.
To prevent this voltage from exceeding the supply rails connect
protective diodes between I

and each of VCC and GND.

OUT

Table IV. Buffer Amplifier Configuration

R1 R2 R3 V

OUT

Open Open 0 0 V–5 V
Open R R 0 V–10 V

R Open R ±5 V
R2R2R±10 V

Suitable R = 5 kΩ.

OPTIONAL SPAN AND ZERO TRIM

For those users who would like lower than specified values of
offset and gain error, Figure 7 shows a simple way to trim these
parameters. Care should be taken to select low drift resistors
because they will affect the temperature drift performance of the
DAC.

The adjustment algorithm is iterative. The procedure for trim­ming the AD420 in the 4 mA–20 mA mode can be accom­plished as follows:

STEP I . . . OFFSET ADJUST
Load all zeros. Adjust RZERO for 4.00000 mA of output
current.

STEP II . . . GAIN ADJUST
Load all ones. Adjust RSPAN for 19.99976 mA (FS – 1 LSB) of
output current.

Return to STEP I and iterate until convergence is obtained.

VOLTAGE-MODE OUTPUT

Since the AD420 is a single supply device, it is necessary to add
an external buffer amplifier to the V

pin to obtain a selec-

OUT

tion of bipolar output voltage ranges as shown in Figure 6.

V

C1

21

AD420

15

REF
IN

Figure 6.

CC

C2

23

11

0.1mF0.1mF

GND

V

OUT

17

R1

R2

R3

V

OUT

V

LL

2

RANGE

SELECT 1

RANGE

SELECT 2

CLEAR
LATCH
CLOCK

DATA IN

REV. F –7–

5
4

6
7
8
9

REF
OUT

20

14

Figure 7. Offset and Gain Adjust

Variation of RZERO between REF OUT (5 V) and GND leads
to an offset adjust range from –1.5 mA to 6 mA, (1.5 mA/V
centered at 1 V).

The 5 kΩ RSPAN2 resistor is connected in parallel with the
internal 40 Ω sense resistor, which leads to a gain increase of

+0.8%.

As RSPAN is changed to 500 Ω, the voltage on REF IN is
attenuated by the combination of RSPAN and the 30 kΩ

REF IN input resistance. When added together with RSPAN2
this results in an adjustment range of –0.8% to +0.8%.

AD420

V

CC

GND

LATCH

CLOCK

DATA IN

V

LL

CLOCK

+5V

DATA

ISOLATIONGALVANIC

BARRIER

+24V

11

2

8

23

7

9

100kV

AD420

THREE-WIRE INTERFACE

Figure 8 shows the AD420 connected in the three-wire interface
mode. The AD420 data input block contains a serial input shift
register and a parallel latch. The contents of the shift register are
controlled by the DATA IN signal and the rising edges of the
CLOCK. Upon request of the LATCH pin the DAC and inter­nal latch are updated from the shift register parallel outputs.
The CLOCK should remain inactive while the DAC is updated.
Refer to the timing requirements for three-wire interface.

FAULT DETECT

V

DAC2

DATA

OUT
I

OUT

V

CC

CC

R

LOAD

LATCH
CLOCK

DATA IN

FAULT
DETECT

LATCH
CLOCK
DATA

IN
GND

V

AD420

DAC1

DATA

OUT

I

OUT

V

CC

CC

R

LOAD

10kV

V

LL

FAULT
DETECT

LATCH
CLOCK

DATA
IN

GND

AD420

Figure 8. Three-Wire Interface Using Multiple DACs with
Joint Fault Detect

USING MULTIPLE DACS WITH FAULT DETECT

The three-wire interface mode can utilize the serial DATA
OUT for easy interface to multiple DACs. To program the two
AD420s in Figure 8, 32 data bits are required. The first 16 bits
are clocked into the input shift register of DAC1. The next 16
bits transmitted pass the first 16 bits from the DATA OUT pin
of DAC1 to the input register of DAC2. The input shift regis­ters of the two DACs operate as a single 32-bit shift register,
with the leading 16 bits representing information for DAC2 and
the trailing 16 bits serving for DAC1. Each DAC is then up­dated upon request of the LATCH pin. The daisy-chain can be
extended to as many DACs as required.

ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS

The AD420 connected in ASYNCHRONOUS INTERFACE
mode with optocouplers is shown in Figure 9. Asynchronous
operation minimizes the number of control signals required for
isolation of the digital system from the control loop. The resistor
connected between the LATCH pin and V
activate this mode. For operation with V

is required to

CC

below 18 V use a

CC

50 kΩ pull-up resistor, from 18 V–32 V use 100 kΩ. Asynchro-

nous mode requires that the clock run at 16 times the data bit
rate, therefore to operate at the maximum input data rate of
150 kBPS an input clock of 2.4 MHz is required. The actual
data rate achieved may be limited by the type of optocouplers
chosen. The number of control signals can further be reduced
by creating the appropriate clock signal on the current loop side
of the isolation barrier. If optocouplers with relatively slow rise
and fall times are used, Schmitt triggers may be required on the
digital inputs to prevent erroneous data being presented to the
DAC.

Figure 9. Asynchronous Interface Using Optocouplers

REV. F–8–

MICROPROCESSOR INTERFACE SECTION

DATA IN
CLOCK
LATCH

SO
SK

AD420

MICROWIRE

G1

V

CC

28V

20V

12V

4V

–60 –40 –20 0 20 40 60 80 100

TEMPERATURE –

8C

25V

WHEN USING SOIC PACKAGED DEVICES, AN
EXTERNAL BOOST TRANSISTOR IS REQUIRED
FOR OPERATION IN THIS AREA

AD420 OR AD420-32

32V

AD420-TO-MC68HC11 (SPI BUS) INTERFACE

The AD420 interface to the Motorola SPI (Serial Peripheral
Interface) is shown in Figure 10. The MOSI, SCK, and SS pins
of the HC11 are respectively connected to the DATA IN,
CLOCK, and LATCH pins of the AD420. The majority of the
interfacing issues are done in the software initialization. A typi­cal routine such as the one shown below begins by initializing
the state of the various SPI data and control registers.

INIT LDAA #$2F ;SS = 1; SCK = 0; MOSI = 1

STAA PORTD ;SEND TO SPI OUTPUTS
LDAA #$38 ;SS, SCK, MOSI = OUTPUTS
STAA DDRD ;SEND DATA DIRECTION INFO
LDAA #$50 ;DABL INTRPTS, SPI IS MASTER & ON
STAA SPCR ;CPOL = 0, CPHA = 0, 1MHZ BAUDRATE

NEXTPT LDAA MSBY ;LOAD ACCUM W/UPPER 8 BITS

BSR SENDAT ;JUMP TO DAC OUTPUT ROUTINE
JMP NEXTPT ;INFINITE LOOP

SENDAT LDY #$1000 ;POINT AT ON-CHIP REGISTERS

BCLR $08,Y,$20 ;DRIVE SS (LATCH) LOW
STAA SPDR ;SEND MS-BYTE TO SPI DATA REG

WAIT1 LDAA SPSR ;CHECK STATUS OF SPIE

BPL WAIT1 ;POLL FOR END OF X-MISSION
LDAA LSBY ;GET LOW 8 BITS FROM MEMORY
STAA SPDR ;SEND LS-BYTE TO SPI DATA REG

WAIT2 LDAA SPSR ;CHECK STATUS OF SPIE

BPL WAIT2; ;POLL FOR END OF X-MISSION
BSET $08,Y,$20 ;DRIVE SS HIGH TO LATCH DATA

RTS

The SPI data port is configured to process data in 8-bit bytes.
The most significant data byte (MSBY) is retrieved from
memory and processed by the SENDAT routine. The SS pin is
driven low by indexing into the PORTD data register and clear
Bit 5. The MSBY is then sent to the SPI data register where it is
automatically transferred to the AD420 internal shift resister.
The HC11 generates the requisite eight clock pulses with data
valid on the rising edges. After the MSBY is transmitted, the
least significant byte (LSBY) is loaded from memory and trans­mitted in a similar fashion. To complete the transfer, the
LATCH pin is driven high when loading the complete 16-bit
word into the AD420.

AD420

Figure 11. AD420-to-MICROWIRE Interface

EXTERNAL BOOST FUNCTION

The external boost transistor reduces the power dissipated in
the AD420 by reducing the current flowing in the on-chip
output transistor (dividing it by the current gain of the external
circuit). A discrete NPN transistor with a breakdown voltage,

, greater than 32 V can be used as shown in Figure 12.

BV

CEO

MJD31C

OR

1kV

2N3053

R

LOAD

19

BOOST

AD420

I

OUT

0.022mF

18

Figure 12. External Boost Configuration

The external boost capability has been developed for those users
who may wish to use the AD420, in the SOIC package, at the
extremes of the supply voltage, load current, and temperature
range. The PDIP package (because of its lower thermal resis­tance) will operate safely over the entire specified voltage, tem­perature, and load current ranges without the boost transistor.
The plot in Figure 13 shows the safe operating region for both
package types. The boost transistor can also be used to reduce
the amount of temperature induced drift in the part. This will
minimize the temperature induced drift of the on-chip voltage
reference, which improves drift and linearity.

MOSI

68HC11

SCK

SS

Figure 10. AD420-to-68HC11 (SPI) Interface

AD420-TO-MICROWIRE INTERFACE

The flexible serial interface of the AD420 is also compatible
with the National Semiconductor MICROWIRE interface. The
MICROWIRE interface is used in microcontrollers such as the
COP400 and COP800 series of processors. A generic interface
to use the MICROWIRE interface is shown in Figure 11. The
G1, SK, and SO pins of the MICROWIRE interface are respec­tively connected to the LATCH, CLOCK, and DATA IN pins
of the AD420.

REV. F –9–

DATA IN
CLOCK
LATCH

AD420

Figure 13. Safe Operating Region

AD420

AD420 PROTECTION

TRANSIENT VOLTAGE PROTECTION

The AD420 contains ESD protection diodes which prevent
damage from normal handling. The industrial control environ­ment can, however, subject I/O circuits to much higher tran­sients. In order to protect the AD420 from excessively high
voltage transients such as those specified in IEC 801, external
power diodes and a surge current limiting resistor may be re­quired, as shown in Figure 14. The constraint on the resistor is
that during normal operation the output voltage level at I

OUT

must remain within its voltage compliance limit

(I

× (Rp + R

OUT

LOAD

) ≤ V

– 2.5 V)

CC

and the two protection diodes and resistor must have appropri­ate power ratings.

V

CC

V

AD420

CC

GND

I

OUT

R

P

R

LOAD

Figure 14. Output Transient Voltage Protection

BOARD LAYOUT AND GROUNDING

The AD420 ground pin, designated GND, is the “high quality”
ground reference point for the device. Any external loads on the
REF OUT and V

pins of the AD420 should be returned to

OUT

this reference point. Analog and digital ground currents should
not share a common path. Each signal should have an appropri­ate analog or digital signal return routed close to it. Using this
approach, signal loops enclose a small area, minimizing the
inductive coupling of noise. Wide PC tracks, large gauge wire,
and ground planes are highly recommended to provide low
impedance signal paths.

POWER SUPPLIES AND DECOUPLING

The AD420 supply pins, VCC (Pin 23) and VLL (Pin 2), should

be decoupled to GND with 0.1 µF capacitors to eliminate high

frequency noise that may otherwise get coupled into the analog
system. High frequency ceramic capacitors are recommended.
The decoupling capacitors should be located in close proximity
to the pins and the ground line to have maximum effect. Further
reductions in noise, and improvements in performance, may be
achieved by using a larger value capacitor on the V

LL

pin.

REV. F–10–

0.210

(5.33)

MAX

0.200 (5.05)

0.125 (3.18)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead Plastic DIP

(N-24)

1.275 (32.30)

1.125 (28.60)

24

112

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

13

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.150
(3.81)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

24-Lead Small Outline (SOIC)

(R-24)

AD420

C1870e–0–9/99

0.6141 (15.60)

0.5985 (15.20)

24 13

PIN 1

0.0118 (0.30)

0.0040 (0.10)

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.2992 (7.60)

121

0.1043 (2.65)

0.0926 (2.35)

SEATING
PLANE

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8°
0°

0.0157 (0.40)

x 45°

REV. F –11–

PRINTED IN U.S.A.