Datasheet AD1984 Datasheet (ANALOG DEVICES)

a

High Definition Audio

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FEATURES

FOUR 192 kHz DACs/ADCs

Two independent stereo DAC/ADC pairs Simultaneous record of two stereo channels Simultaneous playback of two stereo channels Independent 8, 11.025, 16, 22.05, 32, 44.1,

48, 88.2, 96, 176.4, and 192 kHz sample rates 16, 20, and 24-bit resolution Selectable stereo mixer on outputs

4-CHANNEL DIGITAL MICROPHONE INTERFACE

Four 192 kHz digital microphone channels Supports multiple microphone types

Two microphones per pin (four total)

One microphone per pin (two total) Low pin count, uses 3 pins Stereo or quad array support 8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, 96,

176.4, and 192 kHz sample rates

16, 20, and 24-bit resolution

SoundMAX

Codec

AD1984

S/PDIF OUTPUT

Supports 44.1, 48, 88.2, 96, 176.4, and 192 kHz sample rates 16, 20, and 24-bit data; PCM, and AC3 formats Digital PCM gain control

DEDICATED AUXILLARY PINS

Stereo CD/auxillary I/O port w/GND sense Stereo auxillary/dock I/O port Mono out pin for internal speakers or telephony

ENHANCED FEATURES

Two stereo headphone amplifiers Microsoft Vista premimum logo for notebook and desktop

96+ dB audio outputs, 90+ dB audio inputs Internal 32-bit arithmetic for greater accuracy Impedance and presence detection on all jacks Three independent microphone bias pins Digital and analog PCBeep Three general-purpose digital I/O (GPIO) pins

3.3 V analog and digital supply voltages Advanced power management modes 48-lead, Pb-free LFCSP_VQ package

®

H D

A U D

I

O

I N T E R F A C E

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DAC1

DAC0

S/PDIF OUT

DIGITAL

MICROPHONE

DIGITAL PCBEEP

ADC0

ADC1

DM_1/2

DM_3/4

DM_CLK

Figure 1. Functional Block Diagram

AD1984

⌺

HP

⌺

PORT A

PORT D

MONO OUT

PORT E

PORT F

PCBEEP

PORT C

PORT B

AD1984

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REVISION HISTORY

1/07–Rev 0: Initial version

Rev. 0 | Page 2 of 20 | January 2007

GENERAL DESCRIPTION

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The AD1984 family of audio codecs and SoundMAX® software provides superior High Definition audio quality that exceeds Vista Premium performance. The AD1984 has four 192 kHz DACs, four 192 kHz ADCs, S/PDIF output, a four-channel digital microphone interface, Digital Beep and analog PCBeep. These features make the AD1984 the right choice for desktop and notebook PCs where performance is key.

The AD1984 is available in a 48-lead, Pb-free frame chip scale package in both reels and trays. See Ordering Guide on Page 20.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the AD1984 SoundMAX codec’s architecture and functionality. Additional information on the AD1984 is available in the AD1984 Programmers Reference Manual. Please contact your local ADI sales representitive for more information. For information on SoundMAX codecs and software see Analog Devices website at

http://www.analog.com/soundMAX.

JACK CONFIGURATIONS

The guideline shown in Table 1 should be used when selecting ports for particular functions. The symbols used in this table are defined as: LI = Line Level Input, LO = Line Level Output, HP = Output capable of driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier.

AD1984

Table 1. Port Assignments

Port HP MIC LO LI

Port A x x Port B x x Port C x x Port D x x Port E x x x Port F x x MONO_OUT x

Rev. 0 | Page 3 of 20 | January 2007

AD1984

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AD1984 SPECIFICATIONS

TEST CONDITIONS

Parameter Test Condition

Tem pe ra tu re Digital Supply Analog Supply MIC_BIAS_IN (via Low-Pass Filter) Sample Rate F Input Signal (Frequency Sine Wave) Amplitude for THD + N Analog Output Pass Band DAC 10 kΩ Output Load: Line Out tests

ADC 0 dB Gain

S

PERFORMANCE

Parameter Min Typ Max Unit

Line Out Drive (10 kΩ loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio Headphone Drive (32 Ω loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to f Signal-to-Noise Ratio Microphone/Line In (Pin to ADC, Mic Boost = 0 dB) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to f Signal-to-Noise Ratio

25°C

3.3 V

5.0 V 48 kHz 1008 Hz –3.0 dB Full Scale 20 Hz to 20 kHz

32 Ω Output Load: Headphone Tests

A-Weighted)

S

A-Weighted)

S

–86 96 96

–80 96 96

–81 90 90

dB dB dB

GENERAL SPECIFICATIONS

Parameter Min Typ Max Unit

DIGITAL DECIMATION AND INTERPOLATION FILTERS

Pass Band – fS (kHz) = 8 ~ 192 0 0.4 f Pass-Band Ripple– f Stop Band – f Stop-Band Rejection – f Group Delay – f Group Delay Variation Over Pass Band 0 μs

ANALOG-TO-DIGITAL CONVERTERS

Resolution 24 Bits Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ±0.2 ±0.5 dB ADC Offset Error ADC Crosstalk Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –85 dB Line_In to Other –100 –80 dB

(kHz) = 8 ~ 192 ±0.005 dB

S

(kHz) = 8 ~ 192 0.6 f

S

1

(kHz) = 8 ~ 192 –100 dB

S

(kHz) = 8 ~ 192 20 1/f

1

S

2

±10 %

±5mV

Hz

S

Rev. 0 | Page 4 of 20 | January 2007

AD1984

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Parameter Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Resolution 24 Bits Gain Error (Full Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 20 kHz) DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)

DAC VOLUMES

Step size (DAC-0, DAC-1) 1.5 dB Output Gain/Attenuation Range –58.5 0 dB Mute Attenuation of 0 dB Fundamental

1

ADC VOLUMES

Step size (ADCSEL-0, ADCSEL-1) 1.5 dB PGA Gain/Attenuation Range –58.5 +22.5 dB

ANALOG MIXER

Signal-to-Noise Ratio Input to Output – Ports B, C, or F, to Port D Output 95 dB Step Size: All Mixer Inputs –1.5 dB Input Gain/Attenuation Range: All Mixer Inputs –34.5 +12.0 dB

ANALOG LINE LEVEL OUTPUTS

Full-Scale Output Voltage: Line out drive enabled 1.0 V rms Ports A, D, E, F, and Mono Out 2.83 V p-p

Output Impedance External Load Impedance Output Capacitance External Load Capacitance 1000 pF

ANALOG HP DRIVE OUTPUTS

Full-Scale Output Voltage: Line Out Drive Enabled 1.0 V rms Ports A and D (when HP Drive is Enabled) 2.83 V p-p

Output Impedance External Load Impedance Output Capacitance External Load Capacitance

ANALOG INPUTS

Input Voltages – Ports B, C, or E

Mic Boost = 0 dB 1

Input Voltages – Microphone Boost

Mic Boost = +10 dB 0.316

Amplifier, Ports B, C, or E

Mic Boost = +20 dB 0.1

Mic Boost = +30 dB 0.032

Input Impedance PCBEEP Ports B, C, E (Mic Boost = 0 dB) Port F Input Capacitance

1

–85 dB –95 dB

±10 %

–80 dB

1

10 kΩ

32 Ω

190 Ω

15 pF

0.5 Ω

15 pF

1000 pF

V rms

2.83

V p-p V rms

0.894

V p-p V rms

0.283

V p-p V rms

0.089

23 150 45

V p-p

kΩ kΩ kΩ

57.5pF

3

Rev. 0 | Page 5 of 20 | January 2007

AD1984

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Parameter Min Typ Max Unit

MICROPHONE BIAS

MIC_BIAS-B, MIC_BIAS-C MIC_BIAS_IN (Pin 33) = +5 V or +3.3 V V V V MIC_BIAS_IN (Pin 33) = +5 V V V MIC_BIAS_IN (Pin 33) = +3.3 V V

Setting = Hi-Z Hi-Z

REF

Setting = 0 V 0 V dc

REF

Setting = 50% 1.65 V dc

REF

Setting = 80% 3.7 V dc

REF

Setting = 100% 3.9 V dc

REF

Setting = 80% 2.86 V dc

REF

V

Setting = 100% 3.0 V dc

REF

MIC_BIAS-E (When enabled as BIAS) V

Output Drive Current V

Setting = Hi-Z Hi-Z V dc

REF

Setting = 0 V 0 V dc

V

REF

V

Setting = 50% 1.65 V dc

REF

Setting = 80% 2.86 V dc

V

REF

V

Setting = 100% 3.0 V dc

REF

Setting = 50%, 80%, or 100% 1.6 mA

REF

GPIO 0

Input Signal High (VIH)DV Input Signal Low ( V Output Signal High (V Output Signal Low (V Input Leakage Current (Signal High) (I Input Leakage Current (Signal Low) (I

)0DV

IL

) I

OH

)I

OL

IL

= –500 μADV

OUT

= +1500 μA0DV

OUT

) –150 nA

IH

)–50μA

× 0.60 DV

IO

× 0.72 DV

IO

× 0.24 V

IO

× 0.10 V

IO

V

GPIO 1 and 2

Input Signal High (VIH)AV Input Signal Low ( V Output Signal High (V Output Signal Low (V Input Leakage Current (Signal High) (I Input Leakage Current (Signal Low) (I

)0AV

IL

)I

OH

)I

OL

IL

= –500 μAAV

OUT

= +1500 μA0AV

OUT

) –150 nA

IH

)–50μA

× 0.60 AV

DD

× 0.72 AV

DD

× 0.24 V

DD

× 0.10 V

DD

V

DM Clock

Output Signal High (VOH)I Output Signal Low (V

)I

OL

= –500 μAAV

OUT

= +1500 μA0AV

OUT

× 0.72 AV

DD

× 0.10 V

DD

V

DM 1/2 and 3/4

Input Signal High (V Input Signal Low ( V

)AV

IH

)0AV

IL

Input Leakage Current (Signal High) (I Input Leakage Current (Signal Low) (I

) –150 nA

IH

)–50nA

IL

× 0.60 AV

DD

× 0.24 V

DD

V

POWER SUPPLY

Analog (AV Power Supply Range Power Dissipation Supply Current Digital (DV

Power Supply Range Power Dissipation Supply Current Digital I/O (DV Power Supply Range Power Dissipation Supply Current Power Supply Rejection (reference to f

1

Guaranteed but not tested.

2

Measurements reflect main ADC.

3

RMS values assume sine wave input.

) 3.3 V ±5%

DD

) 3.3 V ±10%

DD

) 3.3 V ±10%

IO

3.13 3.30

3.46 V 99 31

2.97 3.30

3.63 V 162 58

2.97 3.30

3.63 V

3.96

1.2

100 mV p-p Signal @ 1 kHz)1 80 dB

S

mW mA

Rev. 0 | Page 6 of 20 | January 2007

HD–AUDIO LINK SPECIFICATION

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High-definition audio signals comply with the High-definition Audio specification. Please refer to these specifications at:

http://www.intel.com/standards/hdaudio/

POWER DOWN STATES

AD1984

Parameter ID

Function node in D0, all nodes active 58 31 mA Function node in D3 Codec in RESET Individual block power savings DAC pair powered down saves (each) ADC pair powered down saves (each) Mixer power control (and associated amps) saves DM_FLT pair powered down saves (each) DM_CLK powered down saves MIC_BIAS powered down saves

1

Function node D3 state powers down all nodes except for the V

background functions such as jack presence detection or analog pass-through are required. Mixer should be kept active when analog pass-through is required. MIC_BIAS can be disabled if microphones are not in use in the power-down state.

2

Test conditions: 30 pF load, 2.0 MHz frequency, 3.3 V A

3

Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the Hi-Z state. The

0 Ω and Hi-Z states remain unaffected by the MIC_BIAS power state.

1

2

3

, Mixer and MIC_BIAS nodes which have independent power controls. V

REF

VDD.

Typ IA

VDD

21 2 mA 33mA

6 5 0 5 0 0

Typ Unit

VDD

5 3 2 0 1

0.5

mA mA mA mA mA mA

should be kept active when

REF

Rev. 0 | Page 7 of 20 | January 2007

AD1984

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ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed below may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Power Supplies Min Max Unit

Digital (DV Digital I/O (DV Analog (AV Input Current (Except Supply Pins) ±10.0 mA Analog Input Voltage (Signal Pins) –0.30 AVDD + 0.3 V Digital Input Voltage (Signal Pins) –0.30 DV Ambient Temperature (Operating) 0 +70 °C Storage Temperature –65 +150 °C

) –0.30 +3.65 V

DD

) –0.30 +3.65 V

IO

) –0.30 +3.65 V

DD

+ 0.3 V

IO

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be take to avoid performance degradation or loss of functionality.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating

T

= T

AMB

T

CASE

PD = Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)

θ

CA

θ

= Thermal Resistance (Junction-to-Ambient)

JA

θ

= Thermal Resistance (Junction-to-Case)

JC

All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7.

Table 2. Thermal Resistance

Package θ

LFCSP_VQ 47 15 32 °C/W

– (PD × θCA)

CASE

= Case Temperature in °C

JA

θ

JC

θ

CA

Unit

Rev. 0 | Page 8 of 20 | January 2007

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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AD1984

DV

CORE

DM_1/2

DV

DM_3/4

SDATA_OUT

BIT_CLK

DV

SDATA_IN

DV

SYNC

RESET

PCBEEP

T C E N

D P

T

A

U

E

/

O

0

-

_

IF

O

I

D

P

G

S

1

2

3

I/O

4

5

6

7

SS

8

9

DD

10

11

12

L

B

_

E

C

T

R S

R

/

O

A

P

_ E S N E S

N O C

O

K

N

L C

=

_

C

M

N

D

L

R

_

F

E

-

T

R

O

P

C

E

N

O

C

O

N

=

= C

N

44 434748 4546 373839404142

S S

C

V

N

A

AD1984JCPZ

TOP VIEW

(NotTo Scale)

)

T

R _ F

T R

O P

F

C

T

E

R

N

O

N

P

O

(

C

D

O

N

G _

=

D

C

N

T

T C E N N O C

R _ A

T R

O P

T C E N N O C

O N

= C

N

L _

O

A

N

T

=

R

C

O

N

P

L

R

_

B

-

T

R

O

P

T C E N N O C

O N =

D D

C

V

N

A

PORT-D_R

36

PORT-D_L

35

SENSE_B/SRC_A

34

MIC_BIAS_IN

33

MONO_OUT

32

GPIO_1/MIC_BIAS-E

31

30

GPIO_2

29

MIC_BIAS-C

28

MIC_BIAS-B

27

VREF_FILT

26

AV

SS

25

AV

DD

242313 14 15 16 17 18 19 20 21 22

L

R

_

C

-

T

R

O

P

Figure 2. AD1984 48-Lead Package and Pinout

Rev. 0 | Page 9 of 20 | January 2007

AD1984

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Table 3. AD1984 Pin Descriptions

Mnemonic Pin No. I/O Description

DIGITAL INTERFACE SDATA_OUT

BIT_CLK SDATA_IN SYNC RESET DIGITAL I/O DM_1/DM_2

DM_3/DM_4

DM_CLK GPIO_2

GPIO_1/MIC_BIAS-E

GPIO_0/EAPD

S/PDIF_OUT JACK SENSE AND EAPD SENSE_A/SRC_B SENSE_B/SRC_A ANALOG I/O PCBEEP Port E_L Port E_R Port F_L Port F_R CD_GND

Port B_L Port B_R Port C_L Port C_R MONO_OUT

Port D_L Port D_R Port A_L Port A_R

The symbols used in this table are defined as: I = Input, O = Output, LI = Line Level Input, LO = Line Level Output, HP = Output capable of driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier.

5

6 8 10 11

2

4

46 30

31

47

48

13 34

12 14 15 16 17 19

21 22

23 24 32 35 36 39 41

I

I I/O I I

I

O I/O

I/O

O

I/O I/O

LI LI, MIC, LO

LI, MIC, LO LI, LO LI, LO I

LI, MIC LI, MIC LI, MIC LI, MIC LO HP, LO HP, LO HP, LO HP, LO

Link Serial Data Output. AD1984 input stream. Clocked on both edges of the BIT_CLK. Link Bit Clock. 24.000 MHz serial data clock . Link Serial Data Input. AD1984 output stream clocked only on one edge of BIT_CLK. Link Frame Sync. Link Reset. AD1984 master hardware reset.

Digital microphone 1 and 2 inputs (for bi-phase microphones), or digital microphone 1 input (for single-phase microphones). Digital microphone 3 and 4 inputs (for bi-phase microphones), or digital microphone 2 input (for single-phase microphones). Clock to drive external digital microphones. General Purpose Input/Output Pins. Digital signals used to control or sense external circuitry. General Purpose I/O/Microphone Bias for Port E. Capable of Hi-Z, 1.65 V, and 2.86 V. Pin 31 shares functionality between GPIO_1 (default) and MIC_BIAS_E. These functions are mutually exclusive and the GPIO function takes priority over the MIC_BIAS function. When the GPIO enable bit is 0, Pin 31 functions as a MIC_BIAS pin associated with Port E. EAPD/General Purpose Input/Output pin. Pin 47 shares functionality between GPIO_0 and EAPD. These functions are mutually exclusive and the EAPD function takes priority over the GPIO function. By default, the pin is in a Hi-Z state. External resistors should be used to insure the proper circuit state when this pin is in Hi-Z. S/PDIF_OUT – Supports S/PDIF output.

Jack Sense A-D Input/Sense B drive. Jack Sense E-F Input/Sense A drive.

Monaural Input from system for Analog PCBeep. Auxiliary Input/Output Left Channel.

Auxiliary Input/Output Right Channel. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. CD-Audio-Analog-Ground-Reference. Must be connected to AGND via a 0.1 μF capacitor if not in use as CD_GND. MUST always be ac coupled. Front Panel Stereo MIC/Line-In. Front Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone. Rear Panel Headphone/Line-Out. Rear Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. Front Panel Headphone/Line-Out.

Rev. 0 | Page 10 of 20 | January 2007

AD1984

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Table 3. AD1984 Pin Descriptions (Continued)

Mnemonic Pin No. I/O Description

FILTER/REFERENCE V

_FILT

REF

MIC_BIAS-B MIC_BIAS-C

DV

CORE

POWER AND GROUND DVIO 3.3V 3 I Link Digital I/O Voltage Reference. 3.3 V DV

SS

3.3 V 9 I Digital supply voltage 3.3 V . This is regulated down to DV

DV

DD

AV

3.3 V 25, 38 I CAUTION: DO NOT APPLY 5 V TO THESE PINS!

DD

MIC_BIAS_IN

5.0 V or 3.3 V

AV

SS

The symbols used in this table are defined as: I = Input, O = Output, LI = Line Level Input, LO = Line Level Output, HP = Output capable of driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier.

27 28 29

1 O CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!

7 I Digital supply return (ground).

33 I Source power for microphone bias boost circuitry.

26, 42 I Analog supply return (ground). AVSS should be connected to DVSS using a conductive

O O

O

Voltage Reference Filter. Switchable Microphone Bias. For use with Port B (Pins 21, 22). Switchable Microphone Bias. For use with Port C (Pins 23, 24).

Both MIC bias pins are capable of Hi-Z, 0 V, 1.65 V, 3.7 V, and 3.9 V (with 5.0 V on Pin 33), Hi-Z, 0 V, 1.65 V, 2.86 V, and 3.0 V (with 3.3 V on Pin 33).

Filter connection for internal core voltage regulator. This pin must be connected to filter caps: 10 μF, 1.0 μF, a nd 0. 1 μF connected in parallel between Pin 1 and

(Pin 7).

D

VSS

on Pin 1 to supply the

internal digital core internal to the AD1984.

Analog supply voltage 3.3 V ONLY. Note: AV

audio performance.

Connect this pin to 5.0 V via a low-pass filter. When connected this way the AD1984 is capable of providing +3.9 V as a mic bias to all of the mic bias pins (except on Pin 31).

If 5 V is not available, connect this pin to +3.3 V (AV The AD1984 produces a mic bias voltage relative to the AV (typically 3.0 V @ AV

trace under, or close to, the AD1984.

supplies should be well regulated and filtered as supply noise degrades

DD

= 3.3 V).

DD

CORE

) via a low-pass filter.

DD

supply

DD

Rev. 0 | Page 11 of 20 | January 2007

AD1984

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DIGITAL MICROPHONE INTERFACE TIMING SPECIFICATIONS

The digital microphone interface can support one, two, or four digital microphones using two or three codec pins. Both uniplex (one mic per data pin) and multiplex (two mics sharing the

in Figure 3, Figure 4, Figure 6, and Figure 7. The interface can generate a microphone clock at 1.5 MHz, 2.0 MHz, or 3.0 MHz to suit quality and power requirements.

same data pin) are supported. These configurations are shown

Table 4. Digital Microphone Timing Parameters

Parameter Min Typ Max Unit

Timing Requirements

t

0

t

0

t

0

t

1

t

2

t

3

t

4

t

5

t

6

MIC 1

DM_CLK (1.5 MHz) Period Duty Cycle DM_CLK (2.0 MHz) Period Duty Cycle DM_CLK (3.0 MHz) Period Duty Cycle

667 60/40 500 50/50 333 50/50

ns % ns % ns

% DM_CLK Rise Time 5ns DM_CLK Fall Time 5ns DM_CLK Edge to Data Valid 40 ns Data Setup to DM_CLK Edge 100 ns Data Hold from DM_CLK Edge 5 ns DM_CLK Edge to Data Hi-Z 7 ns

ON CHIPOFF-CHIP

LEFT

RIGHT

DM_1/2

DQ

>

DQ

>

MUX

GAM

NID:05

DIGITAL F ILTER

DM_3/4

DM_CLK

DQ

>

DQ

>

DM-CLK

GENERATOR

SWAPL/R

Figure 3. Uniplex Digital Microphone, Mono Interface

Rev. 0 | Page 12 of 20 | January 2007

GAM

GAM = GAIN, ATTENUATE, MUTE

NID:06

DIGITAL FILTER

LEFT

HD-AUDIO INTERFACE

RIGHT

MIC 1

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MIC 2

DM_1/2

DM_3/4

DM_CLK

ON CHIPOFF-CHIP

SWAPL/R

DQ

>

DQ

>

DQ

>

DQ

>

MUX

DM-CLK

GENERATOR

GAM

DIGITAL F ILTER

GAM

DIGITAL F ILTER

GAM

GAM = GAIN, ATTENUATE, MUTE

AD1984

LEFT

NID:05

RIGHT

LEFT

HD-AUDIO INTERFACE

NID:06

RIGHT

DM_CLK

DM_1/2 DM_3/4

Figure 4. Uniplex Microphone, Stereo Interface

t

0

t

2

t

1

t

4

t

3

DATA VALID

Figure 5. Uniplex Microphone Timing

Rev. 0 | Page 13 of 20 | January 2007

AD1984

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MIC 1

MIC 2

DM_1/2

ON CHIPOFF-CHIP

DQ

>

DQ

>

MUX

GAM

NID:05

DIGITAL FILTER

LEFT

RIGHT

MIC 1

MIC 2

MIC 3

MIC 4

DM_3/4

DM_CLK

DM_1/2

DM_3/4

DQ

>

DQ

>

GAM = GAIN, ATTENUATE, MUTE

DM-CLK

GENERATOR

SWAPL/R

Figure 6. Multiplex Digital Microphone, Stereo Interface

ON CHIPOFF-CHIP

DQ

>

DQ

>

Q

D

>

DQ

MUX

GAM

NID:06

DIGITAL FILTER

NID:05

DIGITAL F ILTER

NID:06

DIGITAL FILTER

LEFT

HD-AUDIO INTERFACE

RIGHT

LEFT

RIGHT

LEFT

HD-AUDIO INTERFACE

RIGHT

DM_CLK

>

GENERATOR

SWAPL/R

GAM = GAIN, ATTENUATE, MUTE

DM-CLK

Figure 7. Multiplex Digital Microphone, Quad Interface

Rev. 0 | Page 14 of 20 | January 2007

DM_CLK

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DM_1/2

DM_3/4

AD1984

t

0

t

1

t

3

t

5

4

MIC 1

DATA VALID

6

MIC 1

DATA VALID

t

3

t

5

4

MIC 2

DATA VALID

t

6

Figure 8. Multiplex Microphone Timing

t

2

Rev. 0 | Page 15 of 20 | January 2007

AD1984

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HD AUDIO WIDGETS

Table 5. HD Audio Widgets

Node ID Name Type ID Type Description

00 ROOT x Root Device identification 01 FUNCTION x Function Designates this device as an audio CODEC 02 S/PDIF DAC 0 Audio Output S/PDIF digital stream output interface 03 DAC_0 0 Audio Output Stereo headphone channel digital/audio converters 04 DAC_1 0 Audio Output Stereo front channel digital/audio converters 05 Dig Mic Conv 1/2 1 Audio Input Digital microphone Channel 1, 2 converters 06 Dig Mic Conv 3/4 1 Audio Input Digital microphone Channel 3, 4 converters 07 Port A Mixer 2 Audio Mixer Mixes the of DAC_(0, 1) and mixer output amps to drive Port A 08 ADC_0 1 Audio Input Stereo record Channel 0 audio/digital converters 09 ADC_1 1 Audio Input Stereo record Channel 1 audio/digital converters 0A Port D Mixer 2 Audio Mixer Mixes the DAC_1 and mixer output amps to drive Port D 0B Port F Mixer 2 Audio Mixer Mixes the DAC_(0, 1) and mixer output amps to drive Port F 0C ADC Selector 0 3 Audio Selector Selects and amplifies/attenuates the input to ADC_0 0D ADC Selector 1 3 Audio Selector Selects and amplifies/attenuates the input to ADC_1 0E Mono Out Selector 3 Audio Selector Selects the mono out DAC_(0, 1) 0F Port F Out Selector 3 Audio Selector Selects the Port F DAC_(0, 1) 10 Digital Beep 7 Beep Generator Internal digital PCBeep signal 11 Port A (Headphone) 4 Pin Complex Headphone jack pins 12 Port D (Line Out) 4 Pin Complex Line out jack pins 13 Mono Out 4 Pin Complex Monaural output pin (internal speakers or telephony system) 14 Port B (Mic In) 4 Pin Complex Microphone in jack pins 15 Port C (Line In) 4 Pin Complex Line in jack pins 16 Port F (Aux In/Out) 4 Pin Complex Auxiliary I/O pins 17 Dig Mic 1/2 Pin 4 Pin Complex Digital microphone 1, 2 input pin 18 Dig Mic 3/4 Pin 4 Pin Complex Digital microphone 3, 4 input pin 19 Mixer Power Down 5 Power Widget Powers down the analog mixer and associated amps 1A Analog PCBeep 4 Pin Complex External analog PCBeep signal input 1B S/PDIF Out Pin 4 Pin Complex S/PDIF output pin 1C Port E (Dock I/O) 4 Pin Complex Analog dock I/O pins 1D V 1E Mono Out Mixer 2 Audio Mixer Mixes the DAC_(0, 1) and mixer output amps to drive mono out 1F Stereo Mix-Down 2 Audio Mixer Mixes the stereo L/R channels to drive mono output 20 Analog Mixer 2 Audio Mixer Mixes individually gainable analog inputs 21 Mixer Output Atten 3 Audio Selector Attenuates the mixer output to drive the port mixers 22 Port A Out Selector 3 Audio Selector Selects the Port A DAC_(0, 1) 23 Port E Out Selector 3 Audio Selector Selects the Port E DAC_(0, 1) 24 Port E Mixer 2 Audio Mixer Mixes the DAC_(0, 1) and mixer output amps to drive Port E 25 Port E Mic Boost 3 Audio Selector 0 dB, 10 dB, 20 dB, or 30 dB gain boost for Port E 26 BIAS Power Down F Vendor Defined Powers down the internal MIC_BIAS_FILT and all MIC_BIAS pins

Power Down F Vendor Defined Powers down the internal and external V

REF

circuitry

REF

Rev. 0 | Page 16 of 20 | January 2007

AD1984 HD AUDIO PARAMETER

www.BDTIC.com/ADI

Table 6. Root and Function Node Parameters

AD1984

Sub Node

Vendor ID

Node ID Name Type

00 ROOT Root 11D41984 00100400 00010001 01 FUNCTION Function 00020025 00000001 00010C0C 40000003

Table 7. SubSystem ID

01 FUNCTION BFD4 00 00

1

The SSID value is set on codec power-up only. SSID is not reset by link

or soft reset in order to preserve modifications by BIOS control.

Table 8. Widget Parameters

Widget

Node

Capabilities

ID

09

01 000004C0 000E07FF 00000001 80000000 00000009 00052727 02 00030311 000E07E0 00000005 00000003 03 00000405 000E07FF 00000001 00000000 00000009 00052727 04 00000405 000E07FF 00000001 00000000 00000009 00052727 05 0010050B 000E07FF 00000001 80053627 00000001 00000009 06 0010050B 000E07FF 00000001 80053627 00000001 00000009 07 00200103 80000000 00000002 08 00100501 000E07FF 00000001 00000001 00000009 09 00100501 000E07FF 00000001 00000001 00000009 0A 00200103 80000000 00000002 0B 00200103 80000000 00000002 0C 0030010D 00000004 80053627 0D 0030010D 00000004 80053627 0E 00300101 00000002 0F 00300101 00000002 10 0070000C 00000000 800B0F0F 11 0040018D 0000001F 00000001 80000000 12 0040058D 0001001F 00000001 00000009 80000000 13 0040050C 00010010 00000001 00000009 80051F1F 14 0040008B 00003727 00270300 00000000 15 0040008B 00003727 00270300 00000000 16 0040018D 00000037 00000001 80000000 17 00400001 00000020 00000000 18 00400001 00000020 00000000 19 00500500 00000002 00000009 1A 00400000 00000020 00000000 1B 0040030D 00000010 00000001 80052727 1C 0040018D 00003737 00000001 80000000 1D 00F00100 0000000A 1E 00200103 80000000 00000002 1F 00200100 00000001 20 0020010B 80051F17 00000004 21 0030010D 00000001 80051F1F 22 00300101 00000002

1

31:16 15:8 7:0 SSID SKU Asm ID

PCM Size, Rate 0A

00

Stream Formats 0B

Revision ID 02

Pin Capabilities 0C

Count 04

Input Amp Capabilities 0D

Func. Group Typ e 05

Con. List Length 0E

Audio F.G. Caps 08

Power States 0F

GPIO Caps 11

Output Amp Capabilities 12

Rev. 0 | Page 17 of 20 | January 2007

AD1984

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Table 8. Widget Parameters (Continued)

Widget

Node

Capabilities

ID

09

23 00300101 00000002 24 00200103 80000000 00000002 25 0030010D 00000001 00270300 26 00F00100 00000003

Table 9. Connection List

Node ID

[0–3] [4–7] [8–11] INID INID INID INID INID INID INID INIDINID INID

02 00090801 01 08 I 09 03 04 05 00000017 17 06 00000018 18 07 00002122 03 21 08 0000000C 0C 09 0000000D 0D 0A 00002104 04 21 0B 0000210F 0F 21 0C 25209614 1 14 16 20 25 0D 25209614 1 14 16 20 25 0E 00000403 03 04 0F 00000403 03 04 10 11 00000007 07 12 0000000A 0A 13 0000001F 1F 14 15 16 0000000B 0B 17 18 19 00002120 20 21 1A 1B 00000002 02 1C 00000024 24 1D 8F0A1907 96111C1A 0000A61E 07 19 0A 1 0F 1A 1C 11 1 16 1E 1 26 1E 0000210E 0E 21 1F 0000001E 1E 20 251A9614 1 14 16 1A 25 21 00000020 20 22 00000403 03 04 23 00000403 03 04 24 00002123 23 21 25 0000001C 26 26 001C1514 14 15

PCM Size, Rate 0A

Connections 0123456789

Stream Formats 0B

Pin Capabilities 0C

Input Amp Capabilities 0D

Con. List Length 0E

Power States 0F

Output Amp Capabilities 12

Rev. 0 | Page 18 of 20 | January 2007

AD1984

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In Table 10, default configuration values are set on codec power-up only. Default configuration values are not reset by link or soft reset to preserve modifications by BIOS control. Bits 11:9 are reserved.

Table 10. Default Configuration Bytes

31:30 29:28 27:24 23:20 19:16 15:12 8 7:4 3:0

Location

Connectivity

11 Port A 0321401F Jack External Left HP Out 1/8" Jack Green 0 1 F 12 Port D 90130110 Fixed Internal N/A Speaker ATAPI Unknown 1 1 0 13 Mono Out 901301F0 Fixed Internal N/A Speaker ATAPI Unknown 1 F 0 14 Port B 03A190F0 Jack External Left Mic In 1/8" Jack Pink 0 F 0 15 Port C 96A30120 Fixed Internal Bottom Mic In ATAPI Unknown 1 2 0 16 Port F 99330121 Fixed Internal Special 3 CD ATAPI Unknown 1 2 1 17 Dig Mic 1/2 Pin 95A601F0 Fixed Internal Top Mic In Other Digital Unknown 1 F 0 18 Dig Mic 3/4 Pin 95A601F0 Fixed Internal Top Mic In Other Digital Unknown 1 F 0 1A Analog PCBeep 90F301F0 Fixed Internal N/A other ATAPI Unknown 1 F 0 1B S/PDIF Out Pin 014511F0 Jack External Rear SPDIF Out Optical Black 1 F 0 1C Port E 21A1902E Jack Separate Rear Mic In 1/8" Jack Pink 0 2 E

Def. Device Conn Type Color Def Assn. Seq.ID Name Value Chasis Position JD OR

Rev. 0 | Page 19 of 20 | January 2007

AD1984

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OUTLINE DIMENSIONS

Dimensions are shown in millimeters.

ORDERING GUIDE

1.00

0.85

0.80

12° MAX

SEATING PLANE

BSC SQ

PIN 1 INDICATOR

VIEW

7.00

0.60 MAX

TOP

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

6.75

BSC SQ

0.20 REF

0.50

0.40

0.30

0.05 MAX

0.02 NOM COPLANARITY

0.08

37

36

25

24

0.60 MAX

EXPOSED

PAD

(BOTTOM VIEW)

5.50 REF

Figure 9. 48-Lead, Pb-Free, Frame Chip Scale Package [LFCSP_VQ]

7 mm x 7 mm Body, Very Thin Quad (CP-48-1)

0.30

0.23

0.18 PIN 1

48

13

INDICATOR

1

5.25

5.10 SQ

4.95

12

0.25 MIN

Model Temperature Range Package Description Package Option

AD1984JCPZ AD1984JCPZ-REEL

1

Z = Pb-free part.

1

0°C to 70°C 48-Lead LFCSP_VQ CP-48-1 0°C to 70°C 48-Lead LFCSP_VQ CP-48-1

D06535-0-1/07(0)

Rev. 0 | Page 20 of 20 | January 2007

Datasheet AD1984 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

ADDITIONAL INFORMATION

JACK CONFIGURATIONS

AD1984 SPECIFICATIONS

TEST CONDITIONS

PERFORMANCE

GENERAL SPECIFICATIONS

POWER DOWN STATES

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

ENVIRONMENTAL CONDITIONS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DIGITAL MICROPHONE INTERFACE TIMING SPECIFICATIONS

HD AUDIO WIDGETS

AD1984 HD AUDIO PARAMETER

OUTLINE DIMENSIONS

ORDERING GUIDE