Page 1
4 ADC with PLL,
www.BDTIC.com/ADI
FEATURES
Phase-locked loop generated or direct master clock
Low EMI design
107 dB dynamic range and SNR
−94 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24 bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Log volume control with autoramp function
SPI®-controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I
Master and slave modes up to 16-channel input/output
Available in a 48-lead LQFP
APPLICATIONS
Automotive audio systems
Home Theater Systems
Set-top boxes
Digital audio effects processors
2
S, and TDM modes
192 kHz, 24-Bit Codec
AD1974
GENERAL DESCRIPTION
The AD1974 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with differential
inputs using the Analog Devices, Inc. patented multibit sigmadelta (Σ-Δ) architecture. An SPI port is included, allowing a
microcontroller to adjust volume and many other parameters.
The AD1974 operates from 3.3 V digital and analog supplies.
The AD1974 is available in a single-ended output 48-lead LQFP.
The AD1974 is designed for low EMI. This consideration is
pparent in both the system and circuit design architectures.
a
By using the on-board phase-locked loop (PLL) to derive the
master clock from the LR clock or from an external crystal,
the AD1974 eliminates the need for a separate high frequency
master clock and can also be used with a suppressed bit clock.
The ADCs are designed using the latest continuous time architectures from Analog Devices to further minimize EMI. By
using 3.3 V supplies, power consumption is minimized, further
reducing emissions.
FUNCTIONAL BLOCK DIAGRAM
AD1974
ADC
ANALOG
AUDIO
INPUTS
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADC
ADC
ADC
PRECISION
VOLTAGE
REFERENCE
96kHz/192kHz
QUAD
DEC
FILTER
48kHz/
Figure 1.
DIGITAL AUDIO
INPUT/OUTPUT
SERIAL DATA PORT
SDATA
OUT
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL )
CONTROL PO RT
SPI
12.48MHz
CONTROL DAT A
INPUT/OUTPUT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
06614-001
Page 2
AD1974
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Test Conditions............................................................................. 3
Analog Performance Specifications........................................... 3
Crystal Oscillator Specifications................................................. 4
Digital Input/Output Specifications........................................... 4
Power Supply Specifications........................................................ 5
Digital Filters................................................................................. 5
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 11
Analog-to-Digital Converters (ADCs).................................... 11
Clock Signals............................................................................... 11
Reset and Power-Down............................................................. 11
Serial Control Port ..................................................................... 12
Power Supply and Voltage Reference....................................... 12
Serial Data Ports—Data Format............................................... 12
TDM Modes................................................................................ 13
Daisy-Chain Mode..................................................................... 15
Control Registers............................................................................ 18
PLL and Clock Control Registers............................................. 18
AUXPORT Control Registers................................................... 19
ADC Control Registers.............................................................. 20
Additional Modes....................................................................... 22
Application Circuits ....................................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide............................................................................... 24
REVISION HISTORY
4/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
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AD1974
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SPECIFICATIONS
TEST CONDITIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Supply Voltages (AVDD, DVDD) 3.3 V
Temp e r a t ure Ra n ge
1
As specified in Ta b le 1 and Tabl e 2
Master Clock 12.288 MHz (48 kHz f
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 24 bits
Load Capacitance (Digital Output) 20 pF
Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply
Input Voltage High 2.0 V
Input Voltage Low 0.8 V
1
Functionally guaranteed at −40°C to +125°C case temperature.
, 256 × fS mode)
S
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter Conditions Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution All ADCs 24 Bits
Full-Scale Input Voltage (Differential) 1.9 V rms
Dynamic Range 20 Hz to 20 kHz, −60 dB input
No Filter (RMS) 98 102 dB
With A-Weighted Filter (RMS) 100 105 dB
Total Harmonic Distortion + Noise (THD + N) −1 dBFS −96 −87 dB
Gain Error −10 +10 %
Interchannel Gain Mismatch −0.25 +0.25 dB
Offset Error −10 0 +10 mV
Gain Drift 100 ppm/°C
Interchannel Isolation −110 dB
CMRR 100 mV rms, 1 kHz 55 dB
100 mV rms, 20 kHz 55 dB
Input Resistance 14 kΩ
Input Capacitance 10 pF
Input Common-Mode Bias Voltage 1.5 V
REFERENCE
Internal Reference Voltage FILTR pin 1.50 V
External Reference Voltage FILTR pin 1.32 1.50 1.68 V
Common-Mode Reference Output CM pin 1.50 V
Rev. 0 | Page 3 of 24
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AD1974
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Specifications measured at 130°C (case).
Table 2.
Parameter Conditions Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution All ADCs 24 Bits
Full-Scale Input Voltage (Differential) 1.9 V rms
Dynamic Range 20 Hz to 20 kHz, −60 dB input
No Filter (RMS) 95 102 dB
With A-Weighted Filter (RMS) 97 105 dB
Total Harmonic Distortion + Noise (THD + N) −1 dBFS −96 −87 dB
Gain Error −10 +10 %
Interchannel Gain Mismatch −0.25 +0.25 dB
Offset Error −10 0 +10 mV
REFERENCE
Internal Reference Voltage FILTR pin 1.50 V
External Reference Voltage FILTR pin 1.32 1.50 1.68 V
Common-Mode Reference Output CM pin 1.50 V
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter Min Typ Max Unit
Transconductance 3.5 Mmhos
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.
Table 4.
Parameter Conditions/Comments Min Typ Max Unit
Input Voltage High (VIH) 2.0 V
Input Voltage High (VIH) MCLKI pin 2.2 V
Input Voltage Low (VIL) 0.8 V
Input Leakage IIH @ VIH = 2.4 V 10 μA
I
High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V
Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V
Input Capacitance 5 pF
@ VIL = 0.8 V 10 μA
IL
Rev. 0 | Page 4 of 24
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AD1974
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POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter Conditions/Comments Min Typ Max Unit
SUPPLIES
Voltage
DVDD 3.0 3.3 3.6 V
AVDD 3.0 3.3 3.6 V
Digital Current MCLK = 256 f
S
Normal Operation fS = 48 kHz 56 mA
f
f
= 96 kHz 65 mA
S
= 192 kHz 95 mA
S
Power-Down fS = 48 kHz to 192 kHz 2.0 mA
Analog Current
Normal Operation 74 mA
Power-Down 23 mA
DISSIPATION
Operation MCLK = 256 fS, 48 kHz
All Supplies 429 mW
Digital Supply 185 mW
Analog Supply 244 mW
Power-Down, All Supplies 83 mW
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB
20 kHz, 200 mV p-p 50 dB
DIGITAL FILTERS
Table 6.
Parameter Mode Factor Min Typ Max Unit
ADC DECIMATION FILTER
Pass Band 0.4375 f
All modes @ 48 kHz
S
21 kHz
Pass-Band Ripple ±0.015 dB
Transition Band 0.5 f
S
Stop Band 0.5625 f
S
24 kHz
27 kHz
Stop-Band Attenuation 79 dB
Group Delay 22.9844 f
S
479 μs
TIMING SPECIFICATIONS
−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK)
AND RESET
t
MH
t
MH
f
MCLK
f
MCLK
t
PDR
t
PDRR
MCLK duty cycle ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, 768 fS 40 60 %
ADC clock source = direct MCLK @ 512 f
(bypass
S
40 60 %
on-chip PLL)
MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz
Direct 512 fS mode 27.6 MHz
Low 15 ns
Recovery Reset to active output 4096 t
MCLK
Rev. 0 | Page 5 of 24
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AD1974
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Parameter Condition Comments Min Max Unit
PLL
Lock Time MCLK and LRCLK input 10 ms
256 fS VCO Clock 40 60 %
Output Duty Cycle
MCLK_O Pin
SPI PORT See Figure 5
t
CCH
t
CCL
f
CCLK
t
CDS
t
CDH
t
CLS
t
CLH
t
CLHIGH
t
COE
t
COD
t
COH
t
COTS
ADC SERIAL PORT See Figure 13
t
ABH
t
ABL
t
ALS
t
ALH
t
ALS
t
ABDD
AUXILIARY INTERFACE See Figure 12
t
XDS
t
XDH
t
XBH
t
XBL
t
XLS
t
XLH
CCLK high 35 ns
CCLK low 35 ns
CCLK frequency f
CCLK
= 1/t
CCP
; only t
shown in Figure 5
CCP
10 MHz
CDATA setup To CCLK rising 10 ns
CDATA hold From CCLK rising 10 ns
Setup To CCLK rising 10 ns
Hold From CCLK falling 10 ns
High Not shown in Figure 5 10 ns
COUT enable From CCLK falling 30 ns
COUT delay From CCLK falling 30 ns
COUT hold From CCLK falling, not shown in Figure 5 30 ns
COUT tristate From CCLK falling 30 ns
ABCLK high Slave mode 10 ns
ABCLK low Slave mode 10 ns
ALRCLK setup To ABCLK rising, slave mode 10 ns
ALRCLK hold From ABCLK rising, slave mode 5 ns
ALRCLK skew From ABCLK falling, master mode −8 +8 ns
ASDATA delay From ABCLK falling 18 ns
AAUXDATA se t u p To AUXBCLK ris ing 1 0 ns
AAUXDATA hold From AUXBCLK rising 5 ns
AUXBCLK high 10 ns
AUXBCLK low 10 ns
AUXLRCLK setup To AUXBCLK rising 10 ns
AUXLRCLK hold From AUXBCLK rising 5 ns
Rev. 0 | Page 6 of 24
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AD1974
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ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
Analog (AVDD) −0.3 V to +3.6 V
Digital (DVDD) −0.3 V to +3.6 V
Input Current (Except Supply Pins) ±20 mA
Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V
Operating Temperature Range (Case) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA represents thermal resistance, junction-to-ambient; θ
represents the thermal resistance, junction-to-case. All
characteristics are for a 4-layer board.
Table 9.
Package Type θ
48-Lead LQFP 50.1 17 °C/W
JA
θ
JC
JC
Unit
ESD CAUTION
Rev. 0 | Page 7 of 24
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AD1974
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
AGND
AGND
AVDD
NC
NC
NC
NC
PD/RST
NC
DGND
2
3
4
5
6
7
8
9
10
11
12
MCLKI/XI
MCLKO/XO
NC = NO CONNECT
AVDD48LF47ADC2RN46ADC2RP45ADC2LN44ADC2LP43ADC1RN42ADC1RP41ADC1LN40ADC1LP39CM38AVDD
AD1974
TOP VIEW
(Not to S cale)
SINGLE-ENDED
OUTPUT
13
15NC16
17
18
20
21
DVDD
AUXDATA214AUXDATA1
AUXBCLK
AUXLRCLK
ASDATA219ASDATA1
ABCLK
37
36
AGND
35
FILTR
34
AGND
33
AVDD
32
AGND
31
NC
30
NC
29
NC
28
NC
27
CLATCH
26
CCLK
25
DGND
22
23
24
CIN
COUT
ALRCLK
06614-020
Figure 2. AD1974 Single-Ended Output, 48-Lead LQFP Pin Configuration
Table 10. Pin Function Description
Pin No. Type1 Mnemonic Description
1, 4, 32, 34, 36 I AGND Analog Ground.
2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input.
3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output.
5, 33, 37, 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
6 to 9, 11, 16, 28 to 31 NC No Connect.
10 I
PD
/RST
Power-Down/Reset (Active Low).
12, 25 I DGND Digital Ground.
13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply.
14 I/O AUXDATA2 Auxiliary Data Input 2 (From External ADC 2).
15 I/O AUXDATA1 Auxiliary Data Input 1 (From External ADC 1).
17 I/O AUXBCLK Auxiliary Bit Clock.
18 I/O AUXLRCLK Auxiliary Left-Right Framing Clock.
19 I/O ASDATA2 ADC Serial Data Output 2 (ADC 2 Left and ADC 2 Right)/ADC TDM Data Input.
20 O ASDATA1 ADC Serial Data Output 1 (ADC 1 Left and ADC 1 Right)/ADC TDM Data Output.
21 I/O ABCLK Serial Bit Clock for ADCs.
22 I/O ALRCLK Left-Right Framing Clock for ADCs.
23 I CIN Control Data Input (SPI).
24 I/O COUT Control Data Output (SPI).
26 I CCLK Control Clock Input (SPI).
27 I
CLATCH
Latch Input for Control Data (SPI).
35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.
39 I ADC1LP ADC1 Left Positive Input.
40 I ADC1LN ADC1 Left Negative Input.
41 I ADC1RP ADC1 Right Positive Input.
42 I ADC1RN ADC1 Right Negative Input.
43 I ADC2LP ADC2 Left Positive Input.
Rev. 0 | Page 8 of 24
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AD1974
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Pin No. Type1 Mnemonic Description
44 I ADC2LN ADC2 Left Negative Input.
45 I ADC2RP ADC2 Right Positive Input.
46 I ADC2RN ADC2 Right Negative Input.
47 O LF PLL Loop Filter, Return to AVDD.
1
I = input, O = output.
Rev. 0 | Page 9 of 24
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AD1974
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TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.08
0.06
0.04
0.02
0
–0.02
MAGNITUDE (dB)
–0.04
–0.06
–0.08
–0.10
0 18000160001400012000100008000600040002000
FREQUENCY (kHz)
06614-002
Figure 3. ADC Pass-Band Filter Response, 48 kHz
0
–10
–20
–30
–40
–50
–60
MAGNITUDE ( dB)
–70
–80
–90
–100
0 400005000 10000 15000 20000 25000 30000 35000
FREQUENCY (kHz)
Figure 4. ADC Stop-Band Filter Response, 48 kHz
06614-003
Rev. 0 | Page 10 of 24
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AD1974
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THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCS)
There are four ADC channels in the AD1974 configured as two
stereo pairs with differential inputs. The ADCs can operate at a
nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs
include on-board digital antialiasing filters with a 79 dB stopband attenuation and a linear phase response, operating at
an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz
modes). Digital outputs are supplied through two serial data
output pins (one for each stereo pair) as well as a common
frame (ALRCLK) and bit clock (ABCLK). Alternatively, one
of the time division multiplexed (TDM) modes can be used
to access up to 16 channels on a single TDM data line.
The ADCs must be driven from a differential signal source for
b
est performance. The input pins of the ADCs connect to internal switched capacitors. To isolate the external driving op amp
from the glitches caused by the internal switched capacitors,
each input pin should be isolated by using a series connected,
external, 100 Ω resistor together with a 1 nF capacitor connected
from each input to ground. This capacitor must be of high quality,
for instance, a ceramic NPO capacitor or a polypropylene film
capacitor.
The differential inputs have a nominal common-mode voltage
o
f 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the
c
A digital high-pass filter can be switched in line with the ADCs
u
6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency scales directly with sample frequency.
The voltage at CM can be used to bias the external op amps that
b
Refer
Power Supply and Voltage Reference section). The inputs
an also be ac-coupled and do not need an external dc bias to CM.
nder serial control to remove residual dc offsets. It has a 1.4 Hz,
uffer the output signals (see the Power Supply and Voltage
ence section).
CLOCK SIGNALS
The on-chip PLL can be selected to reference the input sample
rate from either the LRCLK or AUXLRCK pins or 256, 384, 512,
or 768 times the sample rate, referenced to the 48 kHz mode from
the MCLKI/XI pin. The default at power-up is 256 × f
MCLKI. In 96 kHz mode, the master clock frequency stays
at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual
multiplication rate is divided by 4. For example, if the AD1974
is programmed in 256 × f
clock input is 256 × 48 kHz = 12.288 MHz. If the AD1974 is
then switched to 96 kHz operation (by writing to the SPI or
2
I
C port), the frequency of the master clock should remain at
12.288 MHz (128 × f
mode, the frequency of the master
S
). In 192 kHz mode, this becomes 64 × fS.
S
from
S
The internal clock for the ADCs is 256 × f
By default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × f
mode) master clock can be used for the ADCs if selected in the
PLL and Clock Control 1 register.
Note that it is not possible to use a direct clock for the ADCs
s
et to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
The PLL can be powered down in the PLL and Clock Control 0
gister. To ensure reliable locking when changing PLL modes,
re
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock has
stabilized.
The internal MCLK can be disabled in the PLL and Clock Control
egister to reduce power dissipation when the AD1974 is idle.
0 r
The clock should be stable before it is enabled. Unless a standalone mode is selected (see the
ck is disabled by reset and must be enabled by writing to the
clo
2
SPI or I
To maintain the highest performance possible, it is recomm
be limited to less than 300 ps rms time interval error (TIE). Even
at these levels, extra noise or tones can appear in the outputs if
the jitter spectrum contains large spectral peaks. If the internal
PLL is not being used, it is highly recommended that an independent crystal oscillator generate the master clock. In addition,
it is especially important that the clock signal should not be
passed through an FPGA, CPLD, DSP, or other large digital
chip before being applied to the AD1974. In most cases, this
induces clock jitter due to the sharing of common power and
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
C port for normal operation.
ended that the clock jitter of the internal master clock signal
Serial Control Port section), the
RESET AND POWER-DOWN
The reset pin sets all the control registers to their default settings.
To avoid pops, reset does not power down the analog outputs.
After reset is deasserted, and the PLL acquires a lock condition,
an initialization routine runs inside the AD1974. This initialization lasts for approximately 256 master clock cycles.
The PLL and Clock Control 0 register and the ADC Control 1
egister power down their respective sections using power down
r
bits. All other register settings are retained. The
should be pulled low by an external resistor to guarantee proper
startup.
for all clock modes.
S
(referenced to 48 kHz
S
RST
PD
/
pin
Rev. 0 | Page 11 of 24
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AD1974
C
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Table 11. Standalone Mode Selection
ADC Clocks CIN COUT CCLK
Slave 0 0 0 0
Master 0 1 0 0
t
CLS
t
LATCH
CCLK
CIN
COUT
t
COE
CCP
D22D23 D9
SERIAL CONTROL PORT
The AD1974 has an SPI control port that permits the programming and reading back of the internal control registers for the
ADCs and the clock system. There is also a standalone mode
available for operation without serial control that is configured
at reset using the serial control pins. All registers are set to
default, except the internal MCLK enable, which is set to 1;
ADC BCLK and LRCLK master/slave, which are set by COUT.
Standalone mode only supports stereo mode with an I
format and 256 f
MCLK rate (see Tab l e 1 1 for details). Using a
S
weak pull-up resistor in applications that have a microcontroller
is highly recommended. This pull-up resistor ensures that the
AD1974 recognizes the presence of a microcontroller.
The SPI control port of the AD1974 is a 4-wire serial control
p
ort. The format is similar to that of the Motorola SPI® format
except that the input data-word is 24 bits wide. The serial bit
clock and latch can be completely asynchronous to the sample
rate of the ADCs.
The f
irst byte is a global address with a read/write bit. For the
Figure 5 shows the format of the SPI signal.
AD1974, the address is 0x04, shifted left one bit due to the R/
bit. The second byte is the AD1974 register address and the
third byte is the data.
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1974 is designed for 3.3 V supplies. Separate power
supply pins (Pin 5, Pin 13, Pin 33, Pin 37, and Pin 38) are provided for the analog and digital sections. These pins should be
bypassed with 100 nF ceramic chip capacitors, as close to the
pins as possible, to minimize noise pickup. A bulk aluminum
electrolytic capacitor of at least 22 μF should also be placed
on the same PC board as the codec. For critical applications,
improved performance is obtained with separate supplies for
the analog and digital sections. If this is not possible, it is rec-
t
t
CCHtCCL
t
CDStCDH
D8
D8
D9
COD
Figure 5. Format of the SPI Signal
2
S data
W
means of a ferrite bead in series with each supply. It is
important that the analog supply be as clean as possible.
All digital inputs are compatible with TTL and CMOS levels.
A
ll outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The ADC internal voltage reference (VREF) is brought out
n FILTR and should be bypassed as close as possible to the
o
AD1974 with a parallel combination of 10 μF and 100 nF. Any
external current drawn should be limited to less than 50 μA.
VREF can be disabled in the PLL and Clock Control 1 register
a
nd FILTR can be driven from an external source. The ADC
input gain varies by the inverse ratio.
CM is the internal common-mode reference. It should be
ypassed as close as possible to the AD1974, with a parallel
b
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The four ADC channels use a common serial bit clock (ABCLK)
and a left-right framing clock (ALRCLK) in the serial data port.
The clock signals are all synchronous with the sample rate. The
normal stereo serial modes are shown in Figure 11.
The ADC serial data modes default to I
programmed for left justified, right justified, and TDM modes.
The word width is 24 bits by default and can be programmed
for 16 or 20 bits. The ADC serial formats and serial clock polarity
are programmable according to the ADC Control 1 register.
The ADC serial ports are programmable to become the bus
masters according to the ADC Control 2 register. By default,
both ADC serial ports are in the slave mode.
ommended that the analog and digital supplies be isolated by
CLATCH
t
CLH
t
COTS
D0
D0
06614-010
2
S. The ports can also be
Rev. 0 | Page 12 of 24
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AD1974
A
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TDM MODES
The AD1974 serial ports also have several different TDM serial
data modes. The first and most commonly used configuration
is shown in Figure 6 where the ADC serial port outputs one
data stream consisting of four on-chip ADCs followed by four
unused slots. In this mode, ABCLK is set to 256 f
TDM mode).
The I/O pins of the serial ports are defined according to the
serial mode selected. For a detailed description of the function
of each pin in TDM and AUX Modes, see Table 12.
The AD1974 allows system configurations with more than four
ADC channels (see Figure 7 and Figure 8) that use 8 ADCs and
16 ADCs. In this mode, four AUX channel slots in the TDM out-
Table 12. Pin Function Changes in TDM and AUX Modes
Pin Name Stereo Mode TDM Mode AUX Mode
ASDATA1 ADC1 data output ADC TDM data output ADCTDM data output
ASDATA2 ADC2 data output ADC TDM data input Not used (float)
AUXDATA1 Not used (ground) Not used (ground) AUXDATA in 1 (from external ADC1)
AUXDATA2 Not used (ground) Not used (ground) AUXDATA in 2 (from external ADC2)
ALRCLK ADC LRCLK input/output ADC TDM frame sync input/output ADCTDM frame sync input/output
ABCLK ADC BCLK input/output ADC TDM BCLK input/output ADCTDM BCLK input/output
AUXLRCLK Not used (ground) Not used (ground) AUXLRCLK input/output
AUXBCLK Not used (ground) Not used (ground) AUXBCLK input/output
(8-channel
S
put stream follow four on-chip ADC channel slots. It should be
noted that due to the high ABCLK frequency, this mode is
available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
LRCLK
ABCLK
ADATA
32 BCLKs
SLOT 1
SLOT 2
LEFT 1
SLOT 3
RIGHT 1
LEFT 2
MSB MSB–1 MSB–2 ADATA
Figure 6. ADC TDM (8-Channel I
256 BCLKs
SLOT 4
UNUSED UNUSED UNUSED UNUSED
RIGHT 2
ALRCLK
ABCLK
2
S Mode.
06614-016
ALRCLK
ABCLK
ASDATA1
(TDM_OUT)
AUXLRCLK
(AUX PORT)
AUXBCLK
(AUX PORT)
AUXDATA1
(AUX1_IN)
AUXDATA2
(AUX2_IN)
ADCL1 ADCR1 ADCL2 ADCR2 AUXL1 AUXR1 AUXL2 AUXR2
FOUR-ON-CHIP DAC CHANNELS
32 BITS
MSB
LEFT RIGHT
MSB MSB
MSB MSB
FOUR-AUX ADC CHANNELS
06614-050
Figure 7. 8-Channel AUX ADC Mode
Rev. 0 | Page 13 of 24
Page 14
AD1974
www.BDTIC.com/ADI
ALRC LK
ABCLK
ASDATA1
(TDM_OUT)
AUXLRCLK
(AUX PORT)
AUXBCLK
(AUX PORT)
AUXDATA1
(AUX1_IN)
AUXDATA2
(AUX2_IN)
FOUR-ON-CHIP
ADC CHANNELS AUXILIARY ADC CHANNELS UNUSED SLOTS
ADCL1 ADCR1 ADCL2 ADCR2 AUXL1 AUXR1 AUXL2 AUXR2 UNUSED UNUSED UNUSED UNUSEDUNUSED UNUSED UNUSED UNUSED
32 BITS
MSB
LEFT RIGHT
MSB MSB
MSB MSB
Figure 8. 16-Channel AUX ADC Mode
06614-052
Rev. 0 | Page 14 of 24
Page 15
AD1974
www.BDTIC.com/ADI
DAISY-CHAIN MODE
The AD1974 also allows a daisy-chain configuration to
expand the system to 8 ADCs and 16 ADCs (see Figure 9 and
Figure 10). There are two configurations for the ADC port to
w
ork in daisy-chain mode. The first one is with an ABCLK at
256 f
shown in Figure 9. The second configuration is with an
S
ABCLK at 512 f
ABCLK mode, the ADC channels occupy the first eight slots,
the second eight slots are empty. The TDM_IN of the first
AD1974 must be grounded in all modes of operation. The
second AD1974 is the device attached to the DSP TDM port.
shown in Figure 10. Note that in the 512 fS
S
ALRCLK
ABCLK
The I/O pins of the serial ports are defined according to the
se
rial mode selected. See Ta bl e 13 for a detailed description
o
f the function of each pin. See Figure 14 for a typical AD1974
co
nfiguration with two external stereo ADCs.
Figure 11 through Figure 13 show the serial mode formats.
F
or maximum flexibility, the polarity of LRCLK and BCLK
are programmable. All of the clocks are shown with their
normal polarity. The default mode is I
2
S.
ASDATA1 (TDM_O UT
OF THE SECOND AD1974
OF THE SECOND AD1974
IN THE CHAIN)
ASDATA2 (TDM_I N
IN THE CHAIN)
ASDATA1 (TDM_O UT
OF THE SECOND AD1974
OF THE SECOND AD1974
IN THE CHAIN)
ASDATA2 (TDM_I N
IN THE CHAIN)
FIRST
AD1974
ALRCLK
ABCLK
FOUR ADC CHANNELS OF THE FI RST IC IN T HE CHAINFOUR ADC CHANNELS OF THE SECOND I C IN THE CHAIN
ADCL1 ADCR1 ADCL2 ADCR2 ADCL1 ADCR1 ADCL2 ADCR2
ADCL1 ADCR1 ADCL2 ADCR2
32 BITS
SECOND
AD1974
FOUR ADC CHANNELS OF
THE SECOND IC I N THE CHAIN
ADCL1 ADCR1 ADCL2 ADC R2 ADCL1 ADCR1 ADCL2 ADCR2 U NUSED
ADCL1 ADCR1 ADCL2 ADC R2
DSP
Figure 9. ADC TDM Daisy-Chain Mode (256 f
FOUR ADC CHANNELS OF
THE FIRST IC IN THE CHAI N
UNUSED UNUSED UNUSED UNUSED UNUSED UNUS ED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
MSB
ABCLK, Two AD1974 Daisy Chains)
S
UNUSED UNUSED UNUSED UNUSED UNUS ED UNUSED UNUSED
32 BITS
06614-056
FIRST
AD1974
SECOND
AD1974
DSP
Figure 10. ADC TDM Daisy-Cha
in Mode (512 f
MSB
ABCLK, Two AD1974 Daisy Chains)
S
Rev. 0 | Page 15 of 24
06614-057
Page 16
AD1974
www.BDTIC.com/ADI
ALRCLK
ABCLK
ASDATA
MSB MSB
LEFT CHANNEL RIGHT CHANNEL
LSB LSB
LEFT JUST IFIED MODE—16 BIT S TO 24 BIT S PER CHANNEL
ALRCLK
ABCLK
ASDATA
ALRCLK
ABCLK
ASDATA
ALRCLK
ABCLK
ASDATA
NOTES
1. DSP MODE DO ES NOT I DENTIFY CHANNEL .
2. LRCL K NORMALLY O PERAT ES AT
3. BCLK FREQUENCY IS NORMAL LY 64 × LRCL K BUT MAY BE OPERATED IN BURST MODE.
MSB
MSB MSB
LEFT CHANNEL
LSB
I2S MODE—16 BIT S TO 24 BIT S PER CHANNEL
LEFT CHANNEL RIGHT CHANNEL
MSB MSB
RIGHT JUST IFIED MO DE—SELECT NUMBER OF BI TS PER CHANNEL
DSP MODE—16 BITS TO 24 BI TS PER CHANNEL
f
EXCEPT FOR DSP MODE WHICH IS 2 ×
S
LSB LSB
LSB LSB
1/
f
S
MSB
f
S.
RIGHT CHANNEL
LSB
06614-013
Figure 11. Stereo Serial Modes
t
XBH
AUXBCLK
t
XBL
t
XLH
AUXRCLK
t
XLS
t
AUXDATA
LEFT JUSTIFIED
MODE
AUXDATA
2
I
C JUSTIFIED
MODE
AUXDATA
RIGHT JUSTIFIED
MODE
XDS
MSB–1MSB
t
XDH
t
XDS
MSB
t
XDH
t
XDS
MSB
t
XDH
Figure 12. Auxiliary S
erial Timing
Rev. 0 | Page 16 of 24
t
XDS
LSB
t
XDH
06614-014
Page 17
AD1974
www.BDTIC.com/ADI
t
ABH
ABCLK
t
ABL
t
ALH
LSB
ALRCLK
ASDATA
LEFT JUSTIFIED
MODE
ASDATA
2
I
C JUSTIFI ED
MODE
ASDATA
RIGHT JUSTIFIED
MODE
t
ABDD
t
ALS
MSB
t
ABDD
MSB–1
MSB
t
ABDD
MSB
Figure 13. ADC Serial Timing
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12)
Pin Name Stereo Mode TDM Mode AUX Mode
ASDATA1 ADC1 data output ADC TDM data output ADCTDM data output
ASDATA2 ADC2 data output ADC TDM data input Not used (float)
AUXDATA1 Not used (ground) Not used (ground) AUXDATA in 1 (from external ADC1)
AUXDATA2 Not used (ground) Not used (ground) AUXDATA in 2 (from external ADC2)
ALRCLK ADC LRCLK input/output ADC TDM Frame Sync input/output ADCTDM frame sync input/output
ABCLK ADC BCLK input/output ADC TDM BCLK input/output ADCTDM BCLK input/output
AUXLRCLK Not used (ground) Not used (ground) AUXLRCLK input/output
AUXBCLK Not used (ground) Not used (ground) AUXBCLK input/output
6614-015
SHARC IS RUNNING
IN SLAVE MODE
(INTERRUPT-DRIVEN)
TxCLK
06614-019
AUX
ADC 1
AUX
ADC 2
LRCLK
BCLK
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
30MHz
12.288MHz
FSYNC-TDM (RFS)
RxCLK
ASDATA1
AUXBCLK
AUXLRCLK
AUXDATA1
AUXDATA2
MCLK
SHARC
RxDATA
ALRCLK ABCLK
AD1974
TDM MASTER
AUX MASTER
TFS (NC)
Figure 14. Example of AUX Mode Connection to SHARC® (AD1974 as TDM Master/AUX Master Shown)
Rev. 0 | Page 17 of 24
Page 18
AD1974
www.BDTIC.com/ADI
CONTROL REGISTERS
The format is the same for I2C and SPI ports. The global address for the AD1974 is 0x04, shifted left one bit due to the R/W bit. All
registers are reset to 0.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address R/
Bit
Table 15. Register Addresses Description
Address Function
0 PLL and Clock Control 0
1 PLL and Clock Control 1
2 AUXPORT Control 0
3 AUXPORT Control 1
4 AUXPORT Control 2
5 Reserved
6 Reserved
7 Reserved
8 Reserved
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 ADC Control 0
15 ADC Control 1
16 ADC Control 2
23:17 16 15:8 7:0
W
Register Address Data
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0
Bit Value Function Description
0 0 Normal operation PLL power-down
1 Power-down
2:1 00 INPUT 256 (×44.1 kHz or 48 kHz) MCLKI/XI pin functionality (PLL active), master clock rate setting
01 INPUT 384 (×44.1 kHz or 48 kHz)
10 INPUT 512 (×44.1 kHz or 48 kHz)
11 INPUT 768 (×44.1 kHz or 48 kHz)
4:3 00 XTAL oscillator enabled MCLKO/XO pin, master clock rate setting
01 256 × fS VCO output
10 512 × fS VCO output
11 Off
6:5 00 MCLKI/XI PLL input
01 AUXLRCLK
10 ALRCLK
11 Reserved
7 0 Disable: ADC idle Internal MCLK enable
1 Enable: ADC active
Rev. 0 | Page 18 of 24
Page 19
AD1974
www.BDTIC.com/ADI
Table 17. PLL and Clock Control 1
Bit Value Function Description
0 0 PLL clock AUXPORT clock source select
1 MCLK
1 0 PLL clock ADC clock source select
1 MCLK
2 0 Enabled On-chip voltage reference
1 Disabled
3 0 Not locked PLL lock indicator (read only)
1 Locked
7:4 0000 Reserved
AUXPORT CONTROL REGISTERS
Table 18. AUXPORT Control 0
Bit Value Function Description
0 0 Reserved Reserved
1 Reserved
2:1 00 32 kHz/44.1 kHz/48 kHz Sample rate
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
5:3 000 1 AUXDATA delay (AUXBCLK periods)
001 0
010 8
011 12
100 16
101 Reserved
110 Reserved
111 Reserved
7:6 00 Stereo (normal) Serial format
01 Reserved
10 ADC AUX mode (ADC-, TDM-coupled)
11 Reserved
Table 19. AUXPORT Control 1
Bit Value Function Description
0 0 Reserved
1 Reserved
2:1 00 64 (two channels) AUXBCLKs per frame
01 Reserved
10 Reserved
11 Reserved
3 0 Left low AUXLRCLK polarity
1 Left high
4 0 Slave AUXLRCLK master/slave
1 Master
5 0 Slave AUXBCLK master/slave
1 Master
6 0 AUXBCLK pin AUXBCLK source
1 Internally generated
7 0 Normal AUXBCLK polarity
1 Inverted
Rev. 0 | Page 19 of 24
Page 20
AD1974
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Table 20. AUXPORT Control 2
Bit Value Function Description
0 0 Reserved
1 Reserved
2:1 00 Reserved
01 Reserved
10 Reserved
11 Reserved
4:3 00 24 Word width
01 20
10 Reserved
11 16
5 0 Reserved
1 Reserved
7:6 00 Reserved
ADC CONTROL REGISTERS
Table 21. ADC Control 0
Bit Value Function Description
0 0 Normal Power-down
1 Power down
1 0 Off High-pass filter
1 On
2 0 Unmute ADC1L mute
1 Mute
3 0 Unmute ADC1R mute
1 Mute
4 0 Unmute ADC2L mute
1 Mute
5 0 Unmute ADC2R mute
1 Mute
7:6 00 32 kHz/44.1 kHz/48 kHz Output sample rate
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
Table 22. ADC Control 1
Bit Value Function Description
1:0 00 24 Word width
01 20
10 Reserved
11 16
4:2 000 1 SDATA delay (BCLK periods)
001 0
010 8
011 12
100 16
101 Reserved
110 Reserved
111 Reserved
Rev. 0 | Page 20 of 24
Page 21
AD1974
www.BDTIC.com/ADI
Bit Value Function Description
6:5 00 Stereo Serial format
01 TDM (daisy chain)
10 ADC AUX mode (TDM-coupled)
11 Reserved
7 0 Latch in midcycle (normal) BCLK active edge (TDM_IN)
1 Latch in at end of cycle (pipeline)
Table 23. ADC Control 2
Bit Value Function Description
0 0 50/50 (allows 32-/24-/20-/16-BCLK per channel) LRCLK format
1 Pulse (32-BCLK/channel)
1 0 Drive out on falling edge (DEF) BCLK polarity
1 Drive out on rising edge
2 0 Left low LRCLK polarity
1 Left high
3 0 Slave LRCLK master/slave
1 Master
5:4 00 64 BCLKs per frame
01 128
10 256
11 512
6 0 Slave BCLK master/slave
1 Master
7 0 ABCLK pin BCLK source
1 Internally generated
Rev. 0 | Page 21 of 24
Page 22
AD1974
A
www.BDTIC.com/ADI
ADDITIONAL MODES
The AD1974 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 15 for an example of an ADC TDM data transmission
ode that does not require high speed ABCLK. This configura-
m
tion is applicable when the AD1974 master clock is generated
by the PLL with the ALRCLK as the PLL reference frequency.
ALRCLK
32 BITS
INTERNAL
ABCLK
ASDATA2
ALRCLK
INTERNAL
ABCLK
To relax the requirement for the setup time of the AD1974 in
cas
es of high speed TDM data transmission, the AD1974 can
latch in the data using the falling edge of ABCLK. This effectively dedicates the entire BCLK period to the setup time. This
mode is useful in cases where the source has a large delay time
in the serial data driver.
ta transmission.
da
Figure 16 shows this pipeline mode of
ASDATA2
Figure 15. Serial ADC Data Transmission in TDM Format Without ABCLK
(Applicable On
ly If PLL Locks to ALRCLK)
06614-059
ALRCLK
ABCLK
DATA MUST BE VAL ID
AT THIS BCL K EDGE
SDATA1
MSB
2
Figure 16. I
(Applicable in Stereo and TDM Useful for High Frequency TDM Transmission)
S Pipeline Mode in ADC Serial Data Transmission
6614-060
Rev. 0 | Page 22 of 24
Page 23
AD1974
F
A
A
www.BDTIC.com/ADI
APPLICATION CIRCUITS
Typical applications circuits are shown in Figure 17 and Figure 18. Figure 17 shows a typical ADC input filter circuit. Recommended loop
filters for LR clock and master clock as the PLL reference are shown in Figure 18.
120p
UDIO
INPUT
600Z
100pF
5.76kΩ
5.76kΩ
2
–
OP275
3
+
5.76kΩ 237Ω
120pF
5.76kΩ
6
–
OP275
5
+
Figure 17. Typical ADC Input Fil
LRCLK
LF
39nF
1
4.7µF
+
1nF
NPO
1nF
4.7µF
7
NPO
237Ω
+
ADCxN
100pF
ADCxP
06614-023
Figure 18. Recommended Loop Filters for LRCLK or MCLK PLL Reference
+
VDD2
2.2nF
3.32kΩ
AVDD2
ter Circuit
MCLK
LF
5.6nF
390pF
562Ω
06614-027
Rev. 0 | Page 23 of 24
Page 24
AD1974
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
9.20
1
12
0.50
BSC
48
13
9.00 SQ
8.80
PIN 1
TOP VIEW
(PINS DO WN)
37
24
0.27
0.22
0.17
36
7.20
7.00 SQ
6.80
25
051706-A
1.45
1.40
1.35
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
0.75
0.60
0.45
0.20
0.09
7°
3.5°
0°
0.08
COPLANARIT Y
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
1.60
MAX
VIEW A
LEAD PITCH
Figure 19. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dim
ensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD1974YSTZ
AD1974YSTZ-RL
EVAL-AD1974EB Evaluation Board
EVAl-AD1974EBZ
1
Z = RoHS Compliant Part.
2
Single-ended output; SPI control port.
1, 2
1, 2
1
–40°C to +105°C 48-Lead LQFP, 13” Reel ST-48
Evaluation Board
–40°C to +105°C 48-Lead LQFP ST-48
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06614-0-4/07(0)
Rev. 0 | Page 24 of 24
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