Datasheet AD1864P-J, AD1864P, AD1864N-K, AD1864N-J, AD1864N Datasheet (Analog Devices)

Complete Dual

a

FEATURES
Dual Serial Input, Voltage Output DACs
No External Components Required
Operates at 8 3 Oversampling per Channel
65 V to 612 V Operation
Cophased Outputs
115 dB Channel Separation

60.3% Interchannel Gain Matching

0.0017% THD+N

APPLICATIONS
Multichannel Audio Applications:
Compact Disc Players
Multivoice Keyboard Instruments
DAT Players and Recorders
Digital Mixing Consoles
Multimedia Workstations

PRODUCT DESCRIPTION

The AD1864 is a complete dual 18-bit DAC offering excellent
THD+N, while requiring no external components. Two com­plete signal channels are included. This results in cophased
voltage or current output signals and eliminates the need for
output demultiplexing circuitry. The monolithic AD1864 chip
includes CMOS logic elements, bipolar and MOS linear
elements and laser-trimmed thin-film resistor elements, all
fabricated on Analog Devices BiMOS II process.

The DACs on the AD1864 chip employ a partially-segmented
architecture. The first four MSBs of each DAC are segmented
into 15 elements. The 14 LSBs are produced using standard
R-2R techniques. Segment and R-2R resistors are laser­trimmed to provide extremely low total harmonic distortion.
This architecture minimizes errors at major code transitions
resulting in low output glitch and eliminating the need for an
external deglitcher. When used in the current output mode, the

AD1864 provides two cophased ± 1 mA output signals.

Each channel is equipped with a high performance output
amplifier. These amplifiers achieve fast settling and high slew

rate, producing ±3 V signals at load currents up to 8 mA. Each

output amplifier is short-circuit protected and can withstand
indefinite short circuits to ground.

The AD1864 was designed to balance two sets of opposing
requirements, channel separation and DAC matching. High
channel separation is the result of careful layout techniques. At
the same time, both channels of the AD1864 have been designed
to ensure matched gain and linearity as well as tracking over time
and temperature. This assures optimum performance when used in
stereo and multi-DAC per channel applications.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

18-Bit Audio DAC

AD1864

DIP BLOCK DIAGRAMS

24

1

–V

TRIM

MSB
I

OUT

AGND

SJ
R

V

OUT

+V

DR

LR

CLK

S

2

REFERENCE

3
4
5
6
7

F

–

8

+

9

L

10

18-BIT

LATCH

11
12

18-BIT

D/A

AD1864

REFERENCE

18-BIT

D/A

18-BIT

LATCH

A versatile digital interface allows the AD1864 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left (LL),
Latch Right (LR) and Clock (CLK). DL and DR are the serial
input pins for the left and right DAC input registers. Input data
bits are clocked into the input register on the rising edge of
CLK. A low going latch edge updates the respective DAC
output. For systems using only a single latch signal, LL and LR
may be connected together. For systems using only one DATA
signal, DR and DL may be connected together.

The AD1864 operates from ± 5 V to ±12 V power supplies. The

digital supplies, V
supplies, V

S

and –VL, can be separated from the analog

L

and –VS, for reduced digital feedthrough. Separate
analog and digital ground pins are also provided. The AD1864
typically dissipates only 225 mW, with a maximum power
dissipation of 265 mW.

The AD1864 is packaged in both a 24-pin plastic DIP and a
28-pin PLCC. Operation is guaranteed over the temperature

range of –25°C to +70°C and over the voltage supply range of
±4.75 V to ±13.2 V.

PRODUCT HIGHLIGHTS

1. The AD1864 is a complete dual 18-bit audio DAC.

2. 108 dB signal-to-noise ratio for low noise operation.

3. THD+N is typically 0.0017%.

4. Interchannel gain and midscale matching.

5. Output voltages and currents are cophased.

6. Low glitch for improved sound quality.

7. Both channels are 100% tested at 8 × F

S

8. Low Power—only 225 mW typ, 265 mW max.

9. Five-wire Interface for individual DAC control.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

+V

S

23

TRIM

22

MSB

21

I

OUT

20

AGND

19

SJ

18

R

–
+

F

17

V

OUT

16

–V

L

15

DL

14

LL

13

DGND

.

(TA = +258C, 6VL = 6VS = 65 V, FS = 352.8 kHz, without MSB adjustment

AD1864–SPECIFICATIONS

RESOLUTION 18 Bits

DIGITAL INPUTS

V

IH

V

IL

, VIH = +V

I

IH

, V

I

IL

IL

Clock Input Frequency 12.7 MHz

ACCURACY

Gain Error 0.4 1.0 % of FSR
Interchannel Gain Matching 0.3 0.8 % of FSR
Midscale Error 4 mV
Interchannel Midscale Matching 5 mV
Gain Linearity Error (0 dB to –90 dB) <2 dB

DRIFT (0°C to +70°C)

Gain Drift ±25 ppm of FSR/°C
Midscale Drift ±4 ppm of FSR/°C

TOTAL HARMONIC DISTORTION + NOISE*

0 dB, 990.5 Hz AD1864N, P 0.004 0.006 %

—20 dB, 990.5 Hz AD1864N, P 0.010 0.040 %

—60 dB, 990.5 Hz AD1864N, P 1.0 4.0 %

CHANNEL SEPARATION*

0 dB, 990.5 Hz 110 115 dB

SIGNAL-TO-NOISE RATIO*

(20 Hz to 30 kHz) N, N-J, N-K 102 108 dB
P, P-J 95 108 dB

D-RANGE* (WITH A-WEIGHT FILTER)

–60 dB, 990.5 Hz AD1864N, P 88 100 dB

OUTPUT

Voltage Output Configuration

Output Range (±3%) 62.88 ±3.0 63.12 V
Output Impedance 0.1 Ω
Load Current ±8mA

Short-Circuit Duration Indefinite to Common

Current Output Configuration

Bipolar Output Range (±30%) ±1mA
Output Impedance (±30%) 1.7 kΩ

POWER SUPPLY

+VL and +V
–VL and –V
+I, (+V
–I, (–VL and –VS = –5 V) –23 –28 mA

POWER DISSIPATION, ±VL = ±VS = ±5 V 225 265 mW

TEMPERATURE RANGE

Specification 0 +25 +70 °C
Operation –25 +70 °C
Storage –60 +100 °C

WARM-UP TIME 1

NO

TES
Specifications shown in boldface are tested on production units at final test without optional MSB adjustment.
*Tested in accordance with EIAJ Test Standard CP-307 with 18-bit data.
Specifications subject to cha

L

= 0.4 V –10 µA

AD1864N-J, P-J 0.003 0.004 %
AD1864N-K 0.0017 0.0025 %

AD1864N-J, P-J 0.010 0.020 %
AD1864N-K 0.010 0.020 %

AD1864N-J, P-J 1.0 2.0 %
AD1864N-K 1.0 2.0 %

AD1864N-J, P-J 94 100 dB
AD1864N-K 94 100 dB

S

S

and +VS = +5 V) 22 25 mA

L

nge without notice.

unless otherwise noted)

Min Typ Max Units

2.0 +V

L

0.8 V

1.0 µA

4.75 5.0 13.2 V
–13.2 –5.0 –4.75 V

–2–

V

min

REV. A

Typical Performance Data—

5

700

100

0

10

0

AD1864

100

90

80

70

60

50

40

THD+N – dB

30

20

10

0

0

24

0dB

–20dB

–60dB

FREQUENCY – kHz

6810

Figure 1. THD+N vs. Frequency

130
120
110
100

90
80
70
60
50
40

CHANNEL SEPARATION – dB

30
20

10

0

0

5

FREQUENCY – kHz

10 1

Figure 2. Channel Separation vs. Frequency

600

500

400

300

200

POWER DISSIPATION – mW

100

0

0681012

SUPPLY VOLTAGE –+V

Figure 4. Power Dissipation vs. Supply Voltage

90

80

70

60

50

40

THD+N – dB

30

20

10

0

500 1000

1500

LOAD RESISTANCE – Ω

2000

2500 300

Figure 5. THD+N vs. Load Resistance

100

8

95

90

THD+N – dB

85

80

0

20 40 60

TEMPERATURE – C

Figure 3. THD+N vs. Temperature

REV. A

–3–

6

4

2

0

–2

–4

GAIN LINEARITY ERROR – dB

–6

–8

–10

–100

–80

–70

–60

INPUT AMPLITUDE – dB

–40

–10–90

–20–50 –30

Figure 6. Gain Linearity Error vs. Input Amplitude

AD1864

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 13.2 V

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 13.2 V

S

–V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –13.2 V to 0 V

L

–V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –13.2 V to 0 V

S

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V

Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V

Short-Circuit Protection . . . . . . . . Indefinite Short to Ground

Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1864 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

L

RIGHT

CHANNEL

I

OUT

AGND

SJ
NC
RF

V

OUT

+V

L

PIN CONFIGURATIONS

DIP Package

1

–V

S

2

TRIM

3

MSB

4

I

OUT

AGND

5

AD1864

6

V

+V

CLK

SJ
R

OUT

DR
LR

7

F

8
9

L

10
11
12

TOP VIEW

(Not to Scale)

PLCC Package

S

CK

S

NC

+V

28 27 26

NC

DGND

TRIM

–V

MSB

321

4

5
6
7

8

9

10

11

12 13

AD1864

TOP VIEW

(Not to Scale)

14 15 16

LR

DR

NC = NO CONNECT

24
23
22
21
20
19
18
17
16
15
14
13

TRIM

17 18

LL

+V

S

TRIM
MSB

I

OUT

AGND
SJ
R

F

V

OUT

–V

DL
LL

DGND

MSB

DL

L

LEFT
CHANNEL

25

I

OUT

24

AGND

23

SJ

22

NC
RF

21

V

20

OUT

–V

19

PIN FUNCTION DESCRIPTIONS

Signal Description

–V

S

Negative Analog Supply
TRIM Right Channel Trim Network Connection
MSB Right Channel Trim Potentiometer Connection
I

OUT

Right Channel Output Current
AGND Right Channel Analog Common Pin
SJ Right Channel Amplifier Summing Junction
R
V
+V

F

OUT

L

Right Channel Feedback Resistor

Right Channel Output Voltage

Positive Digital Supply
DR Right Channel Data Input Pin
LR Right Channel Latch Pin
CLK Clock Input Pin
DGND Digital Common Pin
LL Left Channel Latch Pin
DL Left Channel Data Input Pin
–V
V
R

L

OUT

F

Negative Digital Supply

Left Channel Output Voltage

Left Channel Feedback Resistor
SJ Left Channel Amplifier Summing Junction
AGND Left Channel Analog Common Pin
I

OUT

Left Channel Output Current
MSB Left Channel Trim Potentiometer Wiper Connection
TRIM Left Channel Trim Network Connection
+V

S

Positive Analog Supply

ORDERING GUIDE

THD+N Package

Model @ Full Scale Option*

AD1864N 0.006% N-24

L

AD 1864N-J 0.004% N-24
AD1864N-K 0.0025% N-24
AD1864P 0.006% P-28A
AD1864P-J 0.004% P-28A

*N = Plastic DIP; P = Plastic Leaded Chip Carrier.

–4–

REV. A

AD1864

TOTAL HARMONIC DISTORTION + NOISE

Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the
amplitudes of the harmonics and noise to the value of the
fundamental input frequency. It is usually expressed in percent.

THD+N is a measure of the magnitude and distribution of
linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending
on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small (–20 dB, –60 dB) signal amplitudes. THD+N measure­ments for the AD1864 are made using the first 19 harmonics
and noise out to 30 kHz.

SIGNAL-TO-NOISE RATIO

The Signal-to-Noise Ratio is defined as the ratio of the ampli­tude of the output when a full- scale code is entered to the
amplitude of the output when a midscale code is entered. It is
measured using a standard A-Weight filter. SNR for the
AD1864 is measured for noise components up to 30 kHz.

CHANNEL SEPARATION

Channel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the AD1864 channel separation is
measured in accordance with EIAJ Standard CP-307, Section 5.5.

D-RANGE DISTORTION

D-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
60 dB below full-scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard
A-Weight filter as specified by EIAJ Standard CP-307.

GAIN ERROR

The gain error specification indicates how closely the output of
a given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale output
signal.

INTERCHANNEL GAIN MATCHING

The gain matching specification indicates how closely the
amplitudes of the output signals match when producing
identical input data. It is expressed in % of FSR (Full-Scale
Range = 6 V for the AD1864) and is measured with full-scale
output signals.

MIDSCALE ERROR

Midscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the twos comple­ment input code representing half scale is loaded into the input
register of the DAC. It is expressed in mV.

INTERCHANNEL MIDSCALE MATCHING

The midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the twos complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.

24

–V

TRIM

MSB
I

OUT

AGND

SJ
R

V

OUT

+V
DR

LR

CLK

1

S

2

REFERENCE

3
4
5
6
7

F

–

8

+

9

L

10

18-BIT

LATCH

11

12

18-BIT

D/A

AD1864

REFERENCE

18-BIT

D/A

+

18-BIT

LATCH

+V

S

23

TRIM

22

MSB

21

I

OUT

20

AGND

19

SJ

18

R

–

F

17

V

OUT

16

–V

L

15

DL

14

LL

13

DGND

DIP Block Diagram

FUNCTIONAL DESCRIPTION

The AD1864 is a complete, monolithic, dual 18-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two 18-bit serial input registers and two
18-bit DACs.

The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This
combination of elements produces reference voltages that are
unaffected by changes in temperature and time.

The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique
produces higher slew rate and lower distortion than previous
techniques. Frequency response is also improved. When
combined with the appropriate on-chip feedback resistor, the
output op amps convert the output current to output voltages.

The 18-bit D/A converters use a combination of segmented
decoder and R-2R architecture to achieve consistent linearity
and differential linearity. The resistors which form the ladder
structure are fabricated with silicon chromium thin film. Laser
trimming of these resistors further reduces linearity errors
resulting in low output distortion.

The input registers are fabricated with CMOS logic gates.
These gates allow the achievement of fast switching speeds and
low power consumption, contributing to the low glitch and low
power dissipation of the AD1864.

REV. A

–5–

AD1864

GROUNDING RECOMMENDATIONS

The AD1864 has three ground pins, two labeled AGND and
one labeled DGND. AGND, the analog ground pins, are the
“high quality” ground references for the device. To minimize
distortion and reduce crosstalk between channels, the analog
ground pins should be connected together only at the analog
common point in the system. As shown in Figure 7, the AGND
pins should not be connected at the chip.

–ANALOG

SUPPLY

V

OUT

DIGITAL
SUPPLY

1
2
3
4
5
6
7
8

9
10
11
12

AD1864

–V

S

TRIM

MSB

I

OUT

AGND
SJ
R

F

V

OUT

+V

L

DR

LR
CLK

+V

TRIM

MSB

I

OUT

AGND

SJ
R

V

OUT

–V

DL
LL

DGND

24

S

23
22
21

20
19
18

F

17
16

L

15
14
13

ANALOG
SUPPLY

V

OUT

–DIGITAL
SUPPLY

DIGITAL
COMMON

Figure 7. Recommended DIP Circuit Schematic

The digital ground pin returns ground current from the digital
logic portions of the AD1864 circuitry. This pin should be
connected to the digital common pin in the system. Other
digital logic chips should also be referred to that point. The
analog and digital grounds should be connected together at one
point in the system, preferably at the power supply.

POWER SUPPLIES AND DECOUPLING

The AD1864 has four power supply pins. ± V

provides the

S

supply voltages that operate the analog portions of the DAC,
including the voltage references, output amplifiers and control

amplifiers. The ±V

supplies are designed to operate from ±5 V

S

to ±12 V. These supplies should be decoupled to analog
common using 0.1 µF capacitors. Good engineering practice

suggests that the bypass capacitors be placed as close as possible
to the package pins. This minimizes the parasitic inductive
effects of printed circuit board traces.

The ± V

supplies operate the digital portions of the chip,

L

including the input shift registers and the input latching
circuitry. These supplies should be bypassed to digital common

using 0.1 µF capacitors. ±V

operates with ±5 V to ±12 V

L

supplies. In order to assure proper operation of the AD1864,
–V

must be the most negative power supply voltage at all times.

S

Though separate positive and negative power supply pins are
provided for the analog and digital portions of the AD1864, it is
also possible to use the AD1864 in systems featuring a single
positive and a single negative power supply. In this case, the
+V

and +VL input pins should be connected to the positive

S

power supply. –V

and –VL should be connected to the single

S

negative supply. This feature allows reduction of the cost and
complexity of the system power supply.

As with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be
incorporated into the design of an audio system.

DISTORTION PERFORMANCE AND TESTING

The THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD+N specification, therefore,
provides a direct method to classify and choose an audio DAC
for a desired level of performance. Figure 1 illustrates the typical
THD+N performance of the AD1864 versus frequency. A load

impedance of at least 1.5 kΩ is recommended for best THD+N

performance.

Analog Devices tests and grades all AD1864s on the basis of
THD+N performance. During the distortion test, a high speed
digital pattern generator transmits digital data to each channel
of the device under test. Eighteen-bit data is latched into the

DAC at 352.8 kHz (8 × F

). The test waveform is a 990.5 kHz

S

sine wave with 0 dB, –20 dB and –60 dB amplitudes. A 4096
point FFT calculates total harmonic distortion + noise,
signal-to-noise ratio, D-Range and channel separation. No
deglitchers or MSB trims are used.

OPTIONAL MSB ADJUSTMENT

Use of optional adjust circuitry allows residual distortion error
to be eliminated. This distortion is especially important when
low amplitude signals are being reproduced. The MSB adjust
circuitry is shown in Figure 8. The trim pot should be adjusted
to produce the lowest distortion using an input signal with a
–60 dB amplitude.

200kΩ

100kΩ 470kΩ

1
2
3
4
5
6
7
8

9
10
11
12

AD1864

–V

S

TRIM

MSB

I

OUT

AGND

SJ

R

F

V

OUT

+V

L

DR
LR
CLK

+V
TRIM
MSB

I

OUT

AGND

V

OUT

–V

DL
LL

DGND

24

S

23
22
21
20
19

SJ

18

R

F

17
16

L

15
14
13

200kΩ100kΩ470kΩ

–6–

Figure 8. Optional DIP THD+N Adjust Circuitry

REV. A

AD1864

CURRENT OUTPUT MODE

One or both channels of the ADl864 can be operated in current
output mode. I

can be used to directly drive an external

OUT

current-to-voltage (I-V) converter. The internal feedback
resistor, R
I-V converter, thus assuring that R

, can still be used in the feedback path of the external

F

tracks the DAC over time

F

and temperature.

Of course, the AD1864 can also be used in voltage output mode
utilizing the onboard I-V converter.

VOLTAGE OUTPUT MODES As shown in the ADl864 block diagram, each channel of the ADl864 is complete with an I-V converter and a feedback resistor. These can be connected externally to provide direct voltage output from one or both AD1864 channels. Figure 7 shows these connections. I connected to the summing junction, SJ. V the feedback resistor, R

CLK

. This implementation results in the

F

M
S

DL

B

M

DR

S

B

is connected to

OUT

OUT

is

lowest possible component count and achieves the performance

shown on the specifications page while operating at 8 × F

.

S

INPUT DATA

Data is transmitted to the AD1864 in a bit stream composed of
18-bit words with a serial, twos complement, MSB first format.
Data Left (DL) and Data Right (DR) are the serial inputs for
the left and right DACs, respectively. Similarly, Latch Left (LL)
and Latch Right (LR) update the left and right DACs. The
falling edges of LL and LR cause the last 18 bits clocked into
the Serial Registers to be shifted into the DACs, thereby
updating the DAC outputs. Left and Right channels share the
Clock (CLK) signal. Data is clocked into the input registers on
the rising edge of CLK.

Figure 9 illustrates the general signal requirements for data
transfer for the AD1864.

L
S
B

L
S
B

LL

LR

Figure 9. Control Signals

TIMING

Figure 10 illustrates the specific timing requirements that must
be met in order for the data transfer to be properly accomplished.
The input pins of the AD1864 are both TTL and 5 V CMOS
compatible.

>80ns

>40ns

>15ns

MSB

1st BIT

>30ns

INTERNAL DAC REGISTER

UPDATED WITH 18 MOST RECENT BITS

2nd BIT

>30ns

CLK

LL/LR

>15ns

DL/DR

The minimum clock rate of the AD1864 is at least 12.7 MHz.

This clock rate allows data transfer rates of 2×, 4×, 8× and
16 × F

(where FS equals 44.1 kHz). The applications section

S

of this data sheet contains additional guidelines for using the
AD1864.

>15ns

NEXT

WORD

LSB

(18th BIT)

>60ns

>40ns >40ns

REV. A

Figure 10. Timing Diagram

–7–

BITS CLOCKED

TOSHIFT REGISTER

AD1864

SM5813AP/A

1
2
3
4
5
6
7
8

V

SS1

9

10

11
12
13
14

PT

BCKO

WCKO

DOL
DOR

V

V

SS2

DG

OW18

OW20

–5V ANALOG SUPPLY

AD1864

28
27
26
25
24
23
22

DD

21

20
19
18
17
16
15

+5V DIGITAL SUPPLY –5V DIGITAL SUPPLY

C1

1

–V

S

2

TRIM

3

MSB

4

I

OUT

5

AGND

6

SJ

7

R

F

8

V

OUT

9

+V

L

10

DR

11

LR

12

CLK

+V

TRIM

MSB

I

OUT

AGND

SJ

R

V

OUT

–V

DL
LL

DGND

24

S

23
22
21
20
19
18

F

17
16

L

15
14
13

+5V ANALOG SUPPLY

C2

1
2
3
4

–V

S

AD712

NE5532

OR

+V

LEFT
CHANNEL
OUTPUT

RIGHT

8

S

7
6
5

CHANNEL
OUTPUT

Figure 11. Complete 8 × FS 18-Bit CD Player

8-BIT CD PLAYER DESIGN

Figure 11 illustrates an 18-bit CD player design incorporating
an AD1864 D/A converter, an AD712 or NE5532 dual op amp
and the SM5813 digital filter chip manufactured by NPC. In
this design, the SM5813 filter transmits left and right digital
data to both channels of the AD1864. The left and right latch
signals, LL and LR, are both provided by the word clock signal
(WCKO) of the digital filter. The digital filter supplies data at

an 8 × F

oversample rate to each channel.

S

The digital data is converted to analog output voltages by the
output amplifiers on the AD1864. Note that no external
components are required by the AD1864. Also, no deglitching
circuitry is required.

An AD712 or NE5532 dual op amp is used to provide the
output antialias filters required for adequate image rejection.
One 2-pole filter section is provided for each channel. An
additional pole is created from the combination of the internal
feedback resistors (R

) and the external capacitors C1 and C2.

F

For example, the nominal 3 kΩ RF with a 360 pF capacitor for

C1 and C2 will place a pole at approximately 147 kHz, effec­tively eliminating all high frequency noise components.

Close matching of the ac characteristics of the amplifiers on the
AD712 as well as their low distortion make it an ideal choice for
the task.

LOW distortion, superior channel separation, low power
consumption and a low component count are all realized by this
simple design.

–8–

REV. A

AD1864

VOICE 1

VOICE 2

VOICE 3

VOICE 4

VOICE 5

VOICE 6

N

+5V ANALOG

SUPPLY

–5V ANALOG

SUPPLY

ANALOG

COMMON

VOICE 1 LOAD

VOICE 2 LOAD
VOICE 3 LOAD

DATA

CLOCK

OUTPUT

10
11
12

1
2
3
4
5
6
7
8
9

AD1864

–V

S

TRIM
MSB
I

OUT

AGND
SJ
R

F

V

OUT

+V

L

DR

LR
CLK

+V
TRIM
MSB

I

OUT

AGND

V

OUT

–V

DL
LL

DGND

+V
TRIM
MSB

I

OUT

SJ
R

V

OUT

–V

DL
LL

OUTPUT

OUTPUT

OUTPUT

AD1864

24

S

23
22
21
20
19
18

F

17
16

L

15
14
13

1

–V

S

2

TRIM

3

MSB

4

I

OUT

AGND

5
6

SJ

7

R

F

8

V

OUT

9

+V

L

10

DR

LR

11

12

CLK

+V

TRIM

MSB

I

OUT

AGND

V

OUT

–V

DGND

24

S

23
22
21
20

19

SJ

18

R

F

17
16

L

15

DL

14

LL

13

VOICE 6 LOAD

VOICE 5 LOAD
VOICE 4 LOAD

DIGITAL COMMON
–5V DIGITAL COMMO

OUTPUT

OUTPUT

AD1864

24

S

23
22
21
20
19

SJ

18

R

F

17
16

L

15
14
13

–V

1

S

2

TRIM

3

MSB

4

I

OUT

AGND

5
6
7
8

9
10
11
12

SJ

R

V
+V
DR

F

OUT

LR
CLK

AGND

L

DGND

Figure 12. Cascaded AD1864s in a Multichannel Keyboard Instrument

MULTICHANNEL DIGITAL KEYBOARD DESIGN

Figure 12 illustrates how to cascade AD1864s to add multiple
voices to an electronic musical instrument. In this example, the
data and clock signals are shared between all six DACs. As the
data representing an output for a specific voice is loaded, the
appropriate DAC is updated. For example, after the 18 bits
representing the next output value for Voice #4 is clocked out
on the data line, then “Voice 4 Load” is pulled low. This produces
a new output for Voice 4. Furthermore, all voices can be
returned to the same output by pulling all six load signals low.

In this application, the advantages of choosing the AD1864 are
clear. Its flexible digital interface allows the clock and data to
be shared among all DACs. This reduces printed circuit board
area requirements and also simplifies the actual layout of the
board. The low power requirement of the AD1864 (typically
215 mW) is an advantage in a multiple DAC system where its
power advantage is multiplied by the number of DACs used.

The AD1864 requires no external components, simplifying the
design, reducing the total number of components required and
enhancing reliability.

ADDITIONAL APPLICATIONS

Figures 13 through 16 show connection diagrams for the
AD1864 and a number of standard digital filter chips from
Yamaha, NPC and Sony. Figure 13 shows the SM5814AP
operating with pipelined data. Cophase operation is not
available with the SM5814AP in 18-bit mode. Figures 14
through 16 are all examples of cophase operation. Each

application operates at 8 × F

for each channel. The 2-pole

S

Rauch low-pass filters shown in Figure 11 can be used with all
of the applications shown in this data sheet. The AD711 single
op amp can also be used in these applications in order to ensure
maximum channel separation.

REV. A

–9–

AD1864

V ANALOG

V ANALOG

1

SM5814AP

(22-PIN DIP)

2

3
4
5

V

6

SS

7

8

9

10
11

–5V ANALOG

SUPPLY

+5V ANALOG

SUPPLY

AD1864

+V

TRIM

MSB

I

OUT

AGND

SJ
R

V

OUT

–V

DL
LL

DGND

24

S

23
22
21
20
19
18

F

17

16

L

15
14
13

–5V DIGITAL

SUPPLY

SOMD1

SOMD2

V

BCKO

WDCO

DOR

DOL
DGL

1

22
21
20
19
18
17

DD

16
15
14
13
12

+5V DIGITAL

SUPPLY

–V

S

2

TRIM

3

MSB

4

I

OUT

AGND

5
6

SJ

7

R

F

8

V

OUT

9

+V

L

DR

10
11

LR

12

CLK

Figure 13. AD1864 with NPC SM5814AP Digital Filter

LPF

LPF

RIGHT
CHANNEL
OUTPUT

LEFT
CHANNEL
OUTPUT

1
2
3
4
5
6
7
8

–5

SUPPLY

+5

SUPPLY

AD1864

24

+V

TRIM

MSB

I

OUT

AGND

SJ
R

V

OUT

–V

DL
LL

DGND

S

23

22

21
20
19
18

F

17
16

L

15
14
13

S

L

YM3434

SHL

V

DD2

V

DD1

SHR

16/18

ST

V

BCO

WCO

DRO

DLO

SS

16
15
14
13
12

11
10

9

+5V DIGITAL

1

–V

2

TRIM

3

MSB

4

I

OUT

5

AGND

6

SJ

7

R

F

8

V

OUT

9

+V

10

DR

11

LR

12

CLK

Figure 14. AD1864 with Yamaha YM3434 Digital Filter

–5V DIGITAL

LPF

LPF

RIGHT
CHANNEL
OUTPUT

LEFT
CHANNEL
OUTPUT

–10–

REV. A

16.9344

L

L

5V ANALOG

5V ANALOG

MHz

GND

1

TEST

2
3
4
5

CXD1244S

6
7
8

XIN

9

10

V

DD

V

11

DD

12
13
14
15
16
17

LFS

18

SONY/12S
19
20

TEST

TEST
TEST
TEST
TEST

BCKO

DATAL

GND
GND

DATAR

LE/

WS

OUT 16/18

DPOL

TEST
TEST

AD1864

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

–5V ANALOG

SUPPLY

1
2
3
4
5
6
7
8

9
10
11
12

AD1864

–V

S

TRIM
MSB

I

OUT

AGND

SJ

R

F

V

OUT

+V

L

DR
LR
CLK

+V

TRIM

MSB

I

OUT

AGND

SJ
R

V

OUT

–V

DL

LL

DGND

+5V ANALOG

SUPPLY

24

S

23
22
21
20
19
18

F

17
16

L

15
14
13

LPF

LPF

RIGHT
CHANNEL
OUTPUT

LEFT
CHANNEL
OUTPUT

+5V DIGITAL

SUPPLY

Figure 15. AD1864 with Sony CXD1244S Digital Filter

SM5818AP

(16-PIN DIP)

1
2
3
4
5

6
7

8

V

SS

V

DD

BCKO

WDCO

OMOD2

DOR

DOL

OMOD1

16
15

14

13
12
11
10

9

–

+5V DIGITAL

SUPPLY

SUPPLY

8

10
11

12

1
2
3
4
5
6

SJ

7

9

+V

AD1864

–V

S

TRIM
MSB

I

OUT

AGND

R

F

V

OUT

L

DR

LR
CLK

+V

TRIM

MSB

I

OUT

AGND

SJ
R

V

OUT

–V

DL

LL

DGND

S

F

L

+

SUPPLY

24
23

22

21

20

19
18
17
16
15
14
13

–5V DIGITAL

SUPPLY

–5V DIGITAL

SUPPLY

LPF

LPF

RIGHT
CHANNE
OUTPUT

LEFT
CHANNE
OUTPUT

REV. A

Figure 16. AD1864 with NPC SM5818AP Digital Filter

–11–

AD1864

OTHER DIGITAL AUDIO COMPONENTS AVAILABLE

FROM ANALOG DEVICES

C1405c–1–6/97

AD1856 16-BIT AUDIO DAC

Complete, No External Components

Required

0.0025% THD
Low Cost
16-Pin DIP or SOIC Package
Standard Pinout

AD1860 18-BIT AUDIO DAC

Complete, No External Components

Required

0.002% THD+N
108 dB Signal-to-Noise Ratio
16-Pin DIP or SOIC Package
Standard Pinout

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Pin Plastic DIP

AD1862 20-BIT AUDIO DAC

120 dB Signal-to-Noise Ratio

0.0012% THD+N
105 dB D-Range Performance

±1 dB Gain Linearity

16-Pin DIP

28-Pin PLCC

–12–

PRINTED IN U.S.A.

REV. A