Datasheet AD1852 Datasheet (ANALOG DEVICES)

Stereo, 24-Bit, 192 kHz,

FEATURES

5 V stereo audio DAC system
Accepts 16-bit/18-bit/20-bit/24-bit data
Supports 24 bits, 192 kHz sample rate
Accepts a wide range of sample rates including

32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz

Multibit Σ-Δ modulator with perfect differential linearity

restoration for reduced idle tones and noise floor
Data-directed scrambling DAC—least sensitive to jitter
Differential output for optimum performance
117 dB signal-to-noise (not muted) at 48 kHz sample rate

(A-weighted mono)
114 dB signal-to-noise (not muted) at 48 kHz sample rate

(A-weighted stereo)
117 dB dynamic range (not muted) at 48 kHz sample rate

(A-weighted mono)
114 dB dynamic range (not muted) at 48 kHz sample rate

(A-weighted stereo)

−105 dB THD+N (mono application circuit)

−102 dB THD+N (stereo)
115 dB stop-band attenuation
On-chip clickless volume control
Hardware and software controllable clickless mute
Serial (SPI) control for: serial mode, number of bits, sample

rate, volume, mute, de-emp
Digital de-emphasis processing for 32 kHz, 44.1 kHz, 48 kHz

sample rates
Clock autodivide circuit supports five master-clock frequencies
Flexible serial data port with right-justified, left-justified,

2

I

S-compatible and DSP serial port modes

28-Lead SSOP plastic package

Multibit, Sigma-Delta DAC

AD1852

APPLICATIONS

High end

DVDs, CDs, home theater systems, automotive, audio

systems, sampling musical keyboards, digital mixing
consoles, and digital audio effects processors

GENERAL DESCRIPTION

The AD1852 is a complete, high performance, single-chip, stereo
digital, audio playback system. It is comprised of a multibit, Σ-Δ
modulator, digital interpolation filters, and analog output drive
circuitry. Other features include an on-chip, stereo attenuator
and mute, programmed through an SPI-compatible serial control
port. The AD1852 is fully compatible with all known DVD
formats, including 192 kHz, as well as 96 kHz sample frequencies
and 24 bits. It is also backwards compatible by supporting
50 μs/15 μs digital de-emphasis intended for Red Book compact
discs, as well as de-emphasis at 32 kHz and 48 kHz sample rate.

The AD1852 has a very simple, but very flexible, serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers, and sample rate converters. The
AD1852 can be configured in left-justified, I
or DSP serial port compatible modes. It can support 16, 18, 20,
and 24 bits in all modes. The AD1852 accepts serial audio data
in MSB first, twos-complement format. The AD1852 operates
from a single 5 V power supply. It is fabricated on a single,
monolithic integrated circuit and is housed in a 28-lead SSOP
for operation over the 0°C to 70°C temperature range.

2

S, right-justified,

FUNCTIONAL BLOCK DIAGRAM

VOLUME
MUTE

AD1852

16-/18-/20-/24-BIT

DIGITAL

DATA INPUT

SERIAL

MODE

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2

SERIAL

DATA

INTERFACE

ATTEN/

ATTEN/

RESET

MUTE

MUTE

8 ×

f

S

INTERPOLATOR

f

8 ×

S

INTERPOLATOR

2

AUTO-CLOCK

DIVIDE CIRCUI T

22

ZERO
FLAG

CLOCK

IN

ANALOG
OUTPUTS

CONTROL DAT A

INPUT

3

SERIAL CONTROL

INTERFACE

MULTIBIT SIGMA-

DELTA MODUL AT OR

MULTIBIT SIGMA-

DELTA MODUL AT OR

DE-EMPHASISMUTE

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2000–2009 Analog Devices, Inc. All rights reserved.

ANALOG

SUPPLY

DIGITAL
SUPPLY

VOLTAGE

REFERENCE

DAC

DAC

8457-001

AD1852

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Analog Performance .................................................................... 3

Digital I/O (0°C to 70°C) ............................................................. 4

Temperature Range ...................................................................... 4

Power .............................................................................................. 4

Digital Filter Characteristics ....................................................... 4

Group Delay .................................................................................. 4

Digital Timing ............................................................................... 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ..............................................9

Theory of Operation ...................................................................... 12

Serial Data Input Port ................................................................ 12

Serial Data Input Mode ............................................................. 12

Master Clock Autodivide Feature ............................................ 13

SPI Register Definitions ............................................................ 13

Register Addresses ...................................................................... 14

Volume Left and Volume Right Registers ............................... 14

SPI Timing................................................................................... 14

Mute ............................................................................................. 14

Control Register ......................................................................... 15

De-Emphasis ............................................................................... 15

Output Impedance ..................................................................... 15

Reset ............................................................................................. 15

Control Signals ........................................................................... 15

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

11/09—Rev. 0 to Rev. A

Changes to Format ............................................................. Universal

Changes to Note 1 ............................................................................. 1

Changes to Table 2 ............................................................................ 3

Changes to Table 11 .......................................................................... 7

Changes to Register Addresses Section and Mute Section ....... 14

Changes to Figure 29 ...................................................................... 16

1/00—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD1852

SPECIFICATIONS

Test conditions, unless otherwise noted.

Table 1.

Parameter Rating

Supply Voltages (AVDD, DVDD) 5.0 V
Ambient Temperature 25°C
Input Clock 24.576 MHz (512 × fS Mode)
Input Signal 996.11 Hz

−0.5 dB full scale
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 20 bits
Load Capacitance 100 pF
Load Impedance 47 kΩ
Input Voltage High 2.4 V
Input Voltage Low 0.8 V

ANALOG PERFORMANCE

Table 2.

Parameter1 Min Typ Max Unit

RESOLUTION 24 Bits
SIGNAL-TO-NOISE RATIO (20 Hz TO 20 kHz)

No Filter (Stereo) 112 dB

No Filter (Mono, See Figure 19) 115 dB

With A-Weighted Filter (Stereo) 114 dB

With A-Weighted Filter (Mono) 117 dB

DYNAMIC RANGE (20 Hz To 20 kHz, −60 dB INPUT)

No Filter (Stereo) 107 112 dB

No Filter (Mono, See Figure 24) 115 dB

With A-Weighted Filter (Stereo) 110 114 dB

With A-Weighted Filter (Mono) 117 dB

TOTAL HARMONIC DISTORTION + NOISE (STEREO) −94 −102 dB

0.00079 %
TOTAL HARMONIC DISTORTION + NOISE (MONO, SEE Figure 20) −105 dB

0.00056 %
TOTAL HARMONIC DISTORTION + NOISE (STEREO) VO = −20 dB −92 dB
TOTAL HARMONIC DISTORTION + NOISE (STEREO) VO = −60 dB −52 dB
ANALOG OUTPUTS

Differential Output Range (±Full Scale) 5.6 V p-p

Output Capacitance at Each Output Pin 2 pF

OUT-OF-BAND ENERGY (0.5 × fS TO 100 kHz) −90 dB
CMOUT 2.37 V
DC ACCURACY

Gain Error −10 ±2.0 +10 %

Interchannel Gain Mismatch −0.15 ±0.015 +0.15 dB

Gain Drift 150 250 ppm/°C

DC Offset −50 mV

INTERCHANNEL CROSSTALK (EIAJ METHOD) −120 dB
INTERCHANNEL PHASE DEVIATION ±0.1 Degrees
MUTE ATTENUATION −100 dB
DE-EMPHASIS GAIN ERROR ±0.1 dB

1

Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).

Rev. A | Page 3 of 20

AD1852

DIGITAL I/O (0°C TO 70°C)

Table 3.

Parameter Min Typ Max Unit

Input Voltage High (VIH) 2.2 V
Input Voltage Low (VIL) 0.8 V
Input Leakage (IIH at VIH = 2.4 V) 10 μA
Input Leakage (IIL at VIL = 0.8 V) 10 μA
High Level Output Voltage (VOH), IOH = 1 mA 2.0 V
Low Level Output Voltage (VOL), IOL = 1 mA 0.4 V
Input Capacitance 20 pF

TEMPERATURE RANGE

Table 4.

Parameter Min Typ Max Unit

Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage −55 +150 °C

POWER

Table 5.

Parameter Min Typ Max Unit

SUPPLIES

Voltage, Analog and Digital 4.50 5 5.50 V
Analog Current 33 40 mA
Analog Current—RESET
Digital Current 20 30 mA
Digital Current—RESET

DISSIPATION

Operation—Both Supplies 265 mW
Operation—Analog Supply 165 mW
Operation—Digital Supply 100 mW

POWER SUPPLY REJECTION RATIO

1 kHz, 300 mV p-p Signal at Analog Supply Pins −60 dB
20 kHz, 300 mV p-p Signal at Analog Supply Pins −50 dB

32 46 mA

27 37 mA

DIGITAL FILTER CHARACTERISTICS

Table 6.

Sample Rate (kHz) Pass Band (kHz) Stop Band (kHz) Stop-Band Attenuation (dB) Pass-Band Ripple (dB)

44.1 DC − 20 24.1 − 328.7 110 ±0.0002
48 DC − 21.8 26.23 − 358.28 110 ±0.0002
96 DC − 39.95 56.9 − 327.65 115 ±0.0005
192 DC − 87.2 117 − 327.65 95 +0/−0.04 (DC − 21.8 kHz)
+0/−0.5 (DC − 65.4 kHz)
+0/−1.5 (DC − 87.2 kHz)

GROUP DELAY

Table 7.

Chip Mode Group Delay Calculation fS (kHz) Group Delay (μs)

INT8× Mode 5553/(128 × fS) 48 903.8
INT4× Mode 5601/(64 × fS) 96 911.6
INT2× Mode 5659/(32 × fS) 192 921

Rev. A | Page 4 of 20

AD1852

DIGITAL TIMING

Guaranteed over 0°C to 70°C, AVDD = DVDD = 5.0 V × 10%.

Table 8.

Parameter Description Min Unit

t

MCLK period (f

DMP

t

MCLK low pulse width (all modes) 0.4 × t

DML

t

MCLK high pulse width (all modes) 0.4 × t

DMH

t

BCLK high pulse width (see Figure 26) 20 ns

DBH

t

BCLK low pulse width (see Figure 26) 20 ns

DBL

t

BCLK period (see Figure 26) 60 ns

DBP

t

LRCLK setup (see Figure 26) 20 ns

DLS

t

LRCLK hold (DSP serial port mode only) 5 ns

DLH

t

SDATA setup (see Figure 26) 5 ns

DDS

t

SDATA hold (see Figure 26) 10 ns

DDH

low pulse width

t

RSTL

1

Higher MCLK frequencies are allowable when using the on-chip master clock autodivide feature.

RESET

MCLK

= 256 × f

)1 54 ns

LRCLK

ns

DMP

ns

DMP

15

ns

Rev. A | Page 5 of 20

AD1852

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Rating

DVDD to DGND −0.3 V to +6 V
AVDD to AGND −0.3 V to +6 V
Digital Inputs DGND − 0.3 V to DVDD + 0.3 V
Analog Outputs AGND − 0.3 V to AVDD + 0.3 V (see Figure 26)
AGND to DGND −0.3 V to +0.3 V
Reference Voltage (AVDD + 0.3 V)/2 V
Soldering 300°C
10 sec

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 10.

Package Type θJA θJC Unit

Thermal Resistance

Junction-to-Ambient 109 °C/W
Junction-to-Case 39 °C/W

ESD CAUTION

Rev. A | Page 6 of 20

AD1852

C

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

DGND

2

MCLK

LATCH

3

CCLK

4

CDATA

5

6

7

8

9

10

11

12

13

14

AD1852

TOP VIEW

(Not to Scale)

NC

192/48

ZEROR

DEEMP

96/48

AGND

OUTR+

OUTR–

FILTER

Figure 2. Pin Configuration

Table 11. Pin Function Descriptions

Pin No. Mnemonic Input/Output Description

1 DGND I Digital Ground.
2 MCLK I

Master Clock Input. Connect to an external clock source running at either 256 f

, or 1024 fS.

768 f

S

3 CLATCH I Latch Input for SPI Control Data Port. This input is rising-edge sensitive.
4 CCLK I

SPI Control Clock Input for Control Data. Control input data must be valid on the rising edge of
CCLK. CCLK may be continuous or gated.

5 CDATA I

SPI Control Data Input, MSB First. SPI data port for controlling AD1852 functions as described in
the SPI Register Definitions section.

6 NC

7

192/48

8 ZEROR O

I

No Connect.

192 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 192 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 11 of the control register.

Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input
for more than 1024 LR clock cycles.

9 DEEMP I

De-Emphasis. Digital de-emphasis is enabled when this input signal is high. This is used to
impose a 50 μs/15 μs response characteristic on the output audio spectrum at an assumed

44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via the SPI
control register.

10

96/48

I

96 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 96 kHz.

When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 10 of the control register.
11, 15 AGND I Analog Ground.
12 OUTR+ O Right Channel Positive Line Level Analog Output.
13 OUTR− O Right Channel Negative Line Level Analog Output.
14 FILTR O

Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference

with parallel 10 μF and 0.1 μF capacitors to the AGND.
16 OUTL− O Left Channel Negative Line Level Analog Output.
17 OUTL+ O Left Channel Positive Line Level Analog Output.
18 AVDD I Analog Power Supply. Connect this pin to the analog 5 V supply.
19 FILTB Filter Capacitor Connection. Connect 10 μF||10 nF capacitor to AGND (Pin 15).
20 IDPM1 I Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
21 IDPM0 I Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
22 ZEROL O

Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input

for more than 1024 LR clock cycles.
23 MUTE I Mute. Assert this pin high to mute both stereo analog outputs. De-assert low for normal operation.
24

RESET

I

Reset. The AD1852 is reset on the rising edge of this signal. The serial control port registers are

reset to the default values. For normal operation, assert this pin high.

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DVDD

SDATA

BCLK

LRCLK

RESET

MUTE

ZEROL

IDPM0

IDPM1

FILTB

AVDD

OUTL+

OUTL–

AGND

08457-002

, 384 fS, 512 fS,

S

Rev. A | Page 7 of 20

AD1852

S

A

S

A

S

A

S

A

S

A

Pin No. Mnemonic Input/Output Description

25 LRCLK I
26 BCLK I

Left/Right
Bit Clock Input for Serial Audio Data Input Port. This pin need not run continuously; may be

gated or used in a burst fashion.

27 SDATA I

Serial Audio Data Input, MSB First. Input for the serial audio data stream is as described the
in Serial Data Input Port section.

28 DVDD I Digital Power Supply. Connect this pin to the digital 5 V supply.

Table 12. Serial Data Input Mode

IDPM1 (Pin 20) IDPM0 (Pin 21) Serial Data Input Format

0 0 Right justified
0 1 I2S compatible
1 0 Left justified
1 1 DSP

LRCLK

INPUT

BCLK

INPUT

DAT

INPUT

LSB

LEFT CHANNEL

MSB

Clock Input for Serial Audio Data Input Port. This pin must run continuously.

RIGHT CHANNEL

LSBMSB–2 LSB+2 LSB+1MSB–1

Figure 3. Right-Justified Mode

MSB

MSB –1

MSB –2

LSB +2

LSB+1

LSB

08457-003

LRCLK

INPUT

BCLK

INPUT

DAT

INPUT

LRCLK

INPUT

BCLK

INPUT

DAT

INPUT

LRCLK

INPUT

BCLK

INPUT

DAT

INPUT

LRCLK

INPUT

LEFT CHANNEL

LEFT CHANNEL

LEFT CHANNEL

LSBMSB–2 LSB+2 LSB+1MSB–1MSB

LEFT CHANNEL

LSBLSB+2 LSB+1MSB–1MSB

LSBMSB–2 LSB+2 LSB+1MSB–1MSB

Figure 4. I

2

S-Justified Mode

MSB

Figure 5. Left-Justified Mode

Figure 6. Left-Justified DSP Mode

MSB –1

MSB

MSB– 2

MSB –1

MSB –2

MSB– 1

MSB

RIGHT CHANNEL

RIGHT CHANNEL

LSB+1

LSB+ 2

RIGHT CHANNEL

LSB+1

LSB+ 2

RIGHT CHANNEL

LSB+1

LSB+ 2

LSB

LSB

LSB

MSB

MSB MSB–1

MSB MSB–1

08457-004

08457-005

08457-006

BCLK

INPUT

DAT

INPUT

LSB MSB

Figure 7. 32 × f

MSBLSBMSB–1 MSB–2 LSB+2 LSB+1 MSB–1 MSB–2

Packed Mode

S

MSBLSBLSB+2 LSB+1 M SB–1

8457-007

Rev. A | Page 8 of 20

AD1852

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8 to Figure 13 show the calculated frequency response of the digital interpolation filters. Figure 14 to Figure 25 show the performance of
the AD1852 as measured by an Audio Precision System 2 Cascade. For the wideband plots, the noise floor shown in the plots is higher
than the actual noise floor of the AD1852. This is caused by the higher noise floor of the high bandwidth ADC used in the Audio Precision
measurement system. The two-tone test shown in Figure 16 is per the SMPTE standard for measuring intermodulation distortion.

0.0010

0.0008

0.0006

0.0004

0.0002

0

–0.0002

MAGNITUDE (dB)

–0.0004

–0.0006

–0.0008

–0.0010

0246810121416182022

FREQUENCY (kHz)

Figure 8. Pass-Band Response 8× Mode, 48 kHz Sample Rate

0.5

0.4

0.3

0.2

0.1

0

–0.1

MAGNITUDE (dB)

–0.2

–0.3

–0.4

–0.5

–105 1015202530354045

FREQUENCY (kHz)

Figure 9. 44 kHz Pass-Band Response 4× Mode, 96 kHz Sample Rate

2.0

08457-008

08457-009

0

–20

–40

–60

–80

–100

ATTENUATION (dB)

–120

–140

–160

0 50 100 150 200 250 300 350

FREQUENCY (kHz)

Figure 11. Complete Response, 8× Mode, 48 kHz Sample Rate

0

–20

–40

–60

–80

–100

ATTENUATION (dB)

–120

–140

–160

0 50 100 150 200 250 300

FREQUENCY (kHz)

Figure 12. Complete Response, 4× Mode, 96 kHz Sample Rate

0

08457-011

08457-012

1.5

1.0

0.5

0

–0.5

MAGNITUDE (dB)

–1.0

–1.5

–2.0

0 102030405060708090

FREQUENCY (kHz)

Figure 10. 88 kHz Pass-Band Response 2× Mode, 192 kHz Sample Rate

08457-010

Rev. A | Page 9 of 20

–20

–40

–60

–80

–100

ATTENUATION (dB)

–120

–140

–160

0 50 100 150 200 250

FREQUENCY (kHz)

Figure 13. Complete Response, 2× Mode, 192 kHz Sample Rate

08457-013

AD1852

–

–

–

50

–60

–70

–80

–90

MAGNITUDE (dBr)

–100

–110

–120

10 100 1k 10k 20k

FREQUENCY (Hz)

Figure 14. THD vs. Frequency Input @ −3 dBFS, SR 48 kHz

2

08457-014

0

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE (dB)

–80

–90

–100

–110

–120 0–20–40–60–80–100

FREQUENCY (kHz)

Figure 17. THD + N Ratio vs. Amplitude Input 1 kHz, SR 48 kS/s, 24-Bit

90

08457-017

0

–2

–4

–6

MAGNITUDE (dBr)

–8

–10

–12

10 100 1k 10k 20k

FREQUENCY (Hz)

Figure 15. Normal De-Emphasis Frequency Response Input @

−10 dBFS, SR 48 kHz

10

–30

–50

–70

–90

MAGNITUDE (dBr)

–110

–130

–150

0246810121416182022

FREQUENCY (kHz)

Figure 16. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS

–100

–110

–120

–130

MAGNITUDE (dBr)

–140

–150

–160

0246810121416182022

08457-015

FREQUENCY (kHz)

08457-018

Figure 18. Noise Floor for Zero Input, SR 48 kHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

MAGNITUDE (dBr)

–110

–120

–130

–140

–150

0246810121416182022

08457-016

FREQUENCY (kHz)

08457-019

Figure 19. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz, SR 48 kHz

Rev. A | Page 10 of 20

AD1852

–

–

0

–20

–40

–60

–80

MAGNITUDE (dBr)

–100

–120

–140

–140 –20–40–60–80–100–120 0

(dBFS)

08457-020

Figure 20. Linearity vs. Amplitude Input 200 Hz, SR 48 kS/s, 24-Bit Word

64

–66

–68

–70

–72

MAGNITUDE (dBr)

–74

–76

10 100 1k 10k 20k

FREQUENCY (Hz)

08457-021

Figu re 21. Power Supply Rejection vs. Frequency, AVDD 5 V DC + 100 mV p-p AC

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

MAGNITUDE (dBr)

–100

–110

–120

–130

–140

0110080604020

FREQUENCY (kHz)

20

08457-022

Figure 22. Wideband Plot, 15 kHz Input, 8× Interpolation, SR 48 kHz

50

–60

–70

–80

–90

–100

–110

–120

MAGNITUDE (dBr)

–130

–140

–150

–160

0246810121416182022

FREQUENCY (kHz)

08457-023

Figure 23. Dynamic Range for 1 kHz @ −60 dBFS, Triangular Dithered Input

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

MAGNITUDE (dBr)

–110

–120

–130

–140

–150

–160

0875706560555045403530252015105

FREQUENCY (kHz)

0

08457-024

Figure 24. Wideband Plot, 75 kHz Input, 2× Interpolation, SR 192 kHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

MAGNITUDE (dBr)

–100

–110

–120

–130

–140

0110080604020

FREQUENCY (kHz)

20

08457-025

Figure 25. Wideband Plot, 37 kHz Input, 4× Interpolation, SR 96 kHz

Rev. A | Page 11 of 20

AD1852

THEORY OF OPERATION

SERIAL DATA INPUT PORT

The flexible, serial data input port of the AD1852 accepts data
in twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by either using the external mode pins (IDPM0, Pin 21 and
IDPM1, Pin 20) or the mode select bits (Bit 4 and Bit 5) in the
SPI control register. To control the serial mode using the
external mode pins, the SPI mode select bits should be set to
zero (the default mode at power-up). To control the serial mode
using the SPI mode select bits, the external mode control pins
should be grounded.

In all modes, except for right-justified mode, the serial port
accepts an arbitrary number of bits up to 24. Extra bits do not
cause an error, but they are truncated internally. In right­justified mode, use Bit 8 and Bit 9 of the SPI control register to
set the word length to 16 bits, 20 bits, or 24 bits. The default
mode at power-up is 24-bit mode. When the SPI control port is
not being used, the SPI pins (CLATCH, CCLK, and CDATA
[Pin 3, Pin 4, and Pin 5]) should be tied low.

SERIAL DATA INPUT MODE

The AD1852 uses two multiplexed input pins to control the
mode configuration of the input data port mode (see Tabl e 12).

Figure 3 shows the right-justified mode (16 bits shown). LRCLK is
high for the left channel and low for the right channel. Data is
valid on the rising edge of BCLK.

In normal operation, there are 64-bit clocks per frame (or 32 per
half frame). When the SPI word length control bits (Bit 8 and
Bit 9 in the SPI control register) are set to 24 bits (0:0), the serial
port begins to accept data starting at the eighth bit clock pulse
after the LRCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12
clock position. In 16-bit mode, data is accepted starting at the

th

16

bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore, other data formats
are possible using the delay values previously described. For
detailed timing, see Figure 26.

th

bit

Figure 4 shows the I

2

S mode. LRCLK is low for the left channel
and high for the right channel. Data is valid on the rising edge
of BCLK. The MSB is left justified to an LRCLK transition but
with a single BCLK period delay. The I

2

S mode can be used to

accept any number of bits up to 24.

Figure 5 shows the left-justified mode. LRCLK is high for the
left channel, and low for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an LRCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits, and any number of bit
clocks from two times the word length to 64-bit clocks per
frame.

Figure 6 shows the DSP serial port mode. LRCLK must pulse
high for at least one bit clock period before the MSB of the left
channel is valid, and LRCLK must pulse high again for at least
one bit clock period before the MSB of the right channel is
valid. Data is valid on the falling edge of BCLK. The DSP serial
port mode can be used with any word length up to 24 bits.

In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse and that
synchronism is maintained from that point forward.

Note that the AD1852 is capable of a 32 × f

BCLK frequency

S

packed mode, where the MSB is left justified to an LRCLK
transition, and the LSB is right justified to the opposite LRCLK
transition. LRCLK is high for the left channel and low for the
right channel. Data is valid on the rising edge of BLCK. Packed
mode can be used when the AD1852 is programmed in right­justified or left-justified mode. Packed mode is shown is Figure 7.

Rev. A | Page 12 of 20

AD1852

LEFT-JUSTIFIED

RIGHT-JUSTIFIED

LRCLK

SDATA

MODE

SDATA

2

I

C-JUSTIFI ED

MODE

SDATA

MODE

BCLK

t

DBH

t

DBL

t

DLS

t

DDS

MSB

t

DDH

8-BIT CLOCKS
(24-BIT DATA)

12-BIT CLOCKS
(20-BIT DATA)

16-BIT CLOCKS
(16-BIT DATA)

t

DBP

MSB – 1

t

DDS

MSB

t

DDH

t

DDS

MSB

t

DDH

t

DDS

LSB

t

DDH

08457-026

Figure 26. Serial Data Port Timing

Table 13. Allowable MCLK Frequencies and Internal Delta Clock Rates

Chip Mode Allowable Master Clock Frequencies Nominal Input Sample Rate (kHz) Internal Sigma-Delta Clock Rate

INT 8× Mode 256 × fS, 384 × fS, 512 × fS, 768 × fS, 1024 × fS 48 128 × fS
INT 4× Mode 128 × fS, 192 × fS, 256 × fS, 384 × fS, 512 × fS 96 64 × fS
INT 2× Mode 64 × f

MASTER CLOCK AUTODIVIDE FEATURE

The AD1852 has a circuit that autodetects the relationship between
the master clock and the incoming serial data and internally sets
the correct divide ratio to run the interpolator and modulator. The
allowable frequencies for each mode are shown in Tab l e 13 .
Master clock should be synchronized with LRCLK; however,
phase relation between master clock and LRCLK is not critical.

SPI REGISTER DEFINITIONS

The SPI port allows flexible control of many chip parameters. It
is organized around three registers: a left-channel volume register, a
right-channel volume register, and a control register. Each write
operation to the AD1852 SPI control port requires 16 bits of
serial data in MSB-first format. The bottom two bits are used to
select one of three registers, and the top 14 bits are then written
to that register. This allows a write to one of the three registers

, 96 × fS, 128 × fS, 192 × fS, 256 × fS 192 32 × fS

S

t

CHD

CDATA

CCLK

CLATCH

t

CCH

t

CCL

D15

D14

t

CSU

Figure 27. Serial Control Port Timing

The SPI CCLK signal is used to clock in the data. The incoming
data should change on the falling edge of this signal. At the end
of the 16 CCLK periods, the CLATCH signal should rise to
clock the data internally into the AD1852.

The serial control port timing is shown in Figure 27, and the
SPI digital timing values are listed in Tab l e 14 .

Table 14. SPI Digital Timing

Parameter Description Value

t

CCLK high pulse width 40 ns

CCH

t

CCLK low pulse width 40 ns

CCL

t

CDATA setup time 10 ns

CSU

t

CDATA hold time 10 ns

CHD

t

CLATCH low pulse width 10 ns

CLL

t

CLATCH high pulse width 10 ns

CLH

t

CLATCH setup time 4 × t

CLSU

D0

t

CLH

t

CLL

t

CLSU

8457-027

MCLK

in a single 16-bit transaction.

Rev. A | Page 13 of 20

AD1852

REGISTER ADDRESSES

The lowest two bits of the 16-bit serial control data word are
decoded as the address of the register into which the upper
14 bits are written. These bits are defined in Tabl e 15.

Table 15. AD1852 Registers

Bit 1 Bit 0 Register

0 0 Volume left
1 0 Volume right
0 1 Control register

VOLUME LEFT AND VOLUME RIGHT REGISTERS

A write operation to the left or right volume registers activates
the autoramp, clickless volume control feature of the AD1852.
The upper 10 bits of the volume control word increment or
decrement by 1 at a rate equal to the input sample rate. The
bottom four bits are not fed into the autoramp circuit and thus
take effect immediately. This arrangement gives a worst-case
ramp time of about 20 ms for step changes of more than 60 dB,
which was determined by listening tests to be optimal in terms of
preventing the perception of a click sound on large volume
changes. See Figure 28 for a graphical description of how the
volume changes as a function of time.

The 14-bit volume control word is used to multiply the signal,
and therefore, the control characteristic is linear, not dB. A
constant dB/step characteristic can be obtained by using a
lookup table in the microprocessor that is writing to the SPI
port. The volume word is unsigned (that is, 0 dB is 11 1111
1111 1111).

SPI TIMING

The SPI port is a 3-wire interface with serial data (CDATA),
serial bit clock (CCLK), and data latch (CLATCH). The data
is clocked into an internal shift register on the rising edge of
CCLK. The serial data should change on the falling edge of
CCLK and be stable on the rising edge of CCLK. The rising
edge of CLATCH is used internally to latch the parallel data
from the serial-to-parallel converter. This rising edge should be
aligned with the falling edge of the last CCLK pulse in the 16-bit
frame. The CCLK can run continuously between transactions.

Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
update on the next edge of the LRCLK after the CLATCH write
pulse, as shown in Figure 27.

MUTE

The AD1852 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal high, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Bit 6) high. The
AD1852 was designed to minimize pops and clicks when muting
and unmuting the device by automatically ramping the gain up
or down. When the device is unmuted, the volume returns to
the value set in the volume register.

0

–60

LEVEL (dB)

0

–60

20ms

Figure 28. Smooth Volume Control

VOLUME REQUEST REG ISTER

ACTUAL VOLUME REGISTER

TIME

08457-028

Rev. A | Page 14 of 20

AD1852

CONTROL REGISTER

Tabl e 16 shows the functions of the control register. The control
register is addressed by having a 01 in the bottom two bits of the
16-bit SPI word. The top 14 bits are then used for the control register.

DE-EMPHASIS

The AD1852 has a built-in, de-emphasis filter that can be used
to decode CDs that have been encoded with the standard Red
Book 50 μs/15 μs emphasis response curve. Three curves are
available; one each for the 32 kHz, 44.1 kHz, and 48 kHz
sampling rates. The external DEEMP pin (Pin 9) turns on the

44.1 kHz de-emphasis filter. The other filters may be selected by
writing to Control Bit 2 and Control Bit 3 in the control register.
If the SPI port is used to control the de-emphasis filter, the
external DEEMP pin should be tied low.

OUTPUT IMPEDANCE

The output impedance of the AD1852 is 65 Ω ± 30%.

RESET

The AD1852 may be reset either by a dedicated hardware pin

RESET

(
reset is active, normal operation of the AD1852 is suspended,
and the outputs assume midscale values. The AD1852 should
always be reset at power up. The
active for a minimum of 64 master clock periods. When the
RESET
after a delay equal to the group delay, plus three MCLK periods.

, Pin 24) or by software via the SPI control port. When

RESET

function should be

function becomes inactive, normal operation continues

Using the
default values, when the
rises, the default operation is enabled. Alternatively, the internal

registers can be reset to their default values by setting Bit 7 of
the internal control register high. When Bit 7 is reset low,
default operation continues. The software reset differs from the
hardware reset because the soft reset does not affect the values
stored in the SPI registers.

CONTROL SIGNALS

The IDPM0 and IDPM1 control inputs are normally connected
high or low to establish the operating state of the AD1852, as
described in Ta ble 1 2. They can be changed dynamically (and
asynchronously to LRCLK and the master clock), but it is
possible that a click or pop sound will result during the
transition from one serial mode to another. If possible, the
AD1852 should be placed in mute before such a change is
made.

RESET

pin, the internal registers are set to their

RESET

pin is active low. When

RESET

Table 16. Control Register Functions

Bit Number Function

Bit 11

Bit 10

Bit 9:8 Number of bits in right-justified serial mode
0:0 = 24
0:1 = 20
1:0 = 16
Default = 0:0
Bit 7 Reset; default = 0
Bit 6 Soft mute OR’d with pin; default = 0
Bit 5:4 Serial mode OR’d with mode pins; IDPM1:IDPM0
0:0 = right-justified
0:1 = I2S
1:0 = left-justified
1:1 = DSP mode
Default = 0:0
Bit 3:2 De-emphasis filter select
0:0 = no filter
0:1 = 44.1 kHz filter
1:0 = 32 kHz filter
1:1 = 48 kHz filter
Default = 0:0

INT 2× mode OR’d with Pin 7 (192/48

INT 4× mode OR’d with Pin 10 (96/48

); default = 0

); default = 0

Rev. A | Page 15 of 20

AD1852

JP11

MCLK/SR SEL

I/F MODE IDPM1 IDPM0

RJ, 16-BIT 0 0

2

S01

I
RJ, 20-BIT 1 0
RJ, 24-BIT 1 1

JP21

I/F

MODE

R3

10kΩR210kΩR110kΩ

DVDD

R4

10kΩR510kΩ

SDATA

LRCLK

BCLK

MCLK

DEEMP

MUTE

CLATCH

CCLK

CDATA

RESET

DGND

DVDD

SELECT RATE 192/48 96/48
SPDIF 44.1kHz TO 48kHz 0 0
DIRECT 88.2kHz TO 96kHz 0 1
DIRECT 176.4kHz TO 192kHz 1 0

AD1852 STEREO DAC

DVDD

C3

100nF

96/48

192/48

NC

SDATA

LRCLK

BCLK

MCLK

IDPM0

IDPM1

DEEMP

MUTE

CLATCH

CCLK

CDATA

ZR

ZEROR

ZL

ZEROL

RESET

1

ZL

U2A

HC04

MCLK/SR SELECT

U1

AD1852JRS

AGND

DGND

FB1

600Z

C4

100nF

2

AVDDDVDD

AVDD

R6
221Ω

100nF

CR1
ZERO
LEFT

AGND

C2

OUTL+

OUTL–

OUTR+

OUTR–

FILTR

FILTB

R7
221Ω

CR2
ZERO
RIGHT

C8
10µF

1.96kΩ

R16

1.87kΩ

1.87kΩ

1.96kΩ

1.96kΩ

R18

1.87kΩ

1.87kΩ

1.96kΩ

OUTPUT BUF FERS AND L P FILTERS

R8

R10

R12

R14

C7
10µF

C9
220pF
NP0

C10
220pF
NP0

C11
220pF
NP0

C12
220pF
NP0

+AV

–AV

R17

R11

R13

R19

R15

C1
100nF

R9

1.96kΩ

C14
1nF
NP0

C13
1nF
NP0

1.96kΩ

1.96kΩ

C17
1nF
NP0

C16
1nF
NP0

1.96kΩ

U3B
SSM2135

R20

200Ω

10nF

NP0

3RD ORDER LP BESS EL FIL TER
CORNER FREQ UENCY: 75kHz
GROUP DELAY: ~3.5µs

CC

U3A

C5

SSM2135

100nF

R21

200Ω

C6

10nF

100nF

NP0

CC

C15

C18

J11

J21

LEFT
OUT

RIGHT
OUT

3

ZR

U2B

HC04

4

08457-029

Figure 29. DAC, Output Buffers, and LP Filters

Rev. A | Page 16 of 20

AD1852

R5

R1

SDATA

BCLK

LRCLK

MCLK

2

I

S LEFT/RIGHT

DATA SEPARATOR

AND INVERTER

SDATA
LRCLK
BCLK

AD1852

SDATA
LRCLK
BCLK

AD1852

0°

180°

0°

180°

3.01kΩ

3.01kΩ

3.01kΩ

3.01kΩ

L+

L

L–

R+

L

R–

L+

R

L–

R+

R

R–

R2

C7

1.5nF

R3

R4

R7

3.01kΩ

R8

3.01kΩ

C9

1.5nF

R9

3.01kΩ

R10

3.01kΩ

3.01kΩ

R6

3.01kΩ

R11

3.01kΩ

R12

3.01kΩ

R13

1.00kΩ

C8

1.5nF

R14

1.00kΩ

R15

1.00kΩ

C10

1.5nF

R16

1.00kΩ

C2
270pF

C2
270pF

C3
270pF

C4
270pF

AD797

AD797

R17

549Ω

R18

549Ω

R19

53.6kΩ

R20

53.6kΩ

C5

2.2nF

C6

2.2nF

1

0

1

0

2

I

S INPUT TO

DATA SEPARATOR

DATA SEPARATOR

OUTPUT

LRCLK

SDATA

LRCLK

LSDATA

RDATA

Ln Rn

Ln

Rn

Ln+1

Ln

Rn

Rn+1

Ln+1

Rn+1

Figure 30. Mono Application Circuit

Ln+2

Ln+1

Rn+1

Rn+2

Ln+2

Rn+2

Ln+2

Rn+2

08457-030

Rev. A | Page 17 of 20

AD1852

OUTLINE DIMENSIONS

10.50

10.20

9.90

0.38

0.22

15

5.60

5.30

8.20

5.00

7.80

1.85

1.75

1.65

SEATING
PLANE

7.40

0.25

0.09

8°
4°
0°

0.95

0.75

0.55

060106-A

14

2.00 MAX

0.05 MIN

COPLANARITY

0.10

28

1

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AH

Figure 31. 28-Lead Shrink Small Outline Package [SSOP]

(RS-28)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD1852JRSZ1 0°C to 70°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD1852JRSZRL1 0°C to 70°C 28-Lead Shrink Small Outline Package [SSOP], 13" Tape and Reel RS-28
EVAL-AD1852EBZ

1

Z = RoHS Compliant Part.

1

Evaluation Board

Rev. A | Page 18 of 20

AD1852

NOTES

Rev. A | Page 19 of 20

AD1852

NOTES

©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08457-0-11/09(A)

Rev. A | Page 20 of 20