Datasheet AD1852 Datasheet (Analog Devices)

Stereo, 24-Bit, 192 kHz

a

FEATURES
5 V Stereo Audio DAC System
Accepts 16-Bit/18-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:

32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and
192 kHz

Multibit Sigma-Delta Modulator with “Perfect

Differential Linearity Restoration” for Reduced Idle
Tones and Noise Floor

Data-Directed Scrambling DAC—Least Sensitive to

Jitter
Differential Output for Optimum Performance
117 dB Signal-to-Noise (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)
114 dB Signal-to-Noise (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)
117 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)
114 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)
–105 dB THD+N (Mono Application Circuit)
–102 dB THD+N (Stereo)
115 dB Stopband Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,

Sample Rate, Volume, Mute, De-Emp
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,

48 kHz Sample Rates
Clock Autodivide Circuit Supports Five Master-Clock

Frequencies

Multibit Σ∆ DAC

AD1852*

Flexible Serial Data Port with Right-Justified, Left-

Justified, I

28-Lead SSOP Plastic Package

APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive

Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors

PRODUCT OVERVIEW

The AD1852 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma­delta modulator, digital interpolation filters, and analog output
drive circuitry. Other features include an on-chip stereo attenuator
and mute, programmed through an SPI-compatible serial control
port. The AD1852 is fully compatible with all known DVD
formats including 192 kHz as well as 96 kHz sample frequen­cies and 24 bits. It also is backwards compatible by supporting

50 µs/15 µs digital de-emphasis intended for “Redbook” compact

discs, as well as de-emphasis at 32 kHz and 48 kHz sample rate.

The AD1852 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters. The
AD1852 can be configured in left-justified, I
or DSP serial port compatible modes. It can support 16, 18, 20,
and 24 bits in all modes. The AD1852 accepts serial audio data
in MSB first, twos-complement format. The AD1852 oper­ates from a single 5 V power supply. It is fabricated on a single
monolithic integrated circuit and is housed in a 28-lead SSOP

package for operation over the temperature range 0°C to 70°C.

2

S-Compatible and DSP Serial Port Modes

2

S, right-justified,

FUNCTIONAL BLOCK DIAGRAM

VOLUME

MUTE

AD1852

16-/18-/20-/24-BIT

DATA INPUT

*Patents Pending

DIGITAL

SERIAL

MODE

2

SERIAL

DATA

INTERFACE

ATTEN/

ATTEN/

RESET

MUTE

MUTE

8 3 F

S

INTERPOLATOR

8 3 F

INTERPOLATION

S

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

2

AUTO-CLOCK

DIVIDE CIRCUIT

22

ZERO
FLAG

CLOCK

IN

ANALOG
OUTPUTS

CONTROL DATA

INPUT

3

SERIAL CONTROL

INTERFACE

MULTIBIT SIGMA-

DELTA MODULATOR

MULTIBIT SIGMA-

DELTA MODULATOR

DE-EMPHASISMUTE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ANALOG

SUPPLY

DIGITAL
SUPPLY

VOLTAGE

REFERENCE

DAC

DAC

AD1852–SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages (AVDD, DVDD) 5.0 V

Ambient Temperature 25°C
Input Clock 24.576 MHz (512 × F

Input Signal 996.11 Hz

–0.5 dB Full Scale
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 20 Bits
Load Capacitance 100 pF

Load Impedance 47 kΩ

Input Voltage HI 2.4 V
Input Voltage LO 0.8 V

ANALOG PERFORMANCE (See Figures)

Resolution 24 Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)

No Filter (Stereo) 112 dB

No Filter (Mono—See Figure 29) 115 dB

With A-Weighted Filter (Stereo) 114 dB

With A-Weighted Filter (Mono—See Figure 29) 117 dB

Dynamic Range (20 Hz to 20 kHz, –60 dB Input)

No Filter (Stereo) 107 112 dB

No Filter (Mono—See Figure 29) 115 dB

With A-Weighted Filter (Stereo) 110 114 dB

With A-Weighted Filter (Mono—See Figure 29) 117 dB

Total Harmonic Distortion + Noise (Stereo) –94 –102 dB

Total Harmonic Distortion + Noise (Mono—See Figure 29) –105 dB

Total Harmonic Distortion + Noise (Stereo) V
Total Harmonic Distortion + Noise (Stereo) V

= –20 dB –92 dB

O

= –60 dB –52 dB

O

Analog Outputs

Differential Output Range (± Full Scale) 5.6 V p-p

Output Capacitance at Each Output Pin 2 pF

Out-of-Band Energy (0.5 × F

to 100 kHz) –90 dB

S

CMOUT 2.37 V
DC Accuracy

Gain Error –10 ±2.0 +10 %
Interchannel Gain Mismatch –0.15 ±0.015 +0.15 dB
Gain Drift 150 250 ppm/°C

DC Offset –50 mV

Interchannel Crosstalk (EIAJ Method) –120 dB

Interchannel Phase Deviation ±0.1 Degrees

Mute Attenuation –100 dB

De-Emphasis Gain Error ±0.1 dB

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.

Mode)

S

Min Typ Max Unit

0.00079 %

0.00056 %

DIGITAL I/O (0ⴗC TO 70ⴗC)

Min Typ Max Unit

Input Voltage HI (V
Input Voltage LO (V
Input Leakage (I
Input Leakage (I
High Level Output Voltage (V
Low Level Output Voltage (V

) 2.2 V

IH

) 0.8 V

IL

@ V

IH

IL

= 2.4 V) 10 µA

IH

@ V

= 0.8 V) 10 µA

IL

) IOH = 1 mA 2.0 V

OH

) IOL = 1 mA 0.4 V

OL

Input Capacitance 20 pF

Specifications subject to change without notice.

–2–

REV. 0

AD1852

TEMPERATURE RANGE

Min Typ Max Unit

Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage –55 +150 °C

Specifications subject to change without notice.

POWER

Min Typ Max Unit

Supplies

Voltage, Analog and Digital 4.50 5 5.50 V
Analog Current 33 40 mA
Analog Current—RESET 32 46 mA
Digital Current 20 30 mA
Digital Current—RESET 27 37

Dissipation

Operation—Both Supplies 265 mW
Operation—Analog Supply 165 mW
Operation—Digital Supply 100 mW

Power Supply Rejection Ratio

1 kHz 300 mV p-p Signal at Analog Supply Pins –60 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins –50 dB

Specifications subject to change without notice.

DIGITAL FILTER CHARACTERISTICS

Sample Rate (kHz) Passband (kHz) Stopband (kHz) Stopband Attenuation (dB) Passband Ripple (dB)

44.1 DC–20 24.1–328.7 110 ±0.0002
48 DC–21.8 26.23–358.28 110 ±0.0002
96 DC–39.95 56.9–327.65 115 ±0.0005

192 DC–87.2 117–327.65 95 +0/–0.04 (DC–21.8 kHz)

+0/–0.5 (DC–65.4 kHz)
+0/–1.5 (DC–87.2 kHz)

Specifications subject to change without notice.

GROUP DELAY

Chip Mode Group Delay Calculation F

INT8x Mode 5553/(128 × F
INT4x Mode 5601/(64 × F

) 48 kHz 903.8 µs

S

) 96 kHz 911.6 µs

S

S

Group Delay Unit

INT2x Mode 5659/(32 × FS) 192 kHz 921 µs

Specifications subject to change without notice.

DIGITAL TIMING (Guaranteed Over 0ⴗC to 70ⴗC, AVDD = DVDD = +5.0 V ⴞ 10%)

Min Unit

t

DMP

t

DML

t

DMH

t

DBH

t

DBL

t

DBP

t

DLS

t

DLH

t

DDS

t

DDH

t

RSTL

*Higher MCLK frequencies are allowable when using the on-chip Master Clock Autodivide Feature.
Specifications subject to change without notice.

MCLK Period (FMCLK = 256 × FL/RCLK)* 54 ns
MCLK LO Pulsewidth (All Modes) 0.4 × t
MCLK HI Pulsewidth (All Modes) 0.4 × t

DMP

DMP

ns

ns
BCLK HI Pulsewidth 20 ns
BCLK LO Pulsewidth 20 ns
BCLK Period 60 ns
L/RCLK Setup 20 ns
L/RCLK Hold (DSP Serial Port Mode Only) 5 ns
SDATA Setup 5 ns
SDATA Hold 10 ns
RST LO Pulsewidth 15 ns

REV. 0

–3–

AD1852

WARNING!

ESD SENSITIVE DEVICE

TOP VIEW

(Not to Scale)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8

9
10
11
12
13
14

AD1852

FILTR

OUTR–

OUTR+

AGND

96/48

DEEMP

ZEROR

DGND
MCLK

CLATCH

CCLK

192/48

NC

CDATA

AGND

OUTL–

OUTL+

AVDD

FILTB

IDPM1

IDPM0

DVDD
SDATA
BCLK
LRCLK

ZEROL

MUTE

RESET

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

Min Max Unit

DV

to DGND –0.3 6 V

DD

to AGND –0.3 6 V

AV

DD

Digital Inputs DGND – 0.3 DV
Analog Outputs AGND – 0.3 AV

+ 0.3 V

DD

+ 0.3 V

DD

AGND to DGND –0.3 0.3 V
Reference Voltage (AV

+ 0.3)/2 V

DD

Soldering 300 °C

10 sec

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

PACKAGE CHARACTERISTICS

Min Typ Max Unit

θ

(Thermal Resistance 109 °C/W

JA

[Junction-to-Ambient])

(Thermal Resistance 39 °C/W

θ

JC

[Junction-to-Case])

ORDERING GUIDE

Model Temperature Package Description Package Option

AD1852JRS 0°C to 70°C 28-Lead Shrink Small Outline Package (SSOP) RS-28
AD1852JRSRL 0°C to 70°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 on 13" Reels

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1852 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

AD1852

PIN FUNCTION DESCRIPTIONS

Pin Input/Output Pin Name Description

1 I DGND Digital Ground.
2 I MCLK Master Clock Input. Connect to an external clock source at either 256 F

, 768 FS, or 1024 FS.

512 F

S

3 I CLATCH Latch Input for Control Data. This input is rising-edge sensitive.
4 I CCLK Control Clock Input for Control Data. Control input data must be valid on the rising

edge of CCLK. CCLK may be continuous or gated.

5 I CDATA Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used

for specifying channel-specific attenuation and mute.

6 NC No Connect.
7 I 192/48 Selects 48 kHz (LO) or 192 kHz Sample Frequency.
8 O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal

input for more than 1024 LR Clock Cycles.

9 I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used

to impose a 50 µs/15 µs response characteristic on the output audio spectrum at an

assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be
selected via SPI control register.

10 I 96/48 Selects 48 kHz (LO) or 96 kHz Sample Frequency.
11, 15 I AGND Analog Ground.
12 O OUTR+ Right Channel Positive Line Level Analog Output.
13 O OUTR– Right Channel Negative Line Level Analog Output.
14 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-

ence with parallel 10 µF and 0.1 µF capacitors to the AGND.

16 O OUTL– Left Channel Negative Line Level Analog Output.
17 O OUTL+ Left Channel Positive Line Level Analog Output.
18 I AVDD Analog Power Supply. Connect to Analog 5 V Supply.

19 FILTB Filter Capacitor Connection. Connect 10 µF capacitor to AGND (Pin 15).

20 I IDPM1 Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
21 I IDPM0 Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
22 O ZEROL Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal

input for more than 1024 LR Clock Cycles.

23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
24 I RESET Reset. The AD1852 is reset on the rising edge of this signal. The serial control port

registers are reset to the default values. Connect HI for normal operation.

25 I L/RCLK Left/Right Clock Input for Input Data. Must run continuously.
26 I BCLK Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a

burst fashion.

27 I SDATA Serial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos

complement data per channel.

28 I DVDD Digital Power Supply Connect to digital 5 V supply.

, 384 FS,

S

Table I. Serial Data Input Mode

IDPM1 (Pin 20) IDPM0 (Pin 21) Serial Data Input Format

0 0 Right-Justified
01 I
1 0 Left-Justified
1 1 DSP

2

S-Compatible

REV. 0

–5–

AD1852

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

L/RCLK

INPUT

BCLK

INPUT

LEFT CHANNEL

LSB

MSB

LSBMSB–2MSB–1 LSB+2 LSB+1

RIGHT CHANNEL

MSB–1

MSB–2

MSB

LSB+2

LSB+1

LSB

Figure 1. Right-Justified Mode

MSB

LEFT CHANNEL

MSB–2MSB–1 LSB+2 LSB+1 LSB MSB–2MSB–1MSB LSB+2 LSB+1 LSB MSB

RIGHT CHANNEL

Figure 2. I2S-Justified Mode

LEFT CHANNEL

RIGHT CHANNEL

SDATA

INPUT

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

MSB

LSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1MSB

MSB–2MSB–1 LSB+2 LSB+1 LSB MSB–2MSB–1MSB LSB+2 LSB+1 LSB MSB–1MSB

Figure 3. Left-Justified Mode

LEFT CHANNEL

MSB–1 LSB+2 LSB+1 LSB MSB–1 LSB+2 LSB+1 LSBMSB MSB–1MSB

MSB

RIGHT CHANNEL

Figure 4. Left-Justified DSP Mode

LEFT CHANNEL

RIGHT CHANNEL

Figure 5. 32 × FS Packed Mode

–6–

REV. 0

AD1852

OPERATING FEATURES
Serial Data Input Port

The AD1852’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero (default
at power-up). To control the serial mode using the SPI mode
select bits, the external mode control pins should be grounded.

In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24. Extra
bits will not cause an error, but they will be truncated internally.
In the right-justified mode, control register Bits 8 and 9 are used
to set the wordlength to 16 bits, 20 bits, or 24 bits. The default
on power- up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4, and 5) should be tied LO.

Serial Data Input Mode

The AD1852 uses two multiplexed input pins to control the mode
configuration of the input data port mode. See Table I.

Figure 1 shows the right-justified mode (16 bits shown). L/RCLK
is HI for the left channel, LO for the right channel. Data is valid
on the rising edge of BCLK.

In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI wordlength control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial

BCLK

L/RCLK

t

DBH

t

DBL

t

DLS

t

DBP

port will begin to accept data starting at the eighth bit clock
pulse after the L/RCLK transition. When the wordlength con­trol bits are set to 20-bit mode, data is accepted starting at
the twelfth-bit clock position. In 16-bit mode, data is accepted
starting at the sixteenth-bit clock position. These delays are
independent of the number of bit clocks per frame, and therefore
other data formats are possible using the delay values described
above. For detailed timing, see Figure 6.

Figure 2 shows the I

2

S mode. L/RCLK is LO for the left chan-

nel and HI for the right channel. Data is valid on the rising edge
of BCLK. The MSB is left-justified to an L/RCLK transition
but with a single BCLK period delay. The I

2

S mode can be used

to accept any number of bits up to 24.
Figure 3 shows the left-justified mode. L/RCLK is HI for the

left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/RCLK
transition, with no MSB delay. The left-justified mode can
accept any wordlength up to 24 bits, and any number of bit clocks
from two times the word length to 64 bit clocks per frame.

Figure 4 shows the DSP serial port mode. L/RCLK must pulse
HI for at least one bit clock period before the MSB of the left
channel is valid, and L/RCLK must pulse HI again for at least
one bit clock period before the MSB of the right channel is valid.
Data is valid on the falling edge of BCLK. The DSP serial port
mode can be used with any wordlength up to 24 bits.

In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first L/RCLK pulse, and
that synchronism is maintained from that point forward.

RIGHT-JUSTIFIED

REV. 0

SDATA

LEFT-JUSTIFIED

MODE

SDATA

2

I

S-JUSTIFIED

MODE

SDATA

MODE

t

DDS

MSB

t

DDH

8-BIT CLOCKS

(24-BIT DATA)

12-BIT CLOCKS

(20-BIT DATA)

16-BIT CLOCKS

(16-BIT DATA)

MSB-1

t

DDS

MSB

t

DDH

Figure 6. Serial Data Port Timing

–7–

t

DDS

MSB

t

DDH

t

DDS

LSB

t

DDH

AD1852

Table II.

Nominal Input Internal Sigma-

Chip Mode Allowable Master Clock Frequencies Sample Rate Delta Clock Rate

INT8× Mode 256 × F
INT4× Mode 128 × FS, 192 × FS, 256 × FS, 384 × FS, 512 × F
INT2× Mode 64 × FS, 96 × FS, 128 × FS, 192 × FS, 256 × F

, 384 × FS, 512 × FS, 768 × FS, 1024 × F

S

S

S

S

48 kHz 128 × F
96 kHz 64 × F
192 kHz 32 × F

S

S

S

Note that the AD1852 is capable of a 32 × F

BCLK frequency

S

“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to the opposite L/RCLK
transition. L/RCLK is HI for the left channel, and LO for the
right channel. Data is valid on the rising edge of BLCK. Packed
mode can be used when the AD1852 is programmed in right­justified or left-justified mode. Packed mode is shown is Figure 5.

Master Clock Autodivide Feature

The AD1852 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter­nally sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above. Master clock should be synchronized with L/RCLK but
phase relation between master clock and L/RCLK is not critical.

t

CHD

CDATA

CCLK

CLATCH

t

CCH

t

CCL

D15

D14

t

CSU

Figure 7. Serial Control Port Timing

SPI REGISTER DEFINITIONS

The SPI port allows flexible control of many chip parameters. It is
organized around three registers; a LEFT-CHANNEL VOLUME
register, a RIGHT-CHANNEL VOLUME register, and a
CONTROL register. Each WRITE operation to the AD1852
SPI control port requires 16 bits of serial data in MSB-first format.
The bottom two bits are used to select one of three registers,
and the top 14 bits are then written to that register. This allows
a write to one of the three registers in a single 16-bit transaction.

The SPI CCLK signal is used to clock in the data. The incom­ing data should change on the falling edge of this signal. At the
end of the 16 CCLK periods, the CLATCH signal should rise
to clock the data internally into the AD1852.

D0

t

CLH

t

CLL

t

CLSU

–8–

REV. 0

Table III. SPI Digital Timing

AD1852

Min Unit

t

CCH

t

CCL

t

CSU

t

CHD

t

CLL

t

CLH

t

CLSU

CCLK HI Pulsewidth 40 ns
CCLK LOW Pulsewidth 40 ns
CDATA Setup Time 10 ns
CDATA Hold Time 10 ns
CLATCH LOW Pulsewidth 10 ns
CLATCH HI Pulsewidth 10 ns

CLATCH Setup Time 4 ×

t

MCLK

ns

Register Addresses

The lowest two bits of the 16-bit input word are decoded as fol­lows to set the register that the upper 14 bits will written into.

VOLUME LEFT AND VOLUME RIGHT REGISTERS

A write operation to the left or right volume registers will acti­vate the “autoramp” clickless volume control feature of the
AD1852. This feature works as follows. The upper 10 bits of the
volume control word will be incremented or decremented by 1 at
a rate equal to the input sample rate. The bottom four bits are
not fed into the autoramp circuit and thus take effect immediately.
This arrangement gives a worst-case ramp time of about 20 ms
for step changes of more than 60 dB, which has been deter­mined by listening tests to be optimal in terms of preventing the
perception of a “click” sound on large volume changes. See Fig­ure 8 for a graphical description of how the volume changes
as a function of time.

The 14-bit volume control word is used to multiply the signal,
and therefore the control characteristic is linear, not dB. A constant
dB/step characteristic can be obtained by using a lookup table
in the microprocessor that is writing to the SPI port.

The volume

word is unsigned (i.e., 0 dB is 11 1111 1111 1111).

Table IV.

Bit 1 Bit 0 Register

0 0 Volume Left
1 0 Volume Right
0 1 Control Register

0

–60

LEVEL – dB

0

–60

20ms

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

TIME

Figure 8. Smooth Volume Control

SPI Timing

The SPI port is a 3-wire interface with serial data (CDATA),
serial bit clock (CCLK), and data latch (CLATCH). The
data is clocked into an internal shift register on the rising
edge of CCLK. The serial data should change on the falling
edge of CCLK and be stable on the rising edge of CCLK.
The rising edge of CLATCH is used internally to latch the par­allel data from the serial-to-parallel converter. This rising edge
should be aligned with the falling edge of the last CCLK pulse
in the 16-bit frame. The CCLK can run continuously between
transactions.

Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the L/RCLK after the
CLATCH write pulse as shown in Figure 7.

Mute

The AD1852 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (data11) HI. The
AD1852 has been designed to minimize pops and clicks when
muting and unmuting the device by automatically “ramping”
the gain up or down. When the device is unmuted, the volume
returns to the value set in the volume register.

REV. 0

–9–

AD1852

Table V.

Bit 11 Bit 10 Bit 9:8 Bit 7 Bit 6 Bit 5:4 Bit 3:2

INT2× Mode INT4× Mode Number of Reset. Soft Mute OR’d Serial Mode OR’d De-Emphasis Filter

OR’d with Pin 7 OR’d with Pin 10 Bits in Right- Default = 0 with Pin. with Mode Pins. Select.
(192/48). (96/48). Justified Serial Default = 0 IDPM1:IDPM0 0:0 No Filter
Default = 0 Default = 0 Mode. 0:0 Right-Justified 0:1 44.1 kHz Filter

0:0 = 24 0:1 I
0:1 = 20 1:0 Left-Justified 1:1 48 kHz Filter
1:0 = 16 1:1 DSP Mode Default = 0:0
Default = 0:0 Default = 0:0

2

S 1:0 32 kHz Filter

Control Register

Table V shows the functions of the control register. The control
register is addressed by having an ‘01’ in the bottom two bits of
the 16-bit SPI word. The top 14 bits are then used for the con­trol register.

De-Emphasis

The AD1852 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard

“redbook” 50 µs/15 µs emphasis response curve. Three curves

are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sam­pling rates. The external “DEEMP” pin (Pin 9) turns on the

44.1 kHz de-emphasis filter. The other filters may be selected by
writing to Control Bits 2 and 3 in the control register. If the SPI
port is used to control the de-emphasis filter, the external DEEMP
pin should be tied LO.

Output Impedance

The output impedance of the AD1852 is 65 Ω ± 30%.

Reset

The AD1852 may be reset either by a dedicated hardware pin
(RESET, Pin 24) or by software, via the SPI control port. While
reset is active, normal operation of the AD1852 is suspended and

the outputs assume midscale values. The AD1852 should always
be reset at power up. The RESET function should be active for
a minimum of 64 master clock periods. When the RESET func­tion becomes inactive, normal operation will continue after a
delay equal to the group delay plus three MCLK periods.

Using the RESET pin, the internal registers will be set to their
default values, when the RESET pin is active low. Default
operation will then be enabled when the RESET pin is raised.
Alternatively, the internal registers can be reset to their default
values by setting Bit 7, of the internal control register, high.
When Bit 7 is reset low, default operation will continue. The
software reset differs from the hardware reset because the soft
reset does not affect the values stored in the SPI registers.

Control Signals

The IDPM0 and IDPM1 control inputs are normally connected
HI or LO to establish the operating state of the AD1852. They
can be changed dynamically (and asynchronously to L/RCLK
and the master clock), but it is possible that a click or pop sound
may result during the transition from one serial mode to another.
If possible, the AD1852 should be placed in mute before such a
change is made.

–10–

REV. 0

Typical Performance Characteristics–

FREQUENCY – kHz

0

ATTENUATION – dB

–60

–100

–160

–20

–40

–80

–120

–140

0 150 20050 100 250 300 350

AD1852

Figures 9–14 show the calculated frequency response of the
digital interpolation filters. Figures 15–26 show the performance
of the AD1852 as measured by an Audio Precision System 2
Cascade. For the wideband plots, the noise floor shown in the
plots is higher than the actual noise floor of the AD1852. This is

0.001

0.0008

0.0006

0.0004

0.0002

0

dB
–0.0002

–0.0004

–0.0006

–0.0008

–0.001

0

21012141620

468 18

FREQUENCY – kHz

Figure 9. Passband Response 8× Mode, 48 kHz Sample
Rate

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–10dB5 10152025303540

FREQUENCY – kHz

Figure 10. 44 kHz Passband Response 4× Mode, 96 kHz
Sample Rate

caused by the higher noise floor of the “High Bandwidth” ADC
used in the Audio Precision measurement system. The two-tone
test shown in Figure 17 is per the SMPTE standard for measur­ing Intermodulation Distortion.

Figure 12. Complete Response, 8× Mode, 48 kHz
Sample Rate

0

–20

–40

–60

–80

dB

–100

–120

–140

–160

50 100 250

0

150 200

FREQUENCY – kHz

300

Figure 13. Complete Response, 4× Mode, 96 kHz
Sample Rate

2.0

1.5

1.0

0.5

Figure 11. 88 kHz Passband Response 2× Mode, 192 kHz
Sample Rate

REV. 0

0

dB

–0.5

–1.0

–1.5

–2.0

10 20 30 40 50 60 70 80

0

FREQUENCY – kHz

–11–

0

–20

–40

–60

–80

dB

–100

–120

–140

–160

0 150 20050 100 250

FREQUENCY – kHz

Figure 14. Complete Response, 2× Mode, 192 kHz
Sample Rate

AD1852

FREQUENCY – kHz

dBr

–130

–140

–150

–160

–120

–110

–100

–90

0246810121416182022

FREQUENCY – kHz

dBr

–130
–140
–150

–120

–110

–100

–90

0 2 4 6 8 10 12 14 16 18 20 22

–80

–70

–60

–50

–40

–30

–20

–10

0

–50

–60

–70

–80

dBr

–90

–100

–110

–120

10

100 1k

FREQUENCY – Hz

10k

20k

Figure 15. THD vs. Frequency Input @ –3 dBFS, SR 48 kHz

2

0

–2

–4

dBr

–6

0
–10
–20

–30
–40
–50

dB

–60
–70
–80
–90

–100
–110

–120 –100 –80 –60 –40 –20 0

dBFS

Figure 18. THD + N Ratio vs. Amplitude Input 1 kHz,
SR 48 kS/s, 24-Bit

–8

–10

–12

10

100 1k 10k

FREQUENCY – Hz

Figure 16. Normal De-Emphasis Frequency Response
Input @ –10 dBFS, SR 48 kHz

–10

–30

–50

–70

dBr

–90

–110

–130

–150

0246810121416182022

FREQUENCY – kHz

Figure 17. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS

20k

Figure 19. Noise Floor for Zero Input, SR 48 kHz

Figure 20. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz,
SR 48 kHz

–12–

REV. 0

0

FREQUENCY – kHz

dBr

–130
–140
–150

–120

–110

–100

–90

0246810121416182022

–80

–70

–60

–50

–160

FREQUENCY – kHz

0

–100

12020

dBr

40 60 80 100

–10

–40

–70
–80
–90

–20
–30

–50
–60

–110
–120
–130
–140

–20

–40

–60

dBr

–80

–100

–120

–140

–140 –120 –100 –60 –40 –20 0–80

dBFS

Figure 21. Linearity vs. Amplitude Input 200 Hz,
SR 48 kS/s, 24-Bit Word

AD1852

Figure 24. Dynamic Range for 1 kHz @ –60 dBFS,
Triangular Dithered Input

–64

–66

–68

–70

dBr

–72

–74

–76

10

100

FREQUENCY – Hz

Figure 22. Power Supply Rejection vs. Frequency
AV

5 V DC + 100 mV p-p AC

DD

0

–10
–20
–30

–40
–50
–60
–70

dBr

–80

–90
–100
–110
–120
–130
–140

40 60 80 100

FREQUENCY – kHz

Figure 23. Wideband Plot, 15 kHz Input, 8× Interpolation,
SR 48 kHz

REV. 0

1k 10k

20k

0
–10
–20

–30
–40
–50
–60
–70
–80

dBr

–90

–100
–110
–120
–130
–140
–150
–160

10 15 20 25

305

35 40 45 50 55 60 65 70 75 80

FREQUENCY – kHz

Figure 25. Wideband Plot, 75 kHz Input, 2× Interpolation,
SR 192 kHz

12020

Figure 26. Wideband Plot, 37 kHz Input, 4× Interpolation,
SR 96 kHz

–13–

AD1852

10kVR210kVR110kV

JP11

MCLK/SR SEL

I/F MODE IDPM1 IDPM0
RJ, 16-BIT 0 0

2

I

S01
RJ, 20-BIT 1 0
RJ, 24-BIT 1 1

JP21

I/F

MODE

R3

DVDD

R4

10kVR510kV

SDATA
LRCLK

DEEMP

MUTE

CLATCH

CCLK

CDATA

RESET

DGND

SCLK

MCLK

DVDD

SELECT RATE 2xMCLK 384/256 96/48 MCLK
SPDIF 44.1 0 0 0 11,2896

DIRECT 48.0 0 0 0 11,2880
DIRECT 96.0 0 0 1 12,2880

100nF

96/48

192/48

NC

SDATA
LRCLK

SCLK
MCLK

IDPM0
IDPM1

DEEMP
MUTE

CLATCH
CCLK

ZR

ZL

CDATA

ZEROR
ZEROL

RESET

1

ZL

MCLK/SR SELECT

AD1852 STEREO DAC

DVDD

C3

AD1852JRS

DGND

FB1

600Z

C4

100nF

2

U2A

HC04

U1

AVDD

AVDDDVDD

AGND

R6
221V

100nF

CR1
ZERO
LEFT

C2

OUTL+

OUTL–

OUTR+

OUTR–

AGND

FILTR
FILTB

R7
221V

CR2
ZERO
RIGHT

C8
10mF

1.96kV

R16

1.87kV

1.87kV

1.96kV

1.96kV

R18

1.87kV

1.87kV

1.96kV

OUTPUT BUFFERS & LP FILTERS

R8

R10

R12

R14

C7
10mF

C9
220pF
NP0

C10
220pF
NP0

C11
220pF
NP0

C12
220pF
NP0

R17

R11

R13

R19

R15

C1
100nF

R9

1.96kV
C14

1nF
NP0

C13
1nF
NP0

1.96kV

1.96kV
C17

1nF
NP0

C16
1nF
NP0

1.96kV

U3B
SSM2135

R20

200V

C15

10nF

NP0

3RD ORDER LP BESSEL FILTER
CORNER FREQUENCY: 75kHz
GROUP DELAY: ~3.5ms

+AV

CC

U3A

C5

SSM2135

100nF

R21

200V

C18

10nF

C6

NP0

100nF

–AV

CC

J11

J21

LEFT
OUT

RIGHT
OUT

U2B

4

3

ZR

HC04

Figure 27. AD1852 DAC, Output Buffers, and LP Filters

–14–

REV. 0

SDATA

BCLK

LRCLK

2

S LEFT/RIGHT

I

DATA SEPARATOR

AND INVERTER

MCLK

SDATA
LRCLK
BCLK

AD1852

SDATA
LRCLK
BCLK

AD1852

AD1852

R5

R1

08

1808

08

1808

3.01kV

3.01kV

3.01kV

3.01kV

1.5nF

L+

L

L–

R+

L

R–

L+

R

L–

R+

R

R–

R2

C7

1.5nF

R3

R4

R7

3.01kV
R8

3.01kV
C9

R9

3.01kV
R10

3.01kV

3.01kV

R6

3.01kV

R11

3.01kV

R12

3.01kV

R13

1.00kV
C8

1.5nF

R14

1.00kV

R15

1.00kV
C10

1.5nF

R16

1.00kV

C2
270pF

C2
270pF

C3
270pF

C4
270pF

AD797

AD797

R17

549V

R18

549V

R19

53.6kV

R20

53.6kV

C5

2.2nF

C6

2.2nF

1

0

1

0

I2S INPUT TO

DATA SEPARATOR

DATA SEPARATOR

OUTPUT

LRCLK

SDATA

LRCLK

LSDATA

RDATA

Ln Rn

Ln

Rn

Figure 28. Mono Application Circuit

Ln+1

Ln

Rn

Rn+1

Ln+1

Rn+1

Ln+2

Ln+1

Rn+1

Rn+2

Ln+2

Rn+2

Ln+2

Rn+2

REV. 0

–15–

AD1852

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Shrink Small Outline Package (SSOP)

(RS-28)

0.407 (10.34)

0.397 (10.08)

28 15

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

PIN 1

0.0256
(0.65)

BSC

0.015 (0.38)

0.010 (0.25)

0.066 (1.67)

SEATING

PLANE

0.212 (5.38)

0.205 (5.21)

141

0.07 (1.79)

0.009 (0.229)

0.005 (0.127)

8°
0°

C3770–8–1/00 (rev. 0)

0.03 (0.762)

0.022 (0.558)

–16–

PRINTED IN U.S.A.

REV. 0