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AD120
Preliminary 3-Level / 258 Outputs TFT LCD Gate Driver
Document Title
3-Level / 258 Outputs TFT LCD Gate Driver
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue August 10, 2001 Preliminary
Important Notice:
AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or
service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to
be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMIC
products in such applications is understood to be fully at the risk of the customer.
PRELIMINARY (August, 2001, Version 0.0) AMIC Technology, Inc.
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AD120
Preliminary 3-Level / 258 Outputs TFT LCD Gate Driver
Features
n TFT LCD gate driver
n 3-level / 258 outputs
n 40V max. for each output
n -15V min. for each output
n 2.7V~3.6V logic input/output level
AD120 is a gate driver for TFT LCD panel. There are 258 outputs in the chip. Three-level output allows voltage correction for
better switching noise rejection. It can be used for XGA / SXGA panels.
n Bi-directional data shift control
n Output waveform control
n TCP available
Block Diagram
ST1
ST2
ST1X
ST2X
Shift Register
R/L
CP
.........
XOFF
XON
OGW
Decoder
.........
VH
VOFF
VL
VDD
VSS
OUT0 OUT1 OUT2
Output
.........
.........
OUT255 OUT256 OUT257
PRELIMINARY (August, 2001, Version 0.0) 1 AMIC Technology, Inc
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TCP Pinout
VL
VOFF
VH
ST1
ST2
VSS
CP
VDD
XOFF
XON
R/L
OGW
ST2X
ST1X
VH
VOFF
VL
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AD120
AD120
18
OUT0
19
OUT1
20
OUT2
21
OUT3
22
OUT4
......................................................................
.......................................................................
271
OUT253
272
OUT254
273
OUT255
274
OUT256
275
OUT257
PRELIMINARY (August, 2001, Version 0.0) 2 AMIC Technology, Inc
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Input/Output Pin Function
R
R
R
R
R
Pin No. Symbol I/O Description
11 CP I Clock pulse
7
/L
Right / left direction control for shift register
I
When
.… output257.
/L is LOW, data are shifted to the right, or ST1 / ST2 output0 output1
When R/L is HIGH, data are shifted to the left, or ST1X / ST2X output257
output256 .... output0.
8
XON
I
to force all the outputs to VH voltage.
XON
It is not synchronous to CP.
AD120
4,5,
13,14
18 - 275
12
10
3, 15
1, 17
2, 16
9
6
ST1, ST2,
ST1X, ST2X
OUT257
XOFF
OGW
OUT0~
VSS
VDD
VH
VL
VOFF
I
I Output Gate pulse Width to select output_waveform format.
I/O
O
PWR
PWR
PWR
PWR
PWR
to force all the outputs to VOFF voltage.
XOFF
It is not synchronous to CP.
When
as outputs .
The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses.
When
as outputs.
The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses.
Output drivers
These outputs are synchronized to CP pulses.
The output format and voltage level are controlled by OGW,
ST2, ST1X / ST2X and
Reference voltage
Supply voltage for logic operation
VDD and VSS are voltage levels of input / output logic signals
High voltage for output drivers
Low voltage for output drivers
OFF voltage for output drivers
/L is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined
/L is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined
/L correspondingly as shown in the diagram.
XON, XOFF
, ST1 /
PRELIMINARY (August, 2001, Version 0.0) 3 AMIC Technology, Inc
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AD120
R
R
R
Description
Operation
Output signals OUT0~OUT257 are used for control of the TFT gates of the LCD panel. A bi-directional shift register is
implemented to sequentially output signals OUT0~OUT257. A clock pulse CP is applied to the bi-directional shift register and
the direction of the register is controlled by
When
The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the
diagram. The outputs of the starting signals ST1X / ST2X switch accordingly after 256 CP pulses following start of the shift
register which allows expansion of the outputs by cascading more devices.
When
OUT0. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the
diagram. The outputs of the starting signals ST1/ST2 switch accordingly after 256 CP pulses following start of the shift register
which allows expansion of the outputs by cascading more devices.
3-Level Output
VH - VL = 40V(max.)
VOFF - VL = 0~10V
VH - VSS = 17~28V
/L is LOW and either starting signal ST1 or ST2 goes to HIGH, the shift register starts shifting from OUT0 to OUT257.
/L is HIGH and either starting signal ST1X or ST2X goes to HIGH, the shift register starts shifting from OUT257 to
VH
/L signal.
OUT
VDD
VSS
VOFF
VL
Level
PRELIMINARY (August, 2001, Version 0.0) 4 AMIC Technology, Inc
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Operation Diagram 1 (R/L = L, OGW = L)
1 2 3 256 257
AD120
CP
ST1
ST2
OUT0
OUT1
OUT2
OUT3
~
~
V
DD
~
V
SS
V
DD
V
SS
V
H
V
OFF
V
L
V
H
V
OFF
V
L
V
H
V
OFF
V
L
V
H
V
OFF
V
L
V
H
~
~
~
~
~
~
~
~
~
OUT256
OUT257
ST1X
ST2X
V
OFF
V
L
V
H
V
OFF
V
L
V
DD
V
SS
V
DD
V
SS
~
~
~
~
~
~
~
~
PRELIMINARY (August, 2001, Version 0.0) 5 AMIC Technology, Inc
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Operation Diagram 2 (R/L = L, OGW = H)
1 2 3
CP
ST1
ST2
VDD
XOFF
VSS
VDD
XON
VSS
VH
VOFF
OUT0
VL
VH
AD120
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VOFF
VL
OUT8
PRELIMINARY (August, 2001, Version 0.0) 6 AMIC Technology, Inc
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AD120
Table 1. Function of
XON
L X VH
H L VOFF
H H Table2
* The outputs are asynchronous to CP.
XOFF
XON
and
XOFF
OUT0~OUT257
Table 2. Control of OUT1~OUT256
(
(R/L = L)
(R/L = H)
L L X VOFF
L H X VL
H L X VL
* The outputs are synchronous to CP.
ST1 ST2
ST1X ST2X
H H
OGW OUT1~OUT256
L VH
H
Table 3. Control of OUT0 and OUT257
(
(R/L = L)
(R/L = H)
L L VOFF
L H VL
H L VL
H H VL
* The outputs are synchronous to CP.
ST1 ST2 OUT0
ST1X ST2X OUT257
= H,
XON
VH (CP = “L”)
VL (CP = “H”)
= H,
XON
XOFF
XOFF
= H)
= H)
PRELIMINARY (August, 2001, Version 0.0) 7 AMIC Technology, Inc
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Absolute Maximum Ratings Over Operating Free-air Temperature Range
Parameter Symbol Ratings Unit
Supply Voltage VDD -0.3 ~ +7.0 V
Supply Voltage VH -0.3 ~ 42.0 V
Supply Voltage VL -20.0 ~ +0.3 V
Supply Voltage VOFF VL-0.3 ~ VL+11.0 V
Supply Voltage VH - VL -0.3 ~ 42.0 V
Input Voltage VIN -0.3 ~ VDD+0.3 V
Storage Temperature Tstg -55 ~ 125 °C
Power_on Sequence and Voltage Levels
VH
VDD
AD120
Out0~Out257
Logic Signal
VSS
VOFF
VL
VDD
VSS
Operating Voltage Range
Parameter Symbol Min. Typ. Max. Unit
Supply Voltage VDD 2.7 3.3 3.6 V
Supply Voltage VH 17 - 28 V
Supply Voltage VL -15 - -5 V
Supply Voltage VOFF - VL 0 - 10.0 V
Supply Voltage VH - VL 22 - 40 V
Clock Frequency fCP - - 100 KHz
Operating Free-air Temperature Ta -20 - +75 °C
PRELIMINARY (August, 2001, Version 0.0) 8 AMIC Technology, Inc
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AD120
DC Charactertics
(VDD = 2.7~3.6V, Ta = -20~75°C)
Parameter Symbol Condition Min. Max. Unit Applicable Pin Note
Low Level Input Voltage VIL VSS 0.2 X VDD V All input pins
High Level Input Voltage VIH 0.8 X VDD VDD V All input pins
Low Level Output Voltage VOL IOL = 40µA VSS VSS + 0.4 V
High Level Output Voltage VOH IOH = 40µA VDD -0.4 VDD V
Output Resistance (1) RL VOUT = VL + 0.5 1000 Ù OUT0~OUT257 1
Output Resistance (2) ROFF VOUT = VOFF + 0.5 1000 Ù OUT0~OUT257 1
Output Resistance (3) RH VOUT = VH - 0.5 1000 Ù OUT0~OUT257 1
Input Current II VI = VDD / VSS -5.0 +5.0 µA All input pins
Operating Current (1) IDD 1500 µA VDD 1, 2
Operating Current (2) IH 100 µA VH 1, 2
Notes:
1. VH = 25V, VOFF = 0V, VL = -10V
2. CP = 50KHz
AC Charactertics
(VDD = 2.7~3.6V, Ta = -20~75°C)
Parameter Symbol Condition Min. Max. Unit
Clock Frequency fCP 100 KHz
CP High Pulse Width tCPH 1 µs
CP Low Pulse Width tCPL 4 µs
Input Rise Time tr 10% ~ 90% 50 ns
Input Fall Time tf 90% ~ 10% 50 ns
Gate Off Time tWOFF 1 µs
Data Setup Time tSU 700 ns
Data Hold Time thd 700 ns
Delay Time 1 tpd1 CL = 20pF 800 ns
Delay Time 2 tpd2 CL = 300pF 1000 ns
Delay Time 3 tpd3 CL = 300pF 1000 ns
Delay Time 4 tpd4 CL = 300pF 1000 ns
Delay Time 5 tpd5 CL = 300pF 1000 ns
ST1, ST2,
ST1X, ST2X
PRELIMINARY (August, 2001, Version 0.0) 9 AMIC Technology, Inc
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AD120
Timing Waveform
0.5 x V
CP
t
CPH
DD
0.5 x V
DD
DD
ST1,
ST2
Input
0.5 x V
STX1,
STX2
Output
OUT0~OUT257
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------(OGW = H)
0.5 x VDD
CP
0.5 x VDD
1
t
CPL
0.5 x V
DD
t
SU
tpd2 tpd2
0.5 x V
thd
0.5 x V
80%
DD
2 256
0.5 x V
DD
DD
20%
DD
0.5 x V
~
~
~
~
~
~
~
~
0.5 x V
257
0.5 x V
DD
tpd1 tpd1
50%
DD
0.5 x V
DD
0.5 x V
50%
DD
OUT0~257
tpd2 tpd2
80%
20%
tpd2
tpd2
80%
tpd2
80%
20% 20%
VH
VOFF
VL
tpd2
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------(OGW = L)
0.5 x VDD
CP
tpd2 tpd2 tpd2 tpd2
OUT0~OUT257
0.5 x VDD 0.5 x VDD 0.5 x VDD
20%
80%
20%
80%
V
H
VOFF
VL
0.5 x VDD
tpd2
20%
PRELIMINARY (August, 2001, Version 0.0) 10 AMIC Technology, Inc
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AD120
Timing Waveform (continued)
XOFF
0.5 x V
DD
twOFF
tpd3 tpd3
OUT0~OUT257
20% 20%
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.5 x V
DD
80%80%
V
OFF
V
H
V
L
OUT0~OUT257
XON
0.5 x V
DD
tpd4
20%
0.5 x V
tpd4
DD
80%
V
H
PRELIMINARY (August, 2001, Version 0.0) 11 AMIC Technology, Inc
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Ordering Information
Part No. Package
AD120
AD120T
TCP
PRELIMINARY (August, 2001, Version 0.0) 12 AMIC Technology, Inc
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