Datasheet AD10465 Datasheet (ANALOG DEVICES)

Dual Channel, 14-Bit, 65 MSPS A/D Converter

A

A3A

A

FEATURES

Dual, 65 MSPS minimum sample rate

Channel-to-channel matching, ±0.5% gain error Channel-to-channel isolation, >90 dB DC-coupled signal conditioning included

Selectable bipolar input voltage range

(±0.5 V, ±1.0 V, ±2.0 V) Gain flatness up to 25 MHz: <0.2 dB 80 dB spurious-free dynamic range Twos complement output format

3.3 V or 5 V CMOS-compatible output levels

1.75 W per channel Industrial and military grade

APPLICATIONS

Phased array receivers Communications receivers FLIR processing Secure communications GPS antijamming receivers Multichannel, multimode receivers

GENERAL DESCRIPTION

The AD10465 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6644 ADCs. Each AD6644 has a dc-coupled amplifier front end including an AD8037 low distortion, high bandwidth amplifier that provides high input impedance and gain and drives the AD8138 singleto-differential amplifier. The AD6644s have on-chip track-andhold circuitry and utilize an innovative multipass architecture to achieve 14-bit, 65 MSPS performance.

FUNCTIONAL BLOCK DIAGRAM

DRAOUT

D0A (LSB)

D1A

D2A

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

12

15

16

17

18

19

20

21

22

23

24

25

28

ENCODEA

AINA38AINA27A

TIMING

29 31 32 33 34 35 36 37 38 39 40 41 42

ENCODEA

1

REF_

IN

6

VREF DROUT

11

14

OUTPUT BUFFERING

3

D11 D12A D13A (MS BA) D0B (LSBB) D 1B D2B D3B D4B D5B D6B D7B D8B

with Analog Input Signal Conditioning

AD10465

The AD10465 uses innovative high density circuit design and laser trimmed, thin film resistor networks to achieve exceptional matching and performance, while still maintaining excellent isolation and providing for significant board area savings.

The AD10465 operates with ±5.0 V supplies for the analog signal conditioning with a separate 5.0 V supply for the analogto-digital conversion and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent encode and analog inputs. The AD10465 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while remaining general-purpose.

The AD10465 is packaged in a 68-lead ceramic leaded chip carrier package, footprint-compatible with the earlier generation AD10242 (12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufacturing is done on the Analog Devices Mil38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (−40°C to +85°C). The AD6644 internal components are manufactured on Analog Devices’ high speed complementary bipolar process (XFCB).

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 65 MSPS.

2. Input amplitude options, user configurable.

3. Input signal conditioning included; both channels matched

for gain.

4. Fully tested/characterized performance.

5. Footprint-compatible family; 68-lead CLCC package.

B3

B2

B1

IN

63

62

VREF DROUT

14

OUTPUT BUFFERING

9

TIMING

5

56

REF_B

DRBOUT

55

52

ENCODEB

51

ENCODEB

D13B (MSBB)

49

48

D12B

47

D11B

46

D10B

45

D9B

02356-001

AD10465

Figure 1.

IN

64

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD10465

REVISION HISTORY

Using the Flexible Input ............................................................ 12

Applying the AD10465.................................................................. 13

Encoding the AD10465 ............................................................. 13

Jitter Considerations .................................................................. 13

Power Supplies............................................................................ 14

Output Loading .......................................................................... 14

Layout Information.................................................................... 14

Evaluation Board............................................................................ 15

Bill Of Materials List for AD10465 Evaluation Board........... 19

Silkscreens ................................................................................... 20

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

3/06—Rev. 0 to Rev. A

Remove AZ Grade..............................................................Universal

Changes to General Description Section ...................................... 1

Changes to Table 1............................................................................ 3

Inserted Test Circuits Section ......................................................... 6

Updates to Ordering Guide........................................................... 24

2001—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD10465

SPECIFICATIONS

AVCC = +5 V; AVEE = –5 V; DVCC = 3.3 V applies to each ADC, unless otherwise noted. All specifications guaranteed within 100 ms of initial power-up, regardless of sequencing.

Table 1.

Test1 Mil AD10465BZ/QML-H Parameter Temp Level Subgroup Min Typ Max Unit

RESOLUTION 14 Bits DC ACCURACY

No Missing Codes Full VI 1, 2, 3 Guaranteed Offset Error 25°C I 1 −2.2 ±0.02 +2.2 % FS Full VI 2, 3 −2.2 ±1.0 +2.2 % FS Offset Error Channel Match Full V −1 ±1.0 +1 % Gain Error2 25°C I 1 −3 −1.0 +1 % FS Full VI 2, 3 −5 ±2.0 +5 % FS

Gain Error Channel Match 25°C I 1 −1.5 ±0.5 +1.5 % Max I 2 −3 ±1.0 +3 % Min I 3 −5 +5 % ANALOG INPUT (AIN)

Input Voltage Range

AIN1 Full V ±0.5 V AIN2 Full V ±1.0 V AIN3 Full V ±2 V

Input Resistance

AIN1 Full IV 12 99 100 101 Ω AIN2 Full IV 12 198 200 202 Ω

AIN3 Full IV 12 396 400 404 Ω Input Capacitance3 25°C IV 12 0 4.0 7.0 pF Analog Input Bandwidth4 Full V 100 MHz

ENCODE INPUT (ENC, ENC)5

Differential Input Voltage Full IV 0.4 V p-p Differential Input Resistance 25°C V 10 kΩ Differential Input Capacitance 25°C V 2.5 pF

SWITCHING PERFORMANCE

Maximum Conversion Rate6 Full VI 4, 5, 6 65 MSPS Minimum Conversion Rate6 Full V 12 20 MSPS Aperture Delay (tA) 25°C V 1.5 ns Aperture Delay Matching 25°C IV 12 250 500 ps Aperture Uncertainty (Jitter) 25°C V 0.3 ps rms ENCODE Pulse Width High 25°C IV 12 6.2 7.7 9.2 ns ENCODE Pulse Width Low 25°C IV 12 6.2 7.7 9.2 ns Output Delay (tOD) Full V 6.8 ns ENCODE, Rising to Data Ready, Rising Delay (T

SNR7 Analog Input @ 4.98 MHz 25°C V 70 dBFS Analog Input @ 9.9 MHz 25°C I 4 69 70 dBFS Full II 5, 6 68 70 dBFS Analog Input @ 19.5 MHz 25°C I 4 68 70 dBFS Full II 5, 6 67 70 dBFS Analog Input @ 32.1 MHz 25°C I 4 67 69 dBFS Full II 5, 6 67 69 dBFS

E_DR

) Full 11.5 ns

Rev. A | Page 3 of 24

AD10465

Test1 Mil AD10465BZ/QML-H Parameter Temp Level Subgroup Min Typ Max Unit

SINAD8

Analog Input @ 4.98 MHz 25°C V 70 dB Analog Input @ 9.9 MHz 25°C I 4 67.5 69 dB Full II 5, 6 67.5 69 dB Analog Input @ 19.5 MHz 25°C I 4 65 68 dB Full II 5, 6 65 68 dB

Analog Input @ 32.1 MHz 25°C I 4 60 63 dB Full II 5, 6 58 61 dB SPURIOUS-FREE DYNAMIC RANGE9

Analog Input @ 4.98 MHz 25°C V 85 dBFS

Analog Input @ 9.9 MHz 25°C I 4 73 82 dBFS

Full II 5, 6 70 82 dBFS

Analog Input @ 19.5 MHz 25°C I 4 72 78 dBFS

Full II 5, 6 70 78 dBFS

Analog Input @ 32.1 MHz 25°C I 4 62 68 dBFS Full II 5, 6 60 66 dBFS TWO-TONE IMD REJECTION10

fIN = 10 MHz and 11 MHz 25°C I 4 78 87 dBFS

f1 and f2 are −7 dB II 5, 6 78 dBFS

fIN = 31 MHz and 32 MHz 25°C I 4 68 70 dBFS

f1 and f2 Are −7 dB Full II 5, 6 60 dBFS CHANNEL-TO-CHANNEL ISOLATION11 25°C IV 12 90 dB TRANSIENT RESPONSE 25°C V 15.3 ns OVERVOLTAGE RECOVERY TIME

VIN = 2.0 × fS Full IV 12 40 100 ns

VIN = 4.0 × fS Full IV 12 150 200 ns DIGITAL OUTPUTS12

Logic Compatibility CMOS

DVCC = 3.3 V

Logic 1 Voltage Full I 1, 2, 3 2.5 DVCC − 0.2 V Logic 0 Voltage Full I 1, 2, 3 0.2 0.5 V

DVCC = 5 V

Logic 1 Voltage Full V DVCC − 0.3 V Logic 0 Voltage Full V 0.35 V

Output Coding Twos complement POWER SUPPLY

AVCC Supply Voltage13 Full VI 4.85 5.0 5.25 V

I (AVCC) Current Full I 270 308 mA

AVEE Supply Voltage13 Full VI −5.25 −5.0 −4.75 V

I (AVEE) Current Full V 38 49 mA

DVCC Supply Voltage13 Full VI 3.135 3.3 3.465 V

I (DVCC) Current Full V 30 46 mA

ICC (Total) Supply Current per Channel Full I 1, 2, 3 338 403 mA Power Dissipation (Total) Full I 1, 2, 3 3.5 3.9 W Power Supply Rejection Ratio (PSRR) Full V 0.02 % FSR/% VS Passband Ripple to 10 MHz V 0.1 dB Passband Ripple to 25 MHz V 0.2 dB

Rev. A | Page 4 of 24

AD10465

1

See Table 3.

2

Gain tests are performed on AIN1 input voltage range.

3

Input capacitance specification combines AD8037 die capacitance and ceramic package capacitance.

4

Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

5

All ac specifications tested by driving

6

Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% ± 5%.

7

Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). ENCODE = 65 MSPS. SNR is

reported in dBFS, related back to converter full power.

8

Analog input signal power at –1 dBFS. Signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. ENCODE = 65 MSPS.

9

Analog input signal power swept from −1 dBFS to −60 dBFS; SFDR is the ratio of converter full scale to worst spur.

10

Both input tones at −7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermodulation product.

11

Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.

12

Digital output logic levels: DVCC = 3.3 V, C

13

Supply voltage recommended operating range. AVCC can be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AV

= 5.0 V to 5.25 V.

CC

ENCODE

and ENCODE differentially.

= 10 pF. Capacitive loads > 10 pF degrade performance.

LOAD

Rev. A | Page 5 of 24

AD10465

A

V

A

TEST CIRCUITS

t

A

N

A

IN

N+1

N+2

N+3

t

ENC

ENC, ENC

D[13:0]

DRY

N

3

IN

VIN2

VIN1

200Ω

100Ω

TO AD8037

02356-016

Figure 3. Analog Input Stage

LOADS

10kΩ

AV

CC

AV

CC

AV

CC

10kΩ

ENCODE ENCO DE

10kΩ

t

ENCH

N+1 N+2 N+3 N+4

N–3 N–2 N–1 N

t

ENCL

t

E, DR

Figure 2. Timing Diagram

DV

CC

CURRENT MIRROR

AV

CC

CURRENT MIRROR

Figure 5. Digital Output Stage

N+4

t

OD

02356-015

DV

CC

V

REF

DR_OUT

02356-018

LOADS

02356-017

Figure 4. ENCODE Inputs

DV

CC

CURRENT MIRROR

DV

CC

V

REF

CURRENT MIRROR

100Ω

D0 TO D13

02356-019

Figure 6. Digital Output Stage

Rev. A | Page 6 of 24

AD10465

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Min Max Units

ELECTRICAL

VCC Voltage 0 +7 V V

Voltage –7 0 V

EE

Analog Input Voltage VEE VCC V Analog Input Current −10 +10 mA Digital Input Voltage (ENCODE) 0 VCC V ENCODE, ENCODE Digital Output Current −10 +10 mA

ENVIRONMENTAL1

Operating Temperature Range (Case) −40 +85 °C Maximum Junction Temperature 174 °C Lead Temperature (Soldering, 10 sec) 300 °C Storage Temperature Range (Ambient) −65 +150 °C

1

Typical thermal impedance for 68-lead CLCC package: θJC = 2.2°C/W; θJA =

24.3°C/W.

Differential Voltage

4 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 3. Test Levels

Level Description

I 100% production tested. II

III Sample tested only. IV

V Parameter is a typical value only. VI

100% production tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis.

Parameter is guaranteed by design and characterization testing.

100% production tested at 25°C, sample tested at temperature extremes.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 7 of 24

AD10465

A

D

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

B1

B2

A1

A2

A3

IN

AGNDA

DRAOUT

AV

D0A (LSBA)

D1A

D2A

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

DGNDA

IN

A

AGND

10

11

12

13

EE

14

CC

15

16

17

18

19

20

21

22

23

24

25

26

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

CC

DV

DGNDA

ENCODEA

AGNDAAGNDAREF_A

D12A

D11A

AGND

AGNDB

SHIEL

123456789 6867666564636261

PIN 1 IDENTIFIER

AD10465

TOP VIEW

(Not to Scale)

D1B

D2B

D0B (LSBB)

D13A (MSBA)

Figure 7. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SHIELD Internal Ground Shield Between Channels. 2, 4, 5, 9 to11 AGNDA

A Channel Analog Ground. A ground and B ground should be connected as close to the device

as possible. 3 REF_A A Channel Internal Voltage Reference. 6 AINA1 Analog Input for A Side ADC (Nominally ±0.5 V). 7 AINA2 Analog Input for A Side ADC (Nominally ±1.0 V). 8 AINA3 Analog Input for A Side ADC (Nominally ±2.0 V). 12 DRAOUT Data Ready A Output. 13 AVEE Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). 14 AVCC Analog Positive Supply Voltage (Nominally 5.0 V). 26, 27 DGNDA A Channel Digital Ground. 15 to 25, 31 to 33 D0A to D13A Digital Outputs for ADC A. D0A (LSBA). 28

ENCODEA

Complement of ENCODE. 29 ENCODEA Data Conversion Initiated on Rising Edge of ENCODE Input.

30 DVCC Digital Positive Supply Voltage (Nominally 5.0 V or 3.3 V). 43, 44 DGNDB B Channel Digital Ground. 34 to 42, 45 to 49 D0B to D13B Digital Outputs for ADC B. D0B (LSBB). 53, 54, 57 to 61, 65, 68 AGNDB

B Channel Analog Ground. A ground and B ground should be connected as close to the device

as possible. 50 DVCC Digital Positive Supply Voltage (Nominally 5.0 V or 3.3 V). 51 ENCODEB Data conversion initiated on rising edge of ENCODE input. 52

ENCODEB

Complement of ENCODEB. 55 DRBOUT Data Ready B Output.

56 REF_B B Channel Internal Voltage Reference. 62 AINB1 Analog Input for B Side ADC (Nominally ±0.5 V). 63 AINB2 Analog Input for B Side ADC (Nominally ±1.0 V). 64 AINB3 Analog Input for B Side ADC (Nominally ±2.0 V). 66 AVCC Analog Positive Supply Voltage (Nominally 5.0 V). 67 AVEE Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V).

Rev. A | Page 8 of 24

AVEEAVCCAGNDB

D3B

D4B

D5B

B3

IN

A

D6B

IN

A

D7B

IN

A

D8B

AGNDB

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

DGNDB

AGNDB

REF_B

DRBOUT

AGNDB

ENCODEB

ENCODEB DV

CC

D13B (MSBB)

D12B

D11B

D10B

D9B

DGNDB

02356-002

AD10465

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

(dB)

–70

–80

–90

–100

–110

–120

–130

0 32. 530.027.525.022.520.017.515.012.510.07.55.02.5

0

–10

–20

–30

–40

–50

–60

(dB)

–70

–80

–90

–100

–110

–120

–130

0 32.530.027.525.022. 520.017.515.012.510. 07.55.02.5

0

–10

–20

–30

–40

–50

–60

(dB)

–70

–80

–90

–100

–110

–120

–130

0 32.530.027.525.022. 520.017.515.012.510. 07.55.02.5

2

FREQUENCY (MHz )

Figure 8. Single Tone @ 5 MHz Figure 11. Single Tone @ 10 MHz

ENCODE = 65MSPS

= 20MHz (–1dBF S)

A

IN

SNR = 70.71 SFDR = 79.73dBc

3

6

FREQUENCY (MHz )

Figure 9. Single Tone @ 20 MHz

ENCODE = 65MSPS

= 32MHz (–1dBF S)

A

IN

SNR = 70.22 SFDR = 66.40dBc

2

6

4

FREQUENCY (MHz )

Figure 10. Single Tone @ 32 MHz

ENCODE = 65MSPS

= 5MHz (–1dBFS)

A

IN

SNR = 71.02 SFDR = 92.11d Bc

3

4

6

5

02356-003

2

4

5

02356-004

3

5

02356-005

0

–10

–20

–30

–40

–50

–60

(dB)

–70

–80

–90

–100

–110

–120

–130

0 32.530.027.525.022. 520.017.515.012.510. 07.55.02.5

0

–10

–20

–30

–40

–50

–60

(dB)

–70

–80

–90

–100

–110

–120

–130

0 32.530.027.525.022. 520.017.515.012.510. 07.55.02.5

100

90

80

70

60

50

(–dBc)

40

30

20

10

0

ENCODE = 65MSPS A SNR = 70.79 SFDR = 86.06dBc

2

6

ENCODE = 65MSPS

= 25MHz (–1dBF S)

A

IN

SNR = 70.36 SFDR = 74.58dBc

5

FREQUENCY (MHz )

3

2

FREQUENCY (MHz )

6

Figure 12. Single Tone @ 25 MHz

SFDR

SINAD

INPUT FREQUENCY (MHz)

Figure 13. SFDR and SINAD vs. Frequency

= 10MHz (–1dBF S)

IN

4

32.00019.0009.9894.9898

3

02356-006

4

02356-007

02356-008

Rev. A | Page 9 of 24

AD10465

0

–10

–20

–30

–40

–50

–60

(dB)

–70

–80

–90

–100

–110

–120

–130

F2– F1

0 32.530.027.525.022. 520.017.515.012.510. 07.55.02.5

2F1– F2

2F2– F1

FREQUENCY (MHz )

ENCODE = 65MSPS A

IN

10MHz (–7dBF S) SFDR = 82.83dBc

F1+ F2

= 9MHz AND

2F1+ F2

2F2+ F1

02356-009

Figure 14. Two Tone @ 9 MHz and 10 MHz Figure 17. Two Tone @ 17 MHz and 18 MHz

3.0

2.5

2.0

1.5

ENCODE = 65MSPS DNL MAX = +0.549 LSB DNL MIN = –0. 549 LSB

0

–10

–20

–30

–40

–50

–60

(dB)

–70

–80

–90

–100

–110

–120

–130

0 32. 530.027.525.022.520.017.515.012.510.07.55.02.5

3

2

1

F2–

F1

2F2+F12F1+

F2

2F1–

F2

FREQUENCY (MHz )

ENCODE = 65MSPS A

= 17MHz AND

IN

18MHz (–7dBFS ) SFDR = 77.68dBc

2F2–

F1

ENCODE = 65MSPS INL MAX = +1.173 LSB INL MIN = –1.332 LSB

F1+

F2

02356-012

(LSB)

(dBFS)

1.0

0.5

0

–0.5

–1.0

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

0 163841433612288102408192614440962048

Figure 15. Differential Nonlinearity

1.0 33.029.826.623.420.217.013.810.67.44.2

FREQUENCY (MHz )

Figure 16. Gain Flatness

CODES

0

(LSB)

–1

–2

02356-010

–3

0 163841433612288102408192614440962048

CODES

Figure 18. Integral Nonlinearity

72.0

71.5

71.0

70.5

70.0

69.5

69.0

SNR FULL SCALE

68.5

68.0

02356-011

67.5

+85°C

Figure 19. SNR vs. A

–40°C

+25°C

AIN (MHz)

Frequency

IN

3219105

02356-013

02356-014

Rev. A | Page 10 of 24

AD10465

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay

The delay between a differential crossing of ENCODE and ENCODE

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

, and the instant at which the analog input is sampled.

Output Propagation Delay

The delay between a differential crossing of ENCODE and ENCODE valid logic levels.

Overvoltage Recovery Time

The amount of time required for the converter to recover to

0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in power supply voltage.

, and the time when all output data bits are within

ENCODE Pulse Width/Duty Cycle

Pulse width high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable encode duty cycle.

Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the worst harmonic component.

Integral Nonlinearity

The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed, above which converter performance can degrade.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Can be reported in dB (that is, relative to signal level) or in dBFS (always related back to converter full scale).

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Can be reported in dB (that is, relative to signal level) or in dBFS (always related back to converter full scale).

Spurious-Free Dynamic Range

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic.

Transi ent Res p ons e

The time required for the converter to achieve 0.03% accuracy when a one-half, full-scale step function is applied to the analog input.

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBFS.

Rev. A | Page 11 of 24

AD10465

THEORY OF OPERATION

The AD10465 is a high dynamic range, 14-bit, 65 MHz pipeline delay (three pipelines) analog-to-digital converter. The custom analog input section maintains the same input ranges (1 V p-p, 2 V p-p, and 4 V p-p) and input impedance (100 Ω, 200 Ω, and 400 Ω) as the AD10242.

The AD10465 employs four monolithic Analog Devices components per channel (AD8037, AD8138, AD8031, and AD6644), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 14-bit analog-to-digital converter.

The input signal is passed through a precision laser trimmed resistor divider allowing the user to externally select operation with a full-scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by choosing the proper input terminal for the application.

The AD10465 analog input includes an AD8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifiers inputs and outputs. The AD8037 amplifier provides a high input impedance and gain for driving the AD8138 in a single-ended to differential amplifier configuration. The AD8138 has a −3 dB bandwidth at 300 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help balance the differential inputs to the AD6644, maximizing the performance of the ADC.

The AD8031 provides the buffer for the internal reference of the AD6644. The internal reference voltage of the AD6644 is designed to track the offsets and drifts of the ADC and is used to ensure matching over an extended temperature range of operation. The reference voltage is connected to the output common-mode input on the AD8138. The AD6644 reference voltage sets the output common mode on the AD8138 at 2.4 V, which is the midsupply level for the AD6644.

Table 5. Input Impedance Options

Input Impedance Condition

AIN1 100 Ω When AIN2 and AIN3 are open 75 Ω When AIN3 is shorted to GND 50 Ω When AIN2 is shorted to GND AIN2 200 Ω When AIN3 is open 100 Ω When AIN3 is shorted to GND 75 Ω When AIN2 to AIN3 has an external resistor of 300 Ω, with AIN3 shorted to GND 50 Ω When AIN2 to AIN3 has an external resistor of 100 Ω, with AIN3 shorted to GND AIN3 400 Ω 100 Ω When AIN3 has an external resistor of 133 Ω to GND 75 Ω When AIN3 has an external resistor of 92 Ω to GND 50 Ω When AIN3 has an external resistor of 57 Ω to GND

The AD6644 has complementary analog input pins, AIN and AIN

. Each analog input is centered at 2.4 V and should swing ±0.55 V around this reference. Since AIN and of phase, the differential analog input signal is 2.2 V peak-topeak. Both analog inputs are buffered prior to the first track-

and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives 14 bits of precision, which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1.

The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision, which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3.

The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as twos complement.

AIN

are 180° out

USING THE FLEXIBLE INPUT

The AD10465 has been designed with the user’s ease of operation in mind. Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. While the standard inputs are ±0.5 V, ±1.0 V, and ±2.0 V, the user can select the input impedance of the AD10465 on any input by using the other inputs as alternate locations for GND or an external resistor. the impedance options available at each input location.

Tabl e 5 summarizes

Rev. A | Page 12 of 24

AD10465

V

APPLYING THE AD10465

ENCODING THE AD10465 JITTER CONSIDERATIONS

The AD10465 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 32 MHz input signals when using a high jitter clock source. See the Analog Devices Application Note AN-501, Aper- ture Uncertainty and ADC System Performance, for complete details. For optimum performance, the AD10465 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and

ENCODE

pins via a transformer or capacitors. These pins are biased internally and require no additional bias.

Figure 20 shows one preferred method for clocking the AD10465. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The backto-back Schottky diodes across the transformer secondary limit clock excursions into the AD10465 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD10465, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 Ω) is placed in the series with the primary.

0.1nF

100Ω

CLOCK

SOURCE

Figure 20. Crystal Clock Oscillator, Differential ENCODE

T1-4T

HSMS2812

DIODES

ENCODE

AD10465

ENCODE

02356-020

If a low jitter ECL/PECL clock is available, another option is to ac couple a differential ECL/PECL signal to the ENCODE and ENCODE

input pins as shown in Figure 21. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola.

T

ECL/

PECL

VT

Figure 21. Differential ECL for ENCODE

0.1µF

ENCODE

AD10465

ENCODE

02356-021

The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter.

⎡

+

1

ε

⎞

⎛

⎢

⎜

⎢

⎝

⎢

()

×−=

log20

⎢ ⎢

⎛

⎢

⎜ ⎜

⎢

⎝

⎣

+

⎟

N

2

⎠

2

π

v

2

⎞

rmsNOISE

⎟

n

⎟

2

⎠

rmstfSNR

jANALOG

2/1

⎤ ⎥ ⎥ ⎥

(1)

2

+×××

⎥ ⎥ ⎥ ⎥

⎦

where:

f

is the analog input frequency.

ANALOG

t

is the rms jitter of the encode (rms sum of encode source

j rms

and internal encode circuitry).

ε is the average DNL of the ADC (typically 0.50 LSB).

N is the number of bits in the ADC.

V

is the V rms noise referred to the analog input of the

NOISE rms

ADC (typically 5 LSB).

For a 14-bit analog-to-digital converter like the AD10465, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD10465 as jitter increases. The chart is derived from Equation 1.

For a complete discussion of aperture jitter, please consult the Analog Devices Application Note AN-501, Aperture Uncertainty

and ADC System Performance.

71

2.5

2.7

2.9

AIN = 5MHz

A

= 10MHz

IN

A

= 20MHz

IN

A

= 32MHz

IN

3.1

3.3

02356-022

3.9

3.5

3.7

70

69

68

67

66

65

SNR (dBFS)

64

63

62

61

60

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

RMS CLOCK JIT TER (ps)

Figure 22. SNR vs. Jitter

2.3

Rev. A | Page 13 of 24

AD10465

POWER SUPPLIES

Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that can be “received” by the AD10465. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 μF chip capacitors.

The AD10465 has separate digital and analog power supply pins. The analog supplies are denoted AV supply pins are denoted DV

. AVCC and DVCC should be

CC

and the digital

CC

separate power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AV AD10465 is specified for DV

must be held within 5% of 5 V. The

CC

= 3.3 V as this is a common

CC

supply for digital ASICs.

OUTPUT LOADING

Care must be taken when designing the data receivers for the AD10465. The digital outputs drive an internal series resistor (for example, 100 Ω) followed by a gate, such as the 75LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace has a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷1 ns) of dynamic current per bit flows in or out of the device. A full-scale transition can cause up to 140 mA (14 bits ×10 mA/bit) of current flow through the output stages. These switching currents are confined between ground and the DV should be avoided because they can appreciably add to the dynamic switching currents of the AD10465. It should also be noted that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed with 10 pF loads.

Figure 26. The digital outputs of the AD10465

pin. Standard TTL gates

CC

LAYOUT INFORMATION

The schematic of the evaluation board (see Figure 24) represents a typical implementation of the AD10465. The pinout of the AD10465 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors.

Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate.

Rev. A | Page 14 of 24

AD10465

EVALUATION BOARD

The AD10465 evaluation board (Figure 23) is designed to provide optimal performance for evaluation of the AD10465 analog-to-digital converter. The board encompasses everything needed to ensure the highest level of performance for evaluating the AD10465. The board requires an analog input signal, encode clock, and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and clocks are available at the standard 40-pin connectors, Connector J1 and Connector J2.

Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD10465. The digital outputs of the AD10465 are powered via banana jacks with 3.3 V. Contact the factory if additional layout or applications assistance is required.

Figure 23. Evaluation Board Mechanical Layout

Rev. A | Page 15 of 24

02356-023

AD10465

F

–5.2VAA

C22

10µ

C53

10µF

J1

AGNDB

J2

AGNDB

J22

AGNDB

J7

AGNDA

J8

AGNDA

J20

AGNDA

+5VAA

AGNDA

AINB3

A

B2

IN

A

B1

IN

A

A3

IN

A

A2

IN

A

A1

IN

L10

47

L7

47

47Ω

AT 100MHz

AGNDA

DRAOUT

+5VAA

D0A

D1A

D2A

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

C57

0.1µF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

AGNDA

DRAOUT

–5.2VAA

+5VAA

D0A (LSB)

D1A

D2A

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

DGNDA

CLKLATCHB2

CLKLATCHB1

DRBOUT

DRAOUT

CLKLATCHA1

CLKLATCHA2

C59 10µF

AGNDB

A3

A2

A1

IN

A

987654321

A3

A2

A1

IN

A

AGNDA

DGNDA

ENCAB

ENCA

+3.3VDA

2728293031323334353637383940414243

JP3

JP4

47V

AT 100MHz

L9

47

REFA

AGNDA

AD10465

D11A

D12A

D13A (MSB)

JP5

U2:A U2:D U2:B

1

2

74LCX00M 74LCX00M 74LCX00M

U4:A U4:D U4:B

1

2

74LCX00M 74LCX00M 74LCX00M

JP6

AGNDA

68676665646362

AGNDA

AGNDB

SHIELD

–5.2VAB

+5VAB +5VAB

3

B3

A

B3

A

AGNDB

13

12

13

12

47V

AT 100MHz

L8

47

B2

B1

IN

A

B2

B1

IN

A

U1

D0B (LSB)

D1B

D2B

D3B

D4B

D5B

D6B

D7B

D8B

11

61

AGNDB

REFB

DRBOUT

AGNDB

ENCBB

ENCB

+3.3VDB

D13B (MSB)

D12B

D11B

D10B

D9B

DGNDB

4

5

4

5

+5VAB–5.2VAB

AGNDB

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

C52 10µF

AGNDB

JP1

6

JP2

LATCHB

BUFLATB

BUFLATA

LATCHA

C61

0.1µF

DRBOUT

AGNDB

ENCBB

ENCB

DUT_3.3VDB

D13B (MSB)

D12B

D11B

D10B

D9B

C64

0.1µF

+3.3VDB

L6

47

DGNDB

C58 10µF

D0B

D1B

D2B

D3B

D4B

D5B

D6B

D7B

C26

0.1µF

DGNDB

D8B

DGNDB

10

9

DGNDB

SPARE

GATE

U2:C

DUT_3.3VDADUT_3.3VDB

C27

88

0.1µF

DGNDA

10

DGNDA

SPARE

GATE

U4:C

9

74LCX00M74LCX00M

02356-024

+3.3VDA

DGNDA

C62 10µF

L11

47

ENCAB

DGNDA

ENCA

DUT_+3.3VDA

D11A

C63

0.1µF

D12A

D13A

Figure 24. Evaluation Board

Rev. A | Page 16 of 24

AD10465

ENCODEA

ENCODEB

J6

AGNDA

J18

AGNDA

J16

AGNDB

J17

AGNDB

AGNDA

AGNDB

R82 51Ω

R83 51Ω

R76 51Ω

R79 51Ω

C42

0.1µF

C40

0.1µF

C37

0.1µF

C39

0.1µF

+5VAA

JP8

+5VAA

JP10

JP11 OPEN

JP12 OPEN

JP7

JP9

+5VAA

R140 33kΩ

1

2

3

4

NC = NO CONNECT

+5VAA

R141 33kΩ

1

2

3

4

NC = NO CONNECT

ADP3330

2

IN

6

SD

GND

4

AGNDA

U7

NC

VCC

D

VBB

VEE

MC10EP16D

ADP3330

2

IN

6

SD

GND

4

AGNDB

U9

NC

VCC

D

VBB

VEE

MC10EP16D

U6

1

OUT

8

NR

3

ERR

8

7

Q

6

Q

5

AGNDA

U8

1

OUT

8

NR

3

ERR

8

7

Q

6

Q

5

AGNDB

AGNDB AGNDB

AGNDA

C41

0.47µF

AGNDB

C38

0.47µF

C45 100pF

AGNDA

C43 100pF

R89 100Ω

R95 100Ω

R94 100Ω

R97 100Ω

C44

0.1µF

C49

0.1µF

C48

0.1µF

C46

0.1µF

ENCAB

ENCA

ENCB

ENCBB

02356-025

Figure 25. Evaluation Board

Rev. A | Page 17 of 24

AD10465

A

OUT_3.3VDA

C13

C14

0.1µF

+3.3VDA

AGNDB DGNDA

C15

0.1µF

+3.3VDB

DGNDA

0.1µF

BANANA JACKS FOR GNDS AND PW RS

+5VAB

+5VAA

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

–5.2VAB –5.2VAA

C20

0.1µF

DGNDBAGNDA

R100 0Ω

LATCHA

DGNDA

(MSB) D13A

(LSB) D0A

D1A

R99 0Ω

D2A

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

D11A

D12A

R98 51Ω

U21

VCC

CP2

OE2

I15 I14 I13

I12

I11

I10 I9

I8

CP1

OE1 I7

I6

I5

I4 I3

I2

I1

I0

GND

VCC

O15

O14

O13

O12

O11

O10

O9

O8

O7

O6

O5

O4

O3

O2

O1

O0

GND

DGNDA

25

24

26

27

29

30

32

33

35

36

48

1

37

38

40

41

43

44

46 47

28

34

39

45

74LCX163743MTD

OUT_3.3VDA

42

31

7

18

23

22

20

19

17

16

14

13

12

11

9

8

6

5

3

2

21

15

18

4

R115 100Ω

R114 100Ω

R105 100Ω

R106 100Ω

BUFLATA

R102 100Ω

R109

100Ω

R107 100Ω

R111 100Ω

R117 100Ω

R116 100Ω

R113 100Ω

R104 100Ω

R103 100Ω

R101 100Ω

R108 100Ω

R110 100Ω

R118

51Ω

MSB

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

J3

DGNDA

DGND

OUT_3.3VDA

C25

0.1µF

E87 E88

E72

E89

E140

E139

E141

E143

E142

E146

E144

E148

E145

E149

E147

E152

E150

E153

E151

E184

E154

E188

E185

E189

E194

E190

E196

E195

E198

E197

E200

E199

E202

E201

E204

E203

E206

E205

E223

E224

E225

E226

C21

C23

0.1µF

E159 E160 E161 E167 E168 E169 E170 E178 E180 E182 E183 E191 E192 E193 E208 E210 E212 E214 E216 E218 E220 E222 E228 E230 E232 E234

DGNDB

C24

0.1µF

LATCHB

R123 0Ω

DGNDB

R119

(LSB) D0B

D1B

R124 0Ω

D2B

D3B

D4B

D5B

D6B

D7B

D8B D9B

D10B

D11B D12B

(MSB) D13B

51Ω

0.1µF

E162 E163 E164 E165 E166 E171 E172 E177 1E79 E181 E186 E187 E207 E209 E211 E213 E215 E217 E219 E221 E227

AGNDA

E229 E231 E233

AGNDB DGNDB DGNDB

OUT_3.3VDB

U22

42

VCC

31

VCC

25

CP2

24

OE2

26

I15

27

I14

29

I13

30

I12

32

I11

33

I10

35

I9

36

I8

48

CP1

1

OE1

37

I7

38

I6

40

I5

41

I4

43

I3

44

I2

46

I1

47

I0

28

GND

34

GND

39

GND

45

GND

74LCX163743MTD

VCC

O15

O14

O13

O12

O11

O10

O9

O8

O7

O6

O5

O4

O3

O2

O1

O0

GND

GND GND

7

18

23

22

20

19

17

16

14

13

12

11

9

8

6

5

3

2

21

15

18

4

Figure 26. Evaluation Board

R127 100Ω

R125 100Ω

R129 100Ω

R134 100Ω

BUFLATB

R136 100Ω

R132 100Ω

R120 100Ω

R122 100Ω

R112 100Ω

R126 100Ω

R130 100Ω

R128 100Ω

R135 100Ω

R131 100Ω

R133 100Ω

R121 100Ω

R137

51

Ω

MSB

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

J4

DGNDB

02356-026

Rev. A | Page 18 of 24

AD10465

BILL OF MATERIALS LIST FOR AD10465 EVALUATION BOARD

Table 6. Bill of Materials

Manufacturer and Part

Qty Reference Designator Value Description

2 U2, U4

2 U21, U22

1 U1

2 U6, U8 IC, voltage regulator 3.3 V, RT-6

10 E1 to E10 Banana jack, socket

22

C13 to C15, C20, C21, C23 to C27, C37, C39, C40, C42, C44, C46, C48, C49, C57, C61,

C63, C64 2 C38, C41 0.47 μF Capacitor, 0.47 μF, 5%, 12 V dc, 1206 Vitramon/VJ1206U474MFXMB CAP 1206 2 C43, C45 100 pF Capacitor, 100 pF, 10%, 12 V dc, 0805 Johansen/500R15N101JV4 CAP 0805 2 J3, J4 Connector, 40-pin header male Samtec/TSW-120-08-G-D HD40M 6 L6 to L11 47 μH

2 U7, U9 IC, differential receiver, SOIC-8 Motorola/MC10EP16D MC10EP16D 6

C22, C52, C53, C58,

C59, C62 4 R99, R100, R123, R124 0.0 Ω Resistor, 0.0 Ω, 0805 Panasonic/ERJ-6GEY0R00V RES2 0805 2 R140, R141 33,000 Ω

8

R76, R79, R82, R83, R98,

R118, R119, R137 36

R89, R94, R95, R97,

R101 to R117, R120 to

R122, R125 to R136 8

J1, J2, J6 to J8, J16 to

J18, J20, J22

0.1 μF Capacitor, 0.1 μF, 20%, 12 V dc, 0805 Mena/GRM40X7R104K025BL CAP 0805

10 μF

51 Ω Resistor, 51 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ510V

100 Ω Resistor, 100 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ101V

Connector, SMA female

IC, low-voltage Quad 2-input nand, SOIC-14

IC, 16-bit transparent latch with three-state outputs, TSSOP-48

DUT, IC 14-bit analog-to-digital converter

Inductor, 47 μH @ 100 MHz, 20%, IND2

Capacitor, 10 μF, 20%, 16 V dc, 1812POL

Resistor, 33,000 Ω, 5%, 0.10 Watt, 0805

Number

Toshiba/TC74LCX00FN 74LCX00M

Fairchild/74LCX163743MTD 74LCX163743MTD

ADI/AD10465BZ ADI/AD10465BZ

Analog Devices/ADP3330ART3, 3-RLT

Johnson Components/080740-001

Fair-Rite/2743019447 IND2

Kemet/T491C106M016A57280 POLCAP 1812

Panasonic/ERJ-6GEYJ333V RES2 0805

Johnson Components/1420701-201

Component Name

ADP3330

Banana Hole

RES2 0805, RES 0805

SMA

Rev. A | Page 19 of 24

AD10465

SILKSCREENS

Figure 27. Top Layer Copper

02356-027

Figure 28. Second Layer Copper

Rev. A | Page 20 of 24

02356-028

AD10465

Figure 29. Third Layer Copper

02356-029

02356-030

Figure 30. Fourth Layer Copper

Rev. A | Page 21 of 24

AD10465

Figure 31. Fifth Layer Copper

02356-031

Figure 32. Bottom Layer Copper

Rev. A | Page 22 of 24

02356-032

AD10465

Figure 33. Bottom Silkscreen

02356-033

02356-034

Figure 34. Bottom Assembly

Rev. A | Page 23 of 24

AD10465

0

Q

OUTLINE DIMENSIONS

0.010 (0.25)

0.008 (0.20)

0.007 (0.18)

0.235 (5.97) MAX

10

9

0.960 (24.38)

0.950 (24.13) SQ

0.940 (23.88)

PIN 1

61

60

.050 (1.27)

TOE DOWN

0–8 DEGREES

0.020 (0.508)

DETAIL A

ROTATED 90° CCW

0.055 (1.40)

0.050 (1.27)

0.045 (1.14)

TOP VIEW

(PINS DOWN)

0.020 (0.508)

0.017 (0.432)

0.014 (0.356)

MAX

0.800

(20.32)

BSC

DETAIL A

26

27

1.070

(27.18)

ANGLE

0.010 (0.254)

30°

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

MIN

0.060 (1.52)

0.050 (1.27)

0.040 (1.02)

0.175 (4.45)

44

43

1.190 (30.23)

1.180 (29.97) S

1.170 (29.72)

Figure 35. 68-Lead Ceramic Leaded Chip Carrier [CLCC]

(Z-68A)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD10465BZ −40°C to +85°C 68-Lead Ceramic Leaded Chip Carrier [CLCC] Z-68A

2

5962-9961601HXA −40°C to +85°C 68-Lead Ceramic Leaded Chip Carrier [CLCC] Z-68A AD10465/PCB Evaluation Board with AD10465BZ

1

Case temperature.

2

Z = Pb-free part.

1

Rev. A | Page 24 of 24

Datasheet AD10465 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CIRCUITS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

USING THE FLEXIBLE INPUT

APPLYING THE AD10465

ENCODING THE AD10465 JITTER CONSIDERATIONS

POWER SUPPLIES

OUTPUT LOADING

LAYOUT INFORMATION

EVALUATION BOARD

BILL OF MATERIALS LIST FOR AD10465 EVALUATION BOARD

SILKSCREENS

OUTLINE DIMENSIONS

ORDERING GUIDE