Datasheet AD10256 Datasheet (ANALOG DEVICES)

查询AD10265供应商查询AD10265供应商

Dual Channel, 12-Bit, 65 MSPS A/D Converter

a

FEATURES
Dual, 65 MSPS Minimum Sample Rate

Channel-Channel Matching, ⴞ0.1% Gain Error
Channel-Channel Isolation, >80 dB
AC-Coupled Signal Conditioning Included

Selectable Bipolar Input Voltage Range

(ⴞ0.5 V, ⴞ1.0 V, ⴞ2.0 V)
Gain Flatness up to Nyquist: < 0.5 dB
80 dB Spurious-Free Dynamic Range
Twos Complement Output Format
+3.3 V or +5 V CMOS-Compatible Output Levels

1.05 W Per Channel
Industrial and Military Grade

APPLICATIONS
Phased Array Receivers
Communications Receivers
FLIR Processing
Secure Communications
GPS Anti-Jamming Receivers
Multichannel, Multimode Receivers

with Analog Input Signal Conditioning

AD10265

65 MSPS performance. The AD10265 uses innovative high­density circuit design and laser-trimmed thin-film resistor
networks to achieve exceptional matching and performance
while still maintaining excellent isolation, and providing for
significant board area savings.

The AD10265 operates with ±5.0 V for the analog signal

conditioning with a separate +3.3 V supply for the analog-to­digital conversion. Each channel is completely independent
allowing operation with independent Encode and Analog in­puts. The AD10265 also offers the user a choice of Analog
Input Signal ranges to further minimize additional external
signal conditioning, while still remaining general-purpose.

The AD10265 is packaged in a 68-lead Ceramic Gull Wing
Package, footprint compatible with the earlier generation
AD10242 (12-bit, 40 MSPS). Manufacturing is done on
Analog Devices’ MIL-38534 Qualified Manufacturers Line

(QML) and components are available up to Class-H (–55°C to
+125°C). The AD6640 internal components are manufactured

on Analog Devices’ high speed complementary bipolar process
(XFCB).

PRODUCT DESCRIPTION

The AD10265 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
includes two wide dynamic range AD6640 ADCs. Each
AD6640 has an AD9631/AD9632 ac-coupled amplifier front
end. The AD6640s have on-chip track-and-hold circuitry, and
utilize an innovative multipass architecture, to achieve 12-bit,

FUNCTIONAL BLOCK DIAGRAM

AINA2 AINA1AINA3

(LSB) D0A

D1A
D2A
D3A
D4A
D5A

D6A
D7A
D8A

9

TIMING

AD9632

AIN

AD6640

OUTPUT BUFFERING

AD9631

AIN

AD10265

12

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 65 MSPS.

2. Input amplitude options, user configurable.

3. Input signal conditioning included; both channels matched
for gain.

4. Fully tested/characterized performance for full channel.

5. Footprint compatible family; 68-lead LCCC.

AINB3

AINB2 AINB1

AD9632

AIN

OUTPUT BUFFERING

AIN

AD6640

12

7

AD9631

TIMING

5

ENCODEB

ENCODEB

D11B (MSB)
D10B
D9B
D8B
D7B

ENCODEA

ENCODEA

D9A D10A

D11A

(MSB)

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

D0B

D1B D2B

(LSB)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

D3B D4B D5B

D6B

AD10265–SPECIFICATIONS

Electrical Characteristics

(AVCC = +5 V; AVEE = –5.0 V; DVCC = +3.3 V; applies to each ADC unless otherwise noted)

Test Mil AD10265AZ

Parameter Temp Level Subgroup Min Typ Max Units

RESOLUTION 12 Bits

ACCURACY

No Missing Codes Full VI 1, 2, 3 Guaranteed
Offset Error Full IV 2, 3 –10 3.5 +10 mV
Gain Error

1

+25°C I 1 –1.0 ±0.5 +1.0 % FS
Full VI 2, 3 –2.0 ±0.8 +2.0 % FS

Gain Error Channel Match Full V ±0.1 %

Pass Band Ripple to Nyquist Full I 12 0.2 0.5 dB

ANALOG INPUT (A

)

IN

Input Voltage Range

A

1 Full I ±0.5 V

IN

2 Full I ±1.0 V

A

IN

A

3 Full I ±2V

IN

Input Resistance

1 Full IV 12 99 100 101 Ω

A

IN

A

2 Full IV 12 198 200 202 Ω

IN

3 Full IV 12 396 400 404 Ω

A

IN

Input Capacitance
Analog Input Bandwidth High
Analog Input Bandwidth Low

ENCODE INPUT

4, 5

2

3

3

+25°CIV 12 0 4.0 7.0 pF
+25°C V 160 MHz
+25°CV 50 kHz

Logic Compatibility TTL/CMOS
Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V
Logic “0” Voltage Full I 1, 2, 3 0 0.8 V
Logic “1” Current (V
Logic “0” Current (V

= 5 V) Full I 1, 2, 3 500 650 800 µA

INH

= 0 V) Full I 1, 2, 3 –400 –320 –200 µA

INL

Input Capacitance +25°CV 12 4.5 7.0 pF

SWITCHING PERFORMANCE

Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (t

) +25°C V 400 ps

A

6

6

Full VI 4, 5, 6 65 MSPS
Full V 12 6.5 MSPS

Aperture Delay Matching +25°CV ±2.0 ns
Aperture Uncertainty (Jitter) +25°C V 0.3 ps rms
ENCODE Pulsewidth High +25°C IV 12 6.5 ns
ENCODE Pulsewidth Low +25°C IV 12 6.5 ns

Output Delay (tOD) Full IV 12 7.0 9.0 12.5 ns

7

SNR

Analog Input @ 1.24 MHz +25°CI 4 62 66 dB

Full II 5, 6 60.5 66 dB

@ 17 MHz +25°CI 4 61 65 dB

Full II 5, 6 60 65 dB

@ 32 MHz +25°CI 4 61 63 dB

Full II 5, 6 59.5 62 dB

8

SINAD

Analog Input @ 1.24 MHz +25°CI 4 61 65 dB

Full II 5, 6 60 64 dB

@ 17 MHz +25°CI 4 61 64 dB

Full II 5, 6 59.5 63 dB

@ 32 MHz +25°CI 4 61 62 dB

Full II 5, 6 59 62 dB

–2–

REV. 0

AD10265

Test Mil AD10265AZ

Parameter Temp Level Subgroup Min Typ Max Units

SPURIOUS-FREE DYNAMIC RANGE

Analog Input @ 1.24 MHz +25°C I 4 75 80 dBFS

@ 17 MHz +25°C I 4 72 80 dBFS
@ 32 MHz +25°C I 4 72 79 dBFS

TWO-TONE IMD REJECTION

f1, f2 @ –7 dBFS Full II 4, 5, 6 72 80 dBc

CHANNEL-TO-CHANNEL ISOLATION

LINEARITY

Differential Nonlinearity

(Encode = 20 MHz) +25°C IV 12 –1.0 ±0.5 1.5 LSB

Integral Nonlinearity

(Encode = 20 MHz) Full V ±1.25 LSB

DIGITAL OUTPUTS

Logic Compatibility CMOS
Logic “1” Voltage Full I 1, 2, 3 2.8 DV
Logic “0” Voltage Full I 1, 2, 3 0.2 0.5 V
Output Coding Twos Complement

POWER SUPPLY

AVCC Supply Voltage Full VI +5.0 V

) Current Full V 336 mA

I (AV

CC

AV

Supply Voltage Full VI –5.0 V

EE

) Current Full V 66 mA

I (AV

EE

DV

Supply Voltage Full VI +3.3 V

CC

I (DV
I

) Current Full V 20 mA

CC

(Total) Supply Current Full I 1, 2, 3 422 520 mA

CC

Power Dissipation (Total) Full I 1, 2, 3 2.1 2.4 W
Power Supply Rejection Ratio (PSRR) Full IV 7, 8 0.01 0.02 % FSR/% V

NOTES

1

Gain tests are performed on AIN1 over specified input voltage range.

2

Input capacitance specifications show only ceramic package capacitance.

3

Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

4

ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.

5

ENCODE may also be driven differentially in conjunction with ENCODE; see “Encoding the AD10265” for details.

6

Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.

7

Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS.

8

Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.

9

Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.

10

Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 17.0 MHz

± 100 kHz, f 2 = 18.0 MHz ± 100 kHz.

11

Channel-to-channel isolation tested with A channel/50 ohm terminated <AIN2 grounded, and a full-scale signal applied to B channel (AIN1).

All specifications guaranteed within 100 ms of initial power up regardless of sequencing.
Specifications subject to change without notice.

9

Full II 5, 6 75 80 dBFS

Full II 5, 6 72 79 dBFS

Full II 5, 6 72 79 dBFS

10

11

+25°CIV 12 80 dB

– 0.2 V

CC

S

REV. 0

–3–

AD10265

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

Parameter Min Max Units

ELECTRICAL

V

Voltage 0 7 V

CC

Voltage –7 0 V

V

EE

Analog Input Voltage V

EE

V

V

CC

Analog Input Current –10 +10 mA
Digital Input Voltage (ENCODE) 0 AV

CC

V

ENCODE, ENCODE Differential Voltage 4 V
Digital Output Current –10 +10 mA

ENVIRONMENTAL

2

Operating Temperature (Case) –55 +125 °C
Maximum Junction Temperature +175 °C
Lead Temperature (Soldering, 10 sec) +300 °C
Storage Temperature Range (Ambient) –65 +150 °C

NOTES

1

Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.

2

Typical thermal impedances for “Z” package: θJC = 11°C/W; θJA = 30°C/W.

ORDERING GUIDE

Table I. Output Coding

MSB LSB Base 10 Input

0111111111111 2047 +FS
0000000000001 +1
0000000000000 0 0.0 V
1111111111111 –1
1000000000000 2048 –FS

EXPLANATION OF TEST LEVELS

Test Level

I – 100% Production Tested.

II – 100% production tested at +25°C, and sample tested at

specified temperatures. AC testing done on sample basis.

III – Sample Tested Only.

IV – Parameter is guaranteed by design and characterization

testing.

V – Parameter is a typical value only.

VI – All devices are 100% production tested at +25°C; sample

tested at temperature extremes.

M

odel Temperature Range Package Description Package Option

AD10265AZ –25°C to +85°C (Case) 68-Lead Leaded Ceramic Chip Carrier Z-68A
AD10265/PCB +25°C Evaluation Board with AD10265AZ

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD10265 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

AD10265

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1 SHIELD Internal Ground Shield between channels.
2, 5, 9–11, 26, 27 GNDA A Channel Ground. A and B grounds should be connected as close to the device as possible.
3, 4, 12, 15, 16, NC No Connect. Pins 15 and 17 are internal test pins: it is recommended to connect them to

34, 35, 55–57 GND
6A
7A
8A
13 AV
14 AV
17–25, 31–33 D0A–D11A Digital Outputs for ADC A. D0 (LSB).
28 ENCODEA ENCODE is complement of ENCODE.
29 ENCODEA Data conversion initiated on rising edge of ENCODE input.
30 DV
36–42, 45–49 D0B–D11B Digital Outputs for ADC B. D0 (LSB).
43, 44, 53, 54, GNDB B Channel Ground. A and B grounds should be connected as close to the device

58–61, 65, 68 as possible.
50 DV
51 ENCODEB Data conversion initiated on rising edge of ENCODE input.
52 ENCODEB ENCODE is complement of ENCODE.
62 A
63 A
64 A
66 AV
67 AV

A1 Analog Input for A side ADC (nominally ±0.5 V).

IN

A2 Analog Input for A side ADC (nominally ±1.0 V).

IN

A3 Analog Input for A side ADC (nominally ±2.0 V).

IN

EE

CC

CC

CC

B1 Analog Input for B side ADC (nominally ±0.5 V).

IN

B2 Analog Input for B side ADC (nominally ±1.0 V).

IN

B3 Analog Input for B side ADC (nominally ±2.0 V).

IN

CC

EE

Analog Negative Supply Voltage (nominally –5.0 V). For A side ADC.
Analog Positive Supply Voltage (nominally +5.0 V). For A side ADC.

Digital positive supply voltage (nominally +3.3 V) for A side ADC.

Digital Positive Supply Voltage (nominally +3.3 V) for B side ADC.

Analog Positive Supply Voltage (nominally +5.0 V). For B side ADC.
Analog Negative Supply Voltage (nominally –5.0 V). For B side ADC.

68-Lead Leaded Ceramic Chip Carrier

10

GNDA

11

GNDA

12

NC

13

AV

EE

14

AV

CC

15

NC

16

NC

(LSB) D0A

17
18

D1A

19

D2A

20

D3A

21

D4A

22

D5A

23

D6A

24

D7A

25

D8A

26

GNDA

NC = NO CONNECT

PIN CONFIGURATION

A2

A3

A1

IN

IN

IN

A

A

GNDA

A

9618 7 6 5 68 67 66 65 64 63 624321

GNDA

NC

NC

GNDA

PIN 1

SHIELD

GNDB

AD10265

TOP VIEW

(Not to Scale)

27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42

GNDA

ENCODEA

CC

DV

ENCODEA

D9A

D10A

NC

NC

(LSB) D0B

(MSB) D11A

EE

AV

D1B

CC

AV

D2B

B3

IN

A

GNDB

D3B

D4B

B2

IN

A

D5B

B1

IN

A

D6B

GNDB

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

GNDB

GNDB
GNDB
GNDB
NC
NC
NC
GNDB
GNDB

ENCODEB

ENCODEB
DV

CC

D11B (MSB)
D10B
D9B
D8B
D7B
GNDB

REV. 0

–5–

AD10265

DEFINITION OF SPECIFICATIONS
Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

Encode Pulse Width/Duty Cycle

Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these

Encode

specs define an acceptable

Harmonic Distortion

duty cycle.

The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” de­termined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo­nents, including harmonics but excluding dc.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo­nents, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo­nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered) or in dBFS (always
related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in
dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious compo­nent may or may not be an IMD product. May be reported
in dBc (i.e., degrades as signal levels is lowered) or in dBFS
(always related back to converter full scale).

–6–

REV. 0

AD10265

A

ENCODE

DIGITAL

OUTPUTS

N

IN

t

A

t

OD

N – 2

N + 1

N + 2 N + 3

N – 1 N N + 1 N + 2

Figure 1. Timing Diagram

EQUIVALENT CIRCUITS

AINA3

A2

A

IN

A1

A

IN

Figure 3. Analog Input Stage

R4
200V

R3
100V

AV

N + 4 N + 5

TTL CLOCK

10MHz

f

AINA2

ENC D11

ENC

AINA3

AINA1

NOTE: ALL 65V SUPPLY PINS BYPASSED
TO GND WITH A 0.1mF CAPACITOR

1/2

AD10265

SHOWN

D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

Figure 2. Equivalent Burn-In Circuit

DV

CC

CURRENT

MIRROR

DV

CC

V

REF

CC

D0 – D11

ENCODE

AV

CC

R1

17kV

8kV

R2

TIMING

CIRCUITS

Figure 4. Encode Inputs

R1
17kV

R2
8kV

AV

CC

ENCODE

CURRENT

MIRROR

Figure 5. Digital Output Stage

REV. 0

–7–

AD10265–Typical Performance Characteristics

0
–10
–20

–30
–40

–50
–60
–70
–80
–90

–100
–110
–120

POWER RELATIVE TO FULL SCALE – dB

–130
–140

0 81921024 2048 3072 4096 5120 6144 7168

FREQUENCY – MHz

ENCODE = 65.0MSPS

= 1.24MHz

A

IN

= –1.004dBFS

A

IN

SNR = 64.88dB
SFDR = 78.81dBc

Figure 6. Single Tone @ 1.24 MHz

0
–10
–20

–30
–40
–50
–60
–70
–80
–90

–100
–110
–120

POWER RELATIVE TO FULL SCALE – dB

–130
–140

0 81921024 2048 3072 4096 5120 6144 7168

FREQUENCY – MHz

ENCODE = 65.0MSPS
A

= 17MHz

IN

A

= –1dBFS

IN

SNR = 63.83dB
SFDR = 78.22dBc

Figure 7. Single Tone @ 17 MHz

0
–10
–20

–30
–40
–50
–60
–70
–80
–90

–100
–110
–120

POWER RELATIVE TO FULL SCALE – dB

–130
–140

0 81921024 2048 3072 4096 5120 6144 7168

FREQUENCY – MHz

ENCODE = 65.0MSPS
AIN = 17MHz AND 18MHz
AIN = –7.067dBFS
SFDR = 78dBc

Figure 9. Two-Tone FFT @ 17 MHz/18 MHz

66

ENCODE = 65MHz

65

64

63

SNR – dB

62

61

60

1.24 32
ANALOG FREQUENCY – MHz

Figure 10. SNR vs. A

+258C

+1258C

–558C

17

IN

0
–10
–20

–30
–40
–50
–60
–70
–80
–90

–100
–110
–120

POWER RELATIVE TO FULL SCALE – dB

–130
–140

0 81921024 2048 3072 4096 5120 6144 7168

FREQUENCY – MHz

ENCODE = 65.0MSPS
AIN = 32MHz
A

= –1.021dBFS

IN

SNR = 64.11dB
SFDR = 78.14dBc

Figure 8. Single Tone @ 32 MHz

90

80

70

SFDR – dBFS

60

50

40

SFDR – dBc

30

20

10

0

–60.09

–70.18 –50.18

FUNDAMENTAL – dBFS

SFDR – dBc

SFDR – 75dB

AIN = 17MHz
ENCODE RATE 65MHz

–39.92 –30.07 –20.02 –10.1 –1.099

Figure 11. Single Tone SFDR (AIN @ 17 MHz) vs. Power
Level

–8–

REV. 0

90

FREQUENCY – MHz

–2

–7

0.02

–5

–4

–3

–6

0.06 0.1 0.5

–1

0

120 16060

LEVEL – dBFS

ENCODE RATE = 65MHz
ROOM TEMPERATURE

–8

–9

–10

0.04 0.08 0.3 20 14090

80 SFDR – dBc

70

60

50

40

30

20

SNR, WORST SPUR – dB, dBc

10

0

1.24 17

SNR – dB

ENCODE FREQUENCY = 65MHz
A

= –1dBFS

IN

32 37 65 80 100

ANALOG INPUT FREQUENCY – MHz

Figure 12. SNR/Harmonics to A

> Nyquist MSPS

IN

AD10265

Figure 13. Gain Flatness vs. Input Frequency

REV. 0

–9–

AD10265

THEORY OF OPERATION

Refer to the Functional Block Diagram. The AD10265 em­ploys three monolithic ADI components per channel (AD9631
AD9632 and AD6640), along with multiple passive resistor
networks and decoupling capacitors to fully integrate a com­plete 12-bit analog-to-digital converter.

The input signal is first passed through a precision laser-trimmed
resistor divider, allowing the user to externally select operation

with a full-scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by choosing

the proper input terminal for the application.

Since the AD6640 implements a true differential analog input,
the AD9631/AD9632 have been configured to provide a differ­ential input for the AD6640 ADC through ac-coupling. The ac
signal gain of the AD9631/AD9632 can be trimmed to provide a
constant differential input to the AD6640. This allows the con­verter to be used in multiple system applications without the
need for external gain circuit normally requiring trim. The
AD9631/AD9632 were chosen for their superior ac performance
and input drive capabilities, which have limited the ability of
many amplifiers to drive high performance ADCs. As new am­plifiers are developed, pin-compatible improvements are planned
to incorporate the latest operational amplifier technology.

APPLYING THE AD10265
Encoding the AD10265

Best performance is obtained by driving the encode pins differ­entially. However, the AD10265 is also designed to interface
with TTL and CMOS logic families. The source used to drive
the ENCODE pin(s) must be clean and free from jitter. Sources
with excessive jitter will limit SNR and overall performance.

TTL OR CMOS

SOURCE

0.01mF

Figure 14. Single-Ended TTL/CMOS Encode

The AD10265 encode inputs are connected to a differential
input stage (see Figure 4 under Equivalent Circuits). With no
input connected to either ENCODE pin, the voltage divider
biases the inputs to 1.6 volts. For TTL or CMOS usage, the
encode source should be connected to ENCODE. ENCODE
should be decoupled using a low inductance or microwave chip
capacitor to ground.

If a logic threshold other than the nominal +1.6 V is required,
the following equations show how to use an external resistor,

Rx, to raise or lower the trip point (see Figure 4, R1 = 17 kΩ,
R2 = 8 kΩ).

RR

52

V

=

1

RR RRx R Rx

12 1 2

x

++

to lower logic threshold.

AD10265

ENCODE

ENCODE

ENCODE
SOURCE

0.01mF

ENCODE

V

1

ENCODE

R

x

AD10265

+5V

R1

R2

Figure 15. Lower Threshold for Encode

R

V

52

=

1

R

2

RRx

1

+

RRx

1

+

to raise logic threshold.

AV

CC

R

x

ENCODE
SOURCE

0.01mF

V

1

ENCODE

ENCODE

AD10265

+5V

R1

R2

Figure 16. Raise Logic Threshold for Encode

While the single-ended encode will work well for many applica­tions, driving the encode differentially will provide increased
performance. Depending on circuit layout and system noise, a
1 dB to 3 dB improvement in SNR can be realized. It is recom­mended that differential TTL logic be used, however, because
most TTL families that support complementary outputs are not
delay or slew rate matched. Instead, it is recommended that the
encode signal be ac-coupled into the ENCODE and ENCODE
pins.

The simplest option is shown below. The low jitter TTL signal

is coupled with a limiting resistor, typically 100 Ω, to the pri-

mary side of an RF transformer (these transformers are inexpen­sive and readily available; part number in Figure 17 is from Mini­Circuits). The secondary side is connected to the ENCODE
and ENCODE pins of the converter. Since both encode inputs
are self-biased, no additional components are required.

100V

TTL ENCODE

T1–1T

AD10265

ENCODE

Figure 17. TTL Source—Differential Encode

A clean sine wave may be substituted for a TTL clock. In this
case, the matching network is shown below. Select a transformer
ratio to match source and load impedances. The input imped-

ance of the AD10265 encode is approximately 11 kΩ differen-

tially. Therefore “R,” shown in Figure 18, may be any value that
is convenient for available drive power.

SINE

SOURCE

T1–1T

ENCODE

R

AD10265

ENCODE

–10–

Figure 18. Sine Source—Differential Encode

REV. 0

AD10265

If a low jitter ECL clock is available, another option is to ac­couple a differential ECL signal to the encode input pins as
shown below. The capacitors shown here should be chip capaci­tors, but do not need to be of the low inductance variety.

ECL

GATE

510V

0.1mF

0.1mF

510V

–V

S

ENCODE

ENCODE

AD10265

Figure 19. Differential ECL for Encode

As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.

AD96687 (1/2)

50V

510V

0.1mF

0.1mF

510V

–V

S

ENCODE

ENCODE

AD10265

Figure 20. ECL Comparator for Encode

USING THE FLEXIBLE INPUT

The AD10265 has been designed with the user’s ease of opera­tion in mind. Multiple input configurations have been included
on board to allow the user a choice of input signal levels and

input impedance. While the standard inputs are ±0.5 V, ±1.0 V
and ±2.0 V, the user can select the input impedance of the

AD10265 on any input by using the other inputs as alternate
locations for GND or an external resistor. The following
chart summarizes the impedance options available at each
input location:

1 = 100 Ω when A

A

IN

A

1 = 75 Ω when A

IN

A

1 = 50 Ω when A

IN

2 = 200 Ω when A

A

IN

A

2 = 100 Ω when A

IN

A

2 = 75 Ω when A

IN

2 = 300 Ω, with A

A

IN

A

2 = 50 Ω when A

IN

A

2 = 100 Ω, with A

IN

3 = 400 Ω.

A

IN

A

3 = 100 Ω when AIN3 Has an External Resistor of 133 Ω to GND.

IN

A

3 = 75 Ω when AIN3 Has an External Resistor of 92 Ω to GND.

IN

3 = 50 Ω when AIN3 Has an External Resistor of 57 Ω to GND.

A

IN

2 and AIN3 Are Open.

IN

3 Is Shorted to GND.

IN

2 Is Shorted to GND.

IN

3 Is Open.

IN

3 Is Shorted to GND.

IN

2 to AIN3 Has an External Resistor of

IN

3 Shorted to GND.

IN

2 to AIN3 Has an External Resistor of

IN

3 Shorted to GND.

IN

GROUNDING AND DECOUPLING
Analog and Digital Grounding

Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom­mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signal
and its return path.

2. The minimization of the impedance associated with ground
and power paths.

3. The inherent distributed capacitor formed by the power
plane, PCB insulation and ground plane.

These characteristics result in both a reduction of electro­magnetic interference (EMI) and an overall improvement in
performance.

It is important to design a layout that prevents noise from cou­pling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. The AD10265 does not distinguish between
analog and digital ground pins as the AD10265 should always
be treated as an analog component. All ground pins should be
connected together directly under the AD10265. The PCB
should have a ground plane covering all unused portions of the
component side of the board to provide a low impedance path
and manage the power and ground currents. The ground plane
should be removed from the area near the input pins to reduce
stray capacitance.

LAYOUT INFORMATION

The schematic of the evaluation board (Figure 21) represents a
typical implementation of the AD10265. The pinout of the
AD10265 is very straightforward and facilitates ease of use
and the implementation of high frequency/high resolution
design practices. It is recommended that high quality ceramic
chip capacitors be used to decouple each supply pin to
ground directly at the device. All capacitors can be standard
high quality ceramic chip capacitors.

Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the AD6640 ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.

REV. 0

–11–

AD10265

–5VAA

+5VAB

–5VAA

J13 J14

–5VAA

+5VAB

J12 J15

+5VAB

+5VAA

J11 J16

+5VAA

E2

C23

0.1

+5VAA

SMA

SMA

J10

–5VAA

mF

+5VAA

0.1

J9

+5VAB

C7

0.1mF

–5VAB

–5VAB

GND

GND

GND

GND

+5VAA

GND

C2

mF

GND
GND

GND

D0A
D1A
D2A
D3A
D4A
D5A
D6A

D7A

D8A

R37
2kV

R38

348V

14

V

CC

OUT
V

EE

7

K1115

R5

50

V

R41
2kV

R42

348V

U4

14

V

CC

OUT
V

EE

7

K1115

R6

V

50

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

U3:A

1

3

2

74AS00

U2

C1

0.1mF

8

R39

T1

100

V

136

C29

0.1mF

U5:A

1
2

1:1

4

3

5

74AS00

C8

0.1

mF

8

R43

T2

V

100

136

C30

0.1mF

–5VAB

A2

IN

GND

A

9876543216867666564636261

A3

IN

GNDA

A

GNDA
GNDA
NCA
–5VAA
+5VAA
TESTA

NCA

D0A

D1A
D2A
D3A

D4A
D5A

D6A
D7A
D8A

GNDA

1:1

–5VAB

E1

C22

0.1mF

A2

A1

IN

IN

A

A

GND

A1

A2

IN

NCA

IN

NCA

A

GNDA

A

AD10265

U3:B

4
5

74AS00

5
4

U5:B

74AS00

5
4

GND

GND

GNDA

SHIELD

U1

GND

GNDB

6

BUFLATA

ENCAB

ENCA

6

BUFLATB

ENCBB

ENCB

+5VAB

–5VAB

+5VAB

GND

GNDB

B3

IN

A

B3

IN

A

B2

B1

IN

IN

A

A

B1

B2

IN

IN

A

A

GNDB
GNDB
GNDB

TESTB

GNDB
GNDB

ENCBB

ENCB

+3.3VDB

D11B

D10B

GNDB

GND

GNDB

NCB
NCB

D9B
D8B
D7B

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

BUFLATA

BUFLATB

GND
GND

GND

GND
GND
ENCBB
ENCB
+3.3VDB
D11B
D10B
D9B
D8B
D7B
GND

D8A
GND
GND
GND
GND

D9A

D10A
D11A

D0A

D1A

D2A

D3A

D4A

D5A

D6A

D7A

GND

D7B

D8B

D9B

D10B
D11B

GND
GND

D0B

D1B

D2B

D3B

D4B

D5B

D6B
GND

SMA

J3

9
8
7
6
5
4
3

2

11

1

9
8
7
6

5

4
3
2

11

1

9
8

7
6
5
4
3
2

11

1

9
8
7
6
5
4
3
2

11

1

U6

74LCX574

8D

8Q

7D

7Q

6D

6Q

5D

5Q

4D

4Q

3D

3Q

2D

2Q

1D

1Q

CLK

OC

U7

74LCX574

8D

8Q

7D

7Q

6D

6Q

5D

5Q

4D

4Q

3D

3Q

2D

2Q

1D

1Q

CLK

OC

OC

U8

74LCX574

8D

8Q

7D

7Q

6D

6Q

5D

5Q

4D

4Q

3D

3Q

2D

2Q

1D

1Q

CLK

OC

U9

74LCX574

8D

8Q

7D

7Q

6D

6Q

5D

5Q

4D

4Q

3D

3Q

2D

2Q

1D

1Q

CLK

OC

OC

12
13

SMA

A1

A

IN

12
13
14
15

16

17
18
19

12

13
14
15
16
17
18
19

12
13
14

15
16
17
18
19

12
13
14

15
16
17
18

19

U3:D

74AS00

J4

A

IN

R15

348V

B8A

R16

348V

B9A

R17

348V

B10A

R18

348V

B11A

R19

348V

B0A

R20

348V

R21

348V

R22

348

V

R23

348V

R24

348V

R13

348V

R14

348V

R26

348V

R27

348V

R28

348V

R29

348V

R30

348V

R31

348V

R32

348V

R33

348V

R34

348V

R35

348V

R36

348V

R25

348V

U3:C

9

11

8

10

74AS00

SMA

A2

SMA

J5

J6

A

A3

IN

B1A

B2A

B3A

B4A

B5A

B6A

B7A

B7B

B8B

B9B

B10B

B11B

B0B

B1B

B2B

B3B

B4B

B5B

B6B

U5:C

9

10

74AS00

A

B1

IN

BUFLATA 11

BUFLATB

8

SMA

J7

+3.3VDA

B11A

B10A

B9A
B8A
B7A

B6A

B5A
B4A

B3A

B2A

B1A

B0A
GND
GND

GND

GND
GND

+3.3VDA

B11B

B10B

B9B

B8B

B7B
B6B
B5B

B4B

B3B

B2B
B1B
B0B

GND

GND

GND
GND
GND

U5:D

12
13

74AS00

A

B2

IN

H40DM

J1

140
239
338
437
536
635
734
833
932

10 31

30
12 29
128

13
14 27
15 26
16 25
17 24
18 23
19 22
20 21

H40DM

J2

140
239
338
437
536
635
734
833
932

10 31

30

11
12 29

28

13
14 27
15 26
16 25
17 24
18 23
19 22
20 21

11

SMA

J8

A

B3

IN

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

+3.3VDA

NCB

NCB

D0B

D1B

D2B

D3B

D4B

D5B

D2B

D3B

D4B

D5B

D6B

D6B

D9A

ENCA

GNDA

2728293031323334353637383940414243

GND

ENCAB

ENCA

ENCAB

D9A

+3.3VDA

D10A

D10A

D11A

D11A

GND

GND

D0B

D1B

Figure 21. Evaluation Board Schematic

GNDB

GND

+3.3VDA

C25

10mF

–12–

+

0.1mF

+3.3VDB

C9

C10

C11

0.1mF

C12

0.1mF

0.1mF

C26

10mF

+

C16

0.1mF

C17

0.1mF

C18

0.1mF

0.1mF

C19

+5VAA +5VAB

C20

0.1mF

0.1mF

C21

REV. 0

AD10265

EVALUATION BOARD

The AD10265 evaluation board (Figure 22) is designed to
provide optimal performance for evaluation of the AD10265
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10265.

+5VAB –5VABGND

U4

J10

B1

A

IN

C21

ENCB

U1

C16

PIN 1

J6

B2

A

IN

J5

B3

A

IN

J8

Power to the analog supply pins is connected via banana jacks.
The analog supply powers the crystal oscillator, the associated
components and amplifiers, and the analog section of the
AD10265. The digital outputs of the AD10265 are powered via
Pin 1 of either J1 or J2 found on the digital interface connector
with +3.3 V. Contact the factory if additional layout or applica­tions assistance is required.

J2

R30

R29

R28

R27

R26

R25

C17

R36

R35

R34

R33

R32

R31

U8

U9

J3

A1

A

IN

J4

A2

A

IN

J7

+5VAA –5VAAGND

Figure 22. Evaluation Board Mechanical Layout

R18
R17

R16

U6

C23

U7

J9

A3

A

IN

ENCA

R22

R21

R20

R19

C2

C10

R14

R13

R24

R23

AD10265 EVALUATION BOARD

GS01685 ( 2 )

R15

YW

J1

REV. 0

–13–

AD10265

Figure 23. Top Layer

–14–

REV. 0

AD10265

REV. 0

Figure 24. Bottom Layer

–15–

AD10265

Figure 25. Power Plane Layer

–16–

REV. 0

AD10265

REV. 0

Figure 26. Ground Plane Layer

–17–

AD10265

0.060 (1.52)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Leaded Ceramic Chip Carrier

(Z-68A)

1.180 (29.97) SQ

0.950 (24.13) SQ

961

10

PIN 1

60

0.240 (6.096)

0.800

(20.32)

TOP VIEW

(PINS DOWN)

26

27

0.050 (1.27)

0.018 (0.457)

44

43

–18–

REV. 0