Datasheet ACT-SF2816N, ACT-SF2816N-39P3Q, ACT-SF2816N-39F18Q, ACT-SF2816N-37P7Q, ACT-SF2816N-37P3Q Datasheet (ACT)

FEATURES

eroflex Circuit Technology - Advanced Multichip Modules © SCD3853 REV B 5/18/99

www.aeroflex.com

ACT–SF2816 High Speed

128Kx16 SRAM / 512Kx16 FLASH

Multichip Module

CIRCUIT TECHNOLOGY

■ 2 – 128K x 8 SRAMs & 2 – 512K x 8 Flash Die in

One MCM

■ Access Times of 25ns (SRAM) and 60ns (Flash)

or 35ns (SRAM) and 70 or 90ns (Flash)

■ Organized as 128K x 16 of SRAM and 512K x 16

of Flash Memory with Separate Data Buses

■ Both Blocks of Memory are User Configurable as

512KX8 AND 1MX8 Respectively

■ Low Power CMOS

■ Input and Output TTL Compatible Design

■ MIL-PRF-38534 Compliant MCMs Available

■ Decoupling Capacitors and Multiple Grounds for

Low Noise

■ Industrial and Military Temperature Ranges

■ Industry Standard Pinouts

Note: Programming information available upon request

■ Packaging – Hermetic Ceramic

● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,

Aeroflex code# "P3"

● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With

Shoulder, Aeroflex code# "P7"

● 68 Lead, .94" x .94" x .140" Single-Cavity Small

Outline Gull Wing, Aeroflex code# "F18" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)

■ DESC SMD – TBD

FLASH MEMORY FEATURES

■ Sector Architecture (Each Die)

● 8 Equal Sectors of 64K bytes each

● Any combination of sectors can be erased with one

command sequence

■ +5V Programing, +5V Supply

■ Embedded Erase and Program Algorithms

■ Hardware and Software Write Protection

■ Internal Program Control Time.

■ 10,000 Erase / Program Cycles

Block Diagram – PGA Type Packages (P3 & P7) & CQFP (F18)

FCE1 FWE2FWE1SWE2SWE1 SCE1 SCE2

OE

A0 – A18

128Kx8

SRAM

8 8 8 8

SI/O0-7 SI/O8-15 FI/O0-7 FI/O8-15

128Kx8

SRAM

512Kx8

Flash

FCE2

FI/O

SI/O

512Kx8

Flash

Pin Description

0-15 Flash Data I/O

0-15 SRAM Data I/O

0–18 Address Inputs

A

1-2 Flash Write Enables

FWE

1-2 SRAM Write Enables

SWE

1-2 Flash Chip Enables

FCE

1-2 SRAM Chip Enables

SCE

OE

NC Not Connected

CC Power Supply

V

GND Ground

Output Enable

Absolute Maximum Ratings

Symbol Rating Range Units

-55 to +125 °C

-65 to +150 °C

-0.5 to +7 V

300 °C

T

T

STG

V

T

C

Operating Temperature

Storage Temperature

G

L

Maximum Signal Voltage to Ground

Maximum Lead Temperature (10 seconds)

Parameter

Flash Data Retention 10 Years

Flash Endurance (Write/Erase Cycles) 10,000

Normal Operating Conditions

Symbol Parameter Minimum Maximum Units

V

CC

V

IH

V

IL

Power Supply Voltage

Input High Voltage

Input Low Voltage

+4.5 +5.5 V

+2.2 V

+ 0.3 V

CC

-0.5 +0.8 V

Capacitance

(V

= 0V, f = 1MHz, TC = 25°C)

IN

Symbol Parameter Maximum Units

AD

C

OE

C

WE1,2

C

CE1,2

C

I/O

C

These parameters are guaranteed by design but not tested

A0 – A18 Capacitance

OE Capacitance

F/S Write Enable Capacitance

F/S Chip Enable Capacitance

I/O0 – I/O15 Capacitance

50 pF

50 pF

20 pF

20 pF

20 pF

DC Characteristics

(VCC = 5.0V, VSS = 0V, Tc = -55°C to +125°C, unless otherwise indicated)

Parameter Sym Conditions Min Max Units

I

Input Leakage Current

Output Leakage Current

SRAM Operating Supply Current x 16
Mode

I

CC

Standby Current

SRAM Output Low Voltage

SRAM Output High Voltage

Flash Vcc Active Current for Read (1)

Flash Vcc Active Current for Program

or Erase (2)

Flash Output Low Voltage

Flash Output High Voltage

Flash Low Vcc Lock Out Voltage

Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The
frequency component typically is less than 2mA/MHz, with OE
erase) is in progress 3) DC test conditions: V

V

V

I

I

V

V

V

IL = 0.3V, VIH = VCC - 0.3V

VCC = Max, VIN=0toV

LI

FCE = SCE = VIH, OE = V

I

LO

V

=0toV

OUT

SCE

x16

I

SB

OL

OH

CC1

CC2

OL

OH

LKO

= VIL, OE = VIH, f = 5MHz, VCC =

Max, FCE

FCE = SCE = VIH, OE = VIH, f = 5MHz,

= Max

V

CC

IOL = 8 mA, VCC = Min, FCE = V

IOH = -4.0 mA, , VCC = Min, FCE = V

FCE = VIL, OE = VIH, SCE = V

FCE = VIL, OE = VIH, SCE = V

IOL = 8 mA, VCC = Min, SCE = V

IOH = -2.5 mA, , VCC = Min, SCE = V

CC

= V

IH

at VIH 2) ICC active while Embedded Algorithim (program or

CC

IH,

IH

IH

IH

IH

IH

IH

2.4 V

0.85 x VCC V

3.2 V

10 µA

10 µA

325 mA

40 mA

0.4 V

130 mA

150 mA

0.45 V

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SRAM AC Characteristics

(VCC = 5.0V, VSS= 0V, Tc= -55°C to +125°C)

Read Cycle

Parameter Symbol

Read Cycle Time

Address Access Time

Chip Select Access Time

Output Hold from Address Change

Output Enable to Output Valid

Chip Select to Output in Low Z *

Output Enable to Output in Low Z *

Chip Deselect to Output in High Z *

Output Disable to Output in High Z *

* Parameters guaranteed by design but not tested

Write Cycle

Parameter Symbol

Write Cycle Time

Chip Select to End of Write

Address Valid to End of Write

Data Valid to End of Write

Write Pulse Width

Address Setup Time

Output Active from End of Write *

Write to Output in High Z *

Data Hold from Write Time

Address Hold Time

* Parameters guaranteed by design but not tested

t

t

t

ACE

t

t

t

CLZ

t

OLZ

t

CHZ

t

OHZ

t

WC

t

CW

t

AW

t

DW

t

WP

t

t

OW

t

WHZ

t

DH

t

RC

AA

OH

OE

AS

AH

–025

Min Max

–035

Min Max

Units

25 35 ns

25 35 ns

25 35 ns

0 0 ns

15 20 ns

3 3 ns

0 0 ns

12 20 ns

12 20 ns

–025

Min Max

–035

Min Max

Units

25 35 ns

20 25 ns

20 25 ns

15 20 ns

20 25 ns

0 0 ns

0 0 ns

10 20 ns

0 0 ns

0 0 ns

Truth Table

Mode SCE OE SWE Data I/O Power

Standby H X X High Z Standby

Read L L H Data Out Active

Output Disable L H H High Z Active

Write L X L Data In Active

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Timing Diagrams — SRAM

Read Cycle Timing Diagrams

Read Cycle 1 (SCE = OE = VIL, SWE = VIH)

tRC

A0-18

tAA

tOH

DI/O

Read Cycle 2 (SWE = VIH)

tRC

A0-18

tAA

SCE

tACE

SEE NOTE

Data Valid

OE

DI/O

tCLZ

SEE NOTE

tOLZ

SEE NOTE

High Z

OE

t

Data ValidPrevious Data Valid

tCHZ

t

OHZ

SEE NOTE

Write Cycle Timing Diagrams

Write Cycle (SWE Controlled, OE = VIH)

tWC

A0-18

tAW tAH

tWHZ

tCW

tDW

Data Valid

tWC

tAW

tCW

tWP

tDW

Data Valid

SCE

tAS tWP

SWE

DI/O

Write Cycle (SCE

A0-18

tAS

SCE

SWE

DI/O

SEE NOTE

Controlled, OE = VIH )

tOW

tDH

tAH

tDH

UNDEFINED

DON’T CARE

Note: Guaranteed by design, but not tested.

AC Test Circuit

Current Source

IOL

Z ~ 1.5 V (Bipolar Supply)

IOH

V

Input and Output Timing Reference Level 1.5 V

To Device Under Test

C

L = 50 pF

Current Source

Notes:

Z is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance

1) V

O =75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance

Z
load circuit. 6) ATE Tester includes jig capacitance.

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AC Test Conditions

Parameter Typical Units

Input Pulse Level 0 – 3.0 V

Input Rise and Fall 5 ns

SCD3853 REV B 5/18/99 Plainview NY [phone]

Flash AC Characteristics – Read Only Operations

Parameter

Read Cycle Time

Address Access Time

Chip Enable Access Time

Output Enable to Output Valid

Chip Enable to Output High Z (1)

Output Enable High to Output High Z(1)

Output Hold from Address, CE

Note 1. Guaranteed by design, but not tested

or OE Change, Whichever is First

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Symbol

JEDEC Stand’d

t

AVAV tRC 60 70 90 ns

AVQV tACC 60 70 90 ns

t

ELQV tCE 60 70 90 ns

t

GLQV tOE 30 35 35 ns

t

EHQZ tDF 20 20 20 ns

t

GHQZ tDF 20 20 20 ns

t

t

AXQX tOH 0 0 0 ns

–60

Min Max

–70

Min Max

–90

Min Max

Units

Flash AC Characteristics – Write / Erase / Program Operations, FWE Controlled

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Write Cycle Time

Chip Enable Setup Time

Write Enable Pulse Width

Address Setup Time

Data Setup Time

Data Hold Time

Address Hold Time

Write Enable Pulse Width High

Duration of Byte Programming Operation

Sector Erase Time

Read Recovery Time before Write

Vcc Setup Time

Chip Programming Time

Chip Enable Hold Time

Chip Erase Time

Symbol

JEDEC Stand’d

t

AVAC tWC 60 70 90 ns

ELWL tCE 0 0 0 ns

t

WLWH tWP 40 45 45 ns

t

AVWL tAS 0 0 0 ns

t

DVWH tDS 40 45 45 ns

t

WHDX tDH 0 0 0 ns

t

WLAX tAH 45 45 45 ns

t

WHWL tWPH 20 20 20 ns

t

WHWH1 14 TYP 14 TYP 14 TYP µs

t

WHWH2 30 30 30 Sec

t

tGHWL 0 0 0 µs

VCE 50 50 50 µs

t

1

OEH

t

WHWH3 120 120 120 Sec

t

–60

Min Max

–70

Min Max

–90

Min Max

50 50 50 Sec

10 10 10 ns

1. Toggle and Data Polling only.

Flash AC Characteristics – Write / Erase / Program Operations, FCE Controlled

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Write Cycle Time

Write Enable Setup Time

Chip Enable Pulse Width

Address Setup Time

Data Setup Time

Data Hold Time

Address Hold Time

Chip Enable Pulse Width High

Duration of Byte Programming

Sector Erase Time

Read Recovery Time

Chip Programming Time

Chip Erase Time

Symbol

JEDEC Stand’d

t

AVAC tWC 60 70 90 ns

WLEL tWS 0 0 0 ns

t

ELEH tCP 40 45 45 ns

t

AVEL tAS 0 0 0 ns

t

DVEH tDS 40 45 45 ns

t

EHDX tDH 0 0 0 ns

t

ELAX tAH 45 45 45 ns

t

EHEL tCPH 20 20 20 ns

t

WHWH1 14 TYP 14 TYP 14 TYP µs

t

WHWH2 30 30 30 Sec

t

tGHEL 0 0 0 ns

WHWH3 120 120 120 Sec

t

–60

Min Max

–70

Min Max

Min Max

50 50 50 Sec

–90

Units

Units

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AC Waveforms for Flash Memory Read Operations

tRC

Addresses Addresses Stable

tACC

FCE

tDF

OE

FWE

Outputs

Write/Erase/Program
Operation for Flash Memory, F

Addresses

FCE

OE

5555H PA

tWC

tAS

tGHWL

tAH

tOE

WE Controlled

Data

Polling

Output Valid

PA

tOHtCE

High ZHigh Z

tRC

FWE

Data

5.0V

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.

3. D7 is the 0utput of the complement of the data written to the deviced.

4. Dout is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

Aeroflex Circuit Technology

tDS

tCE

tWP

tWPH

tDH

t

WHWH1

6

D7

tOE

tDF

DOUTPDAOH

tOH

tCE

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AC Waveforms Chip/Sector
Erase Operations for Flash Memory

AH

t

Data

Polling

Addresses

FCE

OE

FWE

Data

CC

V

5555H

tAS

tGHWL

tWP

tWPH

tCE

tDH

55H AAH80H 55H 10H/30HAAH

tDS

tVCE

Notes:

1. SA is the sector address for sector erase.

5555H 5555H SA2AAAH 2AAAH

AC Waveforms for Data Polling
During Embedded Algorithm Operations for Flash Memory

FCE

OE

FWE

tCH

DQ7

DQ0-DQ6

tOEH

tOE

tDF

tCE

tOH

*

DQ

7

DQ7=

Valid Data

tWHWH1 or 2

DQ0–DQ6=Invalid

DQ0–DQ6
Valid Data

tOE

* DQ7=Valid Data (The device has completed the Embedded operation).

High Z

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Write/Erase/Program Operation for Flash Memory, FCE Controlled

Data

Polling

Addresses

FCE

OE

FWE

Data

5.0V

5555H

tWC

PA

tAHtAS

tGHWL

tWS

tCP

tCPH

t

WHWH1

tDH

tDS

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.

3. D7

is the 0utput of the complement of the data written to the device.

4. D

OUT is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

PA

D7

DOUTPDAOH

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Pin Numbers & Functions

66 Pins — PGA-Type

Pin # Function Pin # Function Pin # Function Pin # Function

1 SI/O

2 SI/O9 19 Vcc 36 FI/O10 53 FCE1

3 SI/O10 20 SCE1 37 A6 54 GND

4 A

5 A14 22 SI/O3 39 NC 56 FI/O15

6 A15 23 SI/O15 40 A8 57 FI/O14

7 A16 24 SI/O14 41 A9 58 FI/O13

8 A17 25 SI/O13 42 FI/O0 59 FI/O12

9 SI/O0 26 SI/O12 43 FI/O1 60 A0

10 SI/O1 27 OE 44 FI/O2 61 A1

11 SI/O2 28 A18 45 VCC 62 A2

12 SWE2 29 SWE1 46 FCE2 63 FI/O7

13 SCE2 30 SI/O7 47 FWE2 64 FI/O6

14 GND 31 SI/O6 48 FI/O11 65 FI/O5

15 SI/O11 32 SI/O5 49 A3 66 FI/O4

16 A10 33 SI/O4 50 A4

17 A11 34 FI/O8 51 A5

8 18 A12 35 FI/O9 52 FWE1

13 21 NC 38 A7 55 FI/O3

"P3" — 1.08" SQ PGA Type Package Standard (without shoulders
"P7" — 1.08" SQ PGA Type Package (with shoulders on Pins 1, 11, 56 & 66)

Side View

(P7)

All dimensions in inches

.185
MAX

.025
.035

.050 DIA

.100

TYP

.020
.016

.145

MIN

TYP

Side View

(P3)

.160

MAX

.100 TYP

.020
.016

.165

MIN

Pin 56

Pin 66

)

Bottom View (P7 & P3)

1.085 SQ
MAX

1.000
TYP

.600

TYP

.100 TYP

Pin 1

1.000
TYP

Pin 11

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Pin Numbers & Functions

68 Pins — Dual-Cavity CQFP

Pin # Function Pin # Function Pin # Function Pin # Function

1 GND 18 GND 35 OE

2 FCE

1 19 SI/O8 36 SCE2 53 FI/O7

3 A5 20 SI/O9 37 A17 54 FI/O6

4 A4 21 SI/O10 38 SWE2 55 FI/O5

5 A3 22 SI/O11 39 FWE1 56 FI/O4

6 A2 23 SI/O12 40 FWE2 57 FI/O3

7 A1 24 SI/O13 41 A18 58 FI/O2

8 A0 25 SI/O14 42 NC 59 FI/O1

9 NC 26 SI/O15 43 NC 60 FI/O0

10 SI/O0 27 Vcc 44 FI/O15 61 VCC

11 SI/O1 28 A11 45 FI/O14 62 A10

12 SI/O2 29 A12 46 FI/O13 63 A9

13 SI/O3 30 A13 47 FI/O12 64 A8

14 SI/O4 31 A14 48 FI/O11 65 A7

15 SI/O5 32 A15 49 FI/O10 66 A6

16 SI/O6 33 A16 50 FI/O9 67 SWE1

17 SI/O7 34 SCE1 51 FI/O8 68 FCE2

52 GND

"F18" — CQFP Package

.990 SQ
±.010

.950 SQ

Pin 9

Pin 10

Pin 26

MAX

.800 REF

Pin 61

Pin 60

Pin 44

Pin 43Pin 27

.015

±.002

.050

TYP

.890 SQ

REF

.140

MAX

.640 SQ

REF

.008
±.002

.050

REF

Detail “A”

Metal spacer

.010

±.008

.015

±.002

All dimensions in inches

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See Detail “A”

SCD3853 REV B 5/18/99 Plainview NY [phone]

CIRCUIT TECHNOLOGY

Ordering Information

Model Number DESC SMD Number Speed Package

ACT–SF2816N–26P3Q

ACT–SF2816N–37P3Q

ACT–SF2816N–39P3Q

ACT–SF2816N–26P7Q

ACT–SF2816N–37P7Q

ACT–SF2816N–39P7Q

ACT–SF2816N–26F18Q

ACT–SF2816N–37F18Q

ACT–SF2816N–39F18Q

Note: (S) = Speed for SRAM, (F) = Speed for FLASH

ACT– S F 28 16 N– 26 P7 Q

Aeroflex Circuit
Technology

Memory Type

SF = SRAM Flash Combo Module

Memory Depth

2 = 2M SRAM, 8 = Locations

Memory Width, Bits

Options, N = none

Memory Speed Code

26 = 25ns SRAM & 60ns FLASH
37 = 35ns SRAM & 70ns FLASH
39 = 35ns SRAM & 90ns FLASH

TBD 25(S) / 60(F) ns 1.08"sq PGA-Type

TBD 35(S) / 70(F) ns 1.08"sq PGA-Type

TBD 35(S) / 90(F) ns 1.08"sq PGA-Type

TBD 25(S) / 60(F) ns 1.08"sq PGA-Type

TBD 35(S) / 70(F) ns 1.08"sq PGA-Type

TBD 35(S) / 90(F) ns 1.08"sq PGA-Type

TBD 25(S) / 60(F) ns .94"sq CQFP

TBD 35(S) / 70(F) ns .94"sq CQFP

TBD 35(S) / 90(F) ns .94"sq CQFP

Part Number Breakdown

C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screening
Q = MIL-PRF-38534 Compliant / SMD

Surface Mount Packages Thru-Hole Packages

F18 = .94"SQ 68 Lead Dual-Cavity
CQFP

* Screened to the individual test methods of MIL-STD-883

Screening

*

Package Type & Size

P3 = 1.085"SQ PGA 66 Pins

with out shoulder

P7 = 1.085"SQ PGA 66 Pins

with shoulder

Specifications subject to change without notice.

Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830

Aeroflex Circuit Technology

Telephone: [phone]

FAX: [phone]

Toll Free Inquiries: 1-[phone]

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