Datasheet ACT-SF128K32N-39P1T, ACT-SF128K32N-39P1Q, ACT-SF128K32N-39P1M, ACT-SF128K32N-39P1I, ACT-SF128K32N-39P1C Datasheet (ACT)

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ACT-SF128K32 High Speed

128Kx32 SRAM / 128Kx32 Flash

Multichip Module

FEATURES

■

4 – 128K x 8 SRAMs & 4 – 128K x 8 Flash Die

in One MCM

■ Access Times of 25ns (SRAM) and 60ns

(Flash) or 35ns (SRAM) and 70ns or
90ns (Flash)

■ Organized as 128K x 32 of SRAM and 128K x

32 of Flash Memory with Common Data Bus

■ Low Power CMOS

■ Input and Output TTL Compatible Design

■ MIL-PRF-38534 Compliant MCMs Available

■ Decoupling Capacitors and Multiple

Grounds for Low Noise

■ Commercial, Industrial and Military

Temperature Ranges

■ Industry Standard Pinouts

■ TTL Compatible Inputs and Outputs

■ Packaging – Hermetic Ceramic

● 66–Lead, PGA-Type, 1.385"SQ x 0.245"max,

Aeroflex code# P3,P7 without/with shoulders

CIRCUIT TECHNOLOGY

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FLASH MEMORY FEATURES

■ Sector Architecture (Each Die)

● 8 Equal Sectors of 16K bytes each

● Any combination of sectors can be erased with

one command sequence.

■ +5V Programing, +5V Supply

■ Embedded Erase and Program Algorithms

■ Hardware and Software Write Protection

■ Page Program Operation and Internal

Program Control Time.

■ 10,000 Erase/Program Cycles

ISO

900

1

I

Block Diagram – PGA Type Package (P3 & P7)

FWE4 SWE4 PIN DESCRIPTION

I/O

0-31 Data I/O

A

0–16 Address Inputs

FWE

1-4 Flash Write Enables

SWE

1-4 SRAM Write Enables

128K X 8 FLASH

128K X 8 SRAM

FCE

SCE

OE
NC Not Connected

V

CC Power Supply

GND Ground

Flash Chip Enable

SRAM Chip Enable

Output Enable

OE

A0–A16

SCE
FCS

FWE1

128K X 8 FLASH

128K X 8 SRAM

SWE1

FWE2 SWE2

128K X 8 FLASH

128K X 8 SRAM

I/O8-15 I/O16-23I/O0-7 I/O24-31

FWE3 SWE3

128K X 8 FLASH

128K X 8 SRAM

Absolute Maximum Ratings

Symbol Rating Range Units

-55 to +125 °C

-65 to +150 °C

-0.5 to +7 V
300 °C

T

T

STG

V

T

Operating Temperature

C

Storage Temperature
Maximum Signal Voltage to Ground

G

Maximum Lead Temperature (10 seconds)

L

Parameter

Flash Data Retention 10 Years
Flash Endurance (Write/Erase Cycles) 10,000

Normal Operating Conditions

Symbol Parameter Minimum Maximum Units

V

CC

V

IH

V

IL

Power Supply Voltage
Input High Voltage
Input Low Voltage

+4.5 +5.5 V
+2.2 V

+ 0.3 V

CC

-0.5 +0.8 V

Capacitance

(V

= 0V, f = 1MHz, TC = 25°C)

IN

Symbol Parameter Maximum Units

AD

C
C

WE1-4

C

C
C

This parameter is guaranteed by design but not tested

A0 – A18 Capacitance

OE

OE Capacitance
F/S Write Enable Capacitance

CE

F/S Chip Enable Capacitance

I/O

I/O0 – I/O31 Capacitance

80 pF
80 pF
30 pF
50 pF
30 pF

DC Characteristics

(VCC = 5.0V, VSS = 0V, TC = -55°C to +125°C)

Parameter Sym Conditions Min Max Units

I

Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 32

Mode

I

CC

Standby Current
SRAM Output Low Voltage

SRAM Output High Voltage
Flash Vcc Active Current for Read (1)
Flash Vcc Active Current for Program

or Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Low Vcc Lock Out Voltage

Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The
frequency component typically is less than 2mA/MHz, with OE
erase) is in progress 3) DC test conditions: V

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V
V
I

I

V
V
V

IL = 0.3V, VIH = VCC - 0.3V

VCC = Max, VIN=0toV

LI

FCE = SCE = VIH, OE = V

I

LO

V

=0toV

OUT

SCE

x32

I

SB

OL

OH

CC1

CC2

OL

OH1

LKO

= VIL, OE = VIH, f = 5MHz, VCC =

Max, FCE

FCE = SCE = VIH, OE = VIH, f = 5MHz,

= Max

V

CC

IOL = 8 mA, VCC = Min, FCE = V
IOH = -4.0 mA, , VCC = Min, FCE = V
FCE = VIL, OE = VIH, SCE = V

FCE = VIL, OE = VIH, SCE = V
IOL = 12 mA, VCC = Min, SCE = V

IOH = -2.5 mA, , VCC = Min, SCE = V

CC

= V

IH

at VIH 2) ICC active while Embedded Algorithim (program or

2

CC

IH,

IH

IH

IH

IH

IH

IH

2.4 V

0.85 x VCC V

3.2 4.2 V

10 µA
10 µA

550 mA

80 mA

0.4 V

220 mA
280 mA

0.45 V

SRAM AC Characteristics

(VCC = 5.0V, VSS= 0V, TC = -55°C to +125°C)

Read Cycle

Parameter Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Output Enable to Output Valid
Chip Select to Output in Low Z *
Output Enable to Output in Low Z *
Chip Deselect to Output in High Z *
Output Disable to Output in High Z *
* Parameters guaranteed by design but not tested

Write Cycle

Parameter Symbol

Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Output Active from End of Write *
Write to Output in High Z *
Data Hold from Write Time
Address Hold Time
* Parameters guaranteed by design but not tested

t
t

t

ACE

t
t

t

CLZ

t

OLZ

t

CHZ

t

OHZ

t

WC

t

CW

t

AW

t

DW

t

WP

t

t

OW

t

WHZ

t

DH

t

RC

AA

OH
OE

AS

AH

–025

Min Max

–035

Min Max

Units

25 35 ns

25 35 ns
25 35 ns

0 0 ns

15 20 ns
3 3 ns
0 0 ns

12 20 ns

12 20 ns

–025

Min Max

–035

Min Max

Units

25 35 ns
20 25 ns
20 25 ns
15 20 ns
20 25 ns

0 0 ns
0 0 ns

10 20 ns
0 0 ns
0 0 ns

SRAM Truth Table

Mode SCE OE SWE Data I/O Power

Standby H X X High Z Standby

Read L L H Data Out Active

Output Disable L H H High Z Active

Write L X L Data In Active

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3

Timing Diagrams — SRAM

Read Cycle Timing Diagrams

Read Cycle 1 (SCE = OE = VIL, SWE = VIH)

tRC

A0-16

tAA

tOH

DI/O

Read Cycle 2 (SWE = VIH)

tRC

A0-16

tAA

SCE

OE

DI/O

tCLZ

SEE NOTE

tOLZ

SEE NOTE

High Z

tACE

OE

t

SEE NOTE

Data Valid

Data ValidPrevious Data Valid

tCHZ

t

OHZ

SEE NOTE

Write Cycle Timing Diagrams

Write Cycle (SWE Controlled, OE = VIH)

tWC

A0-16

tAW tAH

tWHZ

tCW

tDW

Data Valid

tWC

tAW

tCW

tWP

tDW

Data Valid

SCE

tAS tWP

SWE

DI/O

Write Cycle (SCE

A0-16

tAS

SCE

SWE

DI/O

SEE NOTE

Controlled, OE = VIH )

tOW

tDH

tAH

tDH

UNDEFINED

DON’T CARE

Note: Guaranteed by design, but not tested.

AC Test Circuit

Current Source

IOL

Z ~ 1.5 V (Bipolar Supply)

To Device Under Test

C

L = 50 pF

Current Source

V

OH

I

Input and Output Timing Reference Level 1.5 V

Notes:

1) V

Z is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance

Z

O =75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance

load circuit. 6) ATE Tester includes jig capacitance.

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4

AC Test Conditions

Parameter Typical Units

Input Pulse Level 0 – 3.0 V

Input Rise and Fall 5 ns

Flash AC Characteristics – Read Only Operations

(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)

Parameter

Read Cycle Time tAVAV tRC 60 70 90 ns
Address Access Time t
Chip Enable Access Time t
Output Enable to Output Valid t
Chip Enable to Output High Z (1) t
Output Enable High to Output High Z(1) t
Output Hold from Address, CE
Note 1. Guaranteed by design, but not tested

or OE Change, Whichever is First tAXQX tOH 0 0 0 ns

Symbol

JEDEC Stand’d

AVQV tACC 60 70 90 ns
ELQV tCE 60 70 90 ns
GLQV tOE 30 35 40 ns
EHQZ tDF 20 20 25 ns
GHQZ tDF 20 20 25 ns

–60

Min Max

–70

Min Max

–90

Min Max

Units

Flash AC Characteristics – Write/Erase/Program Operations, FWE Controlled

(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)

Parameter

Write Cycle Time tAVAC tWC 60 70 90 ns
Chip Enable Setup Time t
Write Enable Pulse Width t
Address Setup Time t
Data Setup Time t
Data Hold Time t
Address Hold Time t
Chip Enable Hold Time t
Write Enable Pulse Width High t
Duration of Byte Programming Operation t
Sector Erase Time t
Chip Erase Time t
Read Recovery Time before Write t
Vcc Setup Time t
Output Enable Setup Time t
Output Enable Hold Time
Note: 1. For Toggle and Data Polling.

1

tOEH 10 10 10 ns

Symbol

JEDEC Stand’d

ELWL tCE 0 0 0 ns

WLWH tWP 30 35 45 ns

AVWL tAS 0 0 0 ns
DVWH tDS 30 30 45 ns
WHDX tDH 0 0 0 ns

WLAX tAH 45 45 45 ns
WHEH tCH 0 0 0 ns
WHWL tWPH 20 20 20 ns

WHWH1 14 TYP 14 TYP 14 TYP µs
WHWH2 60 60 60 Sec
WHWH3 120 120 120 Sec

GHWL 0 0 0 µs

VCE 50 50 50 µs
OES 12.5 12.5 12.5 Sec

–60

Min Max

–70

Min Max

–90

Min Max

Units

Flash AC Characteristics – Write/Erase/Program Operations, FCE Controlled

(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)

Parameter

Write Cycle Time tAVAC tWC 60 70 90 ns
Write Enable Setup Time t
Chip Enable Pulse Width t
Address Setup Time t
Data Setup Time t
Data Hold Time t
Address Hold Time t
Write Enable Hold from Write Enable High t
Chip Enable Pulse Width High t
Duration of Byte Programming t
Sector Erase Time t
Chip Erase Time t
Read Recovery Time
Chip Programming Time 12.5 12.5 12.5 Sec

Symbol

JEDEC Stand’d

WLEL tWS 0 0 0 ns

ELEH tCP 35 35 50 ns
AVEL tAS 0 0 0 ns
DVEH tDS 30 30 50 ns
EHDX tDH 0 0 0 ns
ELAX tAH 45 45 50 ns

EHWH tWH 0 0 0 ns

EHEL tCPH 20 20 20 ns
WHWH1 14 TYP 14 TYP 14 TYP µs
WHWH2 60 60 60 Sec
WHWH3 120 120 120 Sec

tGHEL 0 0 0 ns

–60

Min Max

–70

Min Max

–90

Min Max

Units

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5

AC Waveforms for Flash Memory Read Operations

tRC

Addresses Addresses Stable

tACC

FCE

tDF

OE

FWE

Outputs

Write/Erase/Program
Operation for Flash Memory, F

Addresses

FCE

OE

5555H PA

tWC

tAS

tGHWL

tAH

tOE

WE Controlled

Data

Polling

Output Valid

PA

tOHtCE

High ZHigh Z

tRC

tWP

FWE

Data

5.0V

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.

3. D7 is the 0utput of the complement of the data written to the deviced.

4. Dout is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

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tCE

tDS

tWPH

tDH

t

WHWH1

6

D7

tOE

tDF

DOUTPDAOH

tOH

tCE

AC Waveforms Chip/Sector
Erase Operations for Flash Memory

AH

t

Data

Polling

Addresses

FCE

OE

FWE

Data

CC

V

5555H

tAS

tGHWL

tWP

tWPH

tCE

tDH

tDS

tVCE

Notes:

1. SA is the sector address for sector erase.

5555H 5555H SA2AAAH 2AAAH

55H AAH80H 55H 10H/30HAAH

AC Waveforms for Data Polling
During Embedded Algorithm Operations for Flash Memory

FCE

OE

FWE

tCH

DQ7

DQ0-DQ6

tOEH

tOE

tDF

tCE

tOH

*

DQ

7

DQ7=

Valid Data

tWHWH1 or 2

DQ0–DQ6=Invalid

DQ0–DQ6
Valid Data

tOE

* DQ7=Valid Data (The device has completed the Embedded operation).

High Z

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7

Write/Erase/Program Operation for Flash Memory, FCE Controlled

Data

Polling

Addresses

FCE

OE

FWE

Data

5.0V

5555H

tWC

PA

tAHtAS

tGHWL

tWS

tCP

tCPH

t

WHWH1

tDH

tDS

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.
is the 0utput of the complement of the data written to the device.

3. D7

OUT is the output of the data written to the device.

4. D

5. Figure indicates last two bus cycles of four bus cycle sequence.

PA

D7

DOUTPDAOH

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8

Pin Numbers & Functions

66 Pins — PGA-Type

Pin # Function Pin # Function Pin # Function Pin # Function

1 I/O
2 I/O9 19 Vcc 36 I/O26 53 SWE3
3 I/O10 20 FCE 37 A7 54 GND
4 A
5 A16 22 I/O3 39 SWE1 56 I/O31
6 A11 23 I/O15 40 A13 57 I/O30
7 A0 24 I/O14 41 A8 58 I/O29
8 NC 25 I/O13 42 I/O16 59 I/O28

9 I/O0 26 I/O12 43 I/O17 60 A1
10 I/O1 27 OE 44 I/O18 61 A2
11 I/O2 28 NC 45 VCC 62 A3
12 FWE2 29 FWE1 46 SWE4 63 I/O23
13 SCE2 30 I/O7 47 FWE4 64 I/O22
14 GND 31 I/O6 48 I/O27 65 I/O21
15 I/O11 32 I/O5 49 A4 66 I/O20
16 A10 33 I/O4 50 A5
17 A9 34 I/O24 51 A6

8 18 A15 35 I/O25 52 FWE3

14 21 SCE 38 A12 55 I/O19

"P3" — 1.08" SQ PGA Type Package Standard (without shoulders

)

"P7" — 1.08" SQ PGA Type Package (with shoulders on Pins 1, 11, 56 & 66)

Bottom View (P7 & P3)

Side View

(P7)

.185
MAX

.025
.035

.050 DIA

.100

TYP

.020
.016

.145

MIN

All dimensions in inches

TYP

Side View

(P3)

.160
MAX

.100 TYP

.020
.016

.165

MIN

Pin 56

Pin 66

1.085 SQ
MAX

1.000
TYP

.600

TYP

.100 TYP

Pin 1

1.000
TYP

Pin 11

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9

CIRCUIT TECHNOLOGY

Ordering Information

Model Number DESC Part Number Speed Package

ACT-SF128K32N–26P1X
ACT-SF128K32N–37P1X
ACT-SF128K32N–39P1X

Note: (S) = Speed for SRAM, (F) = Speed for FLASH

ACT– SF 128K 32 N– 26 P1 M

Aeroflex Circuit
Technology

Memory Type

SF = SRAM Flash Combo Module

Memory Depth, Locations

Memory Width, Bits

Pinout Options

N = none

Memory Speed (Code)

26 = 25ns SRAM / 60ns FLASH
37 = 35ns SRAM / 70ns FLASH
39 = 35ns SRAM / 90ns FLASH

TBD 25(S) / 60(F) ns 1.08"sq PGA-Type
TBD 35(S) / 70(F) ns 1.08"sq PGA-Type
TBD 35(S) / 90(F) ns 1.08"sq PGA-Type

Part Number Breakdown

C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C Screened
Q = MIL-PRF-38534 Compliant/SMD

P3 = 1.08"SQ PGA 66 Pins WO/Shoulder
P7 = 1.08"SQ PGA 66 Pins W/Shoulder

Screening

Package Types & Sizes

Thru-Hole Packages

*

* Screened to the individual test methods of MIL-STD-883

Specifications subject to change without notice.

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