Datasheet ACT-SF128K16N-39P7Q, ACT-SF128K16N-39P3Q, ACT-SF128K16N-39F18Q, ACT-SF128K16N-37P7Q, ACT-SF128K16N-37P3Q Datasheet (ACT)

eroflex Circuit Technology - Advanced Multichip Modules © SCD1677 REV A 4/28/98

ACT–SF128K16 High Speed

128Kx16 SRAM/FLASH Multichip Module

CIRCUIT TECHNOLOGY

FEATURES

■ 2 – 128K x 8 SRAMs & 2 – 128K x 8 Flash Die in

One MCM

■ Access Times of 25ns (SRAM) and 60ns (Flash) or

35ns (SRAM) and 70 or 90ns (Flash)

■ 128K x 16 SRAM

■ 128K x 16 5V Flash

■ Organized as 128K x 16 of SRAM and 128K x 16 of

Flash Memory with Separate Data Buses

■ Both Blocks of Memory are User Configurable as

256K x 8

■ Low Power CMOS

■ Input and Output TTL Compatible Design

■ MIL-PRF-38534 Compliant MCMs Available

■ Decoupling Capacitors and Multiple Grounds for Low

Noise

■ Industrial and Military Temperature Ranges

■ Industry Standard Pinouts

Note: Programming information available upon request

www.aeroflex.com

■ Packaging – Hermetic Ceramic

● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,

Aeroflex code# "P3"

● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With

Shoulder, Aeroflex code# "P7"

● 68 Lead, .94" x .94" x .140" Single-Cavity Small

Outline Gull Wing, Aeroflex code# "F18" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)

■ DESC SMD Pending – 5962-96900

FLASH MEMORY FEATURES

■ Sector Architecture (Each Die)

● 8 Equal Sectors of 16K bytes each

● Any combination of sectors can be erased with one

command sequence.

■ +5V Programing, 5V ±10% Supply

■ Embedded Erase and Program Algorithms

■ Hardware and Software Write Protection

■ Internal Program Control Time.

■ 10,000 Erase/Program Cycles

Block Diagram – PGA Type Package (P3,P7) and CQFP (F18)

FCE2

128Kx8

Flash

OE

A0 – A16

FCE1 FWE2FWE1SWE2SWE1 SCE1 SCE2

128Kx8

SRAM

8 8 8 8

SI/O0-7 SI/O8-15 FI/O0-7 FI/O8-15

128Kx8

SRAM

128Kx8

Flash

Pin Description

FI/O

0-15 Flash Data I/O

SI/O

0-15 SRAM Data I/O

A

0–16 Address Inputs

FWE

1-2 Flash Write Enables

SWE

1-2 SRAM Write Enables

FCE

1-2 Flash Chip Enables

SCE

1-2 SRAM Chip Enables

OE
NC Not Connected

V

CC Power Supply

GND Ground

Output Enable

Absolute Maximum Ratings

Symbol Rating Range Units

-55 to +125 °C

-65 to +150 °C

-0.5 to +7 V
300 °C

T

T

STG

V

T

Case Operating Temperature

C

Storage Temperature
Maximum Signal Voltage to Ground

G

Maximum Lead Temperature (10 seconds)

L

Parameter

Flash Data Retention 10 Years
Flash Endurance (Write/Erase Cycles) 10,000

Normal Operating Conditions

Symbol Parameter Minimum Maximum Units

V

CC

V

IH

V

IL

Power Supply Voltage
Input High Voltage
Input Low Voltage

+4.5 +5.5 V
+2.2 V

+ 0.3 V

CC

-0.5 +0.8 V

Capacitance

(V

= 0V, f = 1MHz, TC = 25°C)

IN

Symbol Parameter Maximum Units

AD

C

OE

C

WE1,2

F/S C

CE1,2

F/S C

F/S C

These parameters are guaranteed by design but not tested

A0 – A16 Capacitance
OE Capacitance
F/S Write Enable Capacitance
F/S Chip Enable Capacitance

I/O

I/O0 – I/O15 Capacitance

50 pF
50 pF
20 pF
20 pF
20 pF

DC Characteristics

(VCC = 5.0V, VSS= 0V, TC= -55°C to +125°C, unless otherwise indicated)

Parameter Sym Conditions Min Max Units

I

Input Leakage Current
Output Leakage Current

SRAM Operating Supply Current x 16 Mode

I

CC

Standby Current
SRAM Output Low Voltage

SRAM Output High Voltage
Flash Vcc Active Current for Read (1)
Flash Vcc Active Current for Program or

Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Low Vcc Lock Out Voltage

Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less
than 2mA/MHz, with OE

at VIH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V

V

VCC = Max, VIN=0toV

LI

FCE = SCE = VIH, OE = V

I

LO

V

=0toV

OUT

SCE

= VIL, OE = VIH, f = 5MHz, VCC =

Max, FCE

FCE = SCE = VIH, OE = VIH, f = 5MHz,

= Max

V

CC

IOL = 8 mA, VCC = 4.5V
IOH = -4.0 mA, , VCC = 4.5V
FCE = VIL, OE = VIH, SCE = V

FCE = VIL, OE = VIH, SCE = V
IOL = 12 mA, VCC = 4.5V, SCE = V

IOH = -2.5 mA, , VCC = 4.5V, SCE = V

I

SB

V
V
I

CC1

I

CC2

V
V

LKO

x16

OL
OH

OL
OH

= V

CC

IH

CC

IH,

2.4 V

IH

IH

IH

0.85 x VCC V

IH

3.2 V

10 µA
10 µA

250 mA

40 mA

0.4 V

100 mA
130 mA

0.45 V

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2

SRAM AC Characteristics

(VCC = 5.0V, VSS= 0V, TC = -55°C to +125°C)

Read Cycle

Parameter Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Output Enable to Output Valid
Chip Select to Output in Low Z *
Output Enable to Output in Low Z *
Chip Deselect to Output in High Z *
Output Disable to Output in High Z *
* Parameters guaranteed by design but not tested

Write Cycle

Parameter Symbol

Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Output Active from End of Write *
Write to Output in High Z *
Data Hold from Write Time
Address Hold Time
* Parameters guaranteed by design but not tested

t
t

t

ACE

t
t

t

CLZ

t

OLZ

t

CHZ

t

OHZ

t

WC

t

CW

t

AW

t

DW

t

WP

t

t

OW

t

WHZ

t

DH

t

RC
AA

OH
OE

AS

AH

–025

Min Max

–035

Min Max

Units

25 35 ns

25 35 ns
25 35 ns

0 0 ns

15 20 ns
3 3 ns
0 0 ns

12 20 ns

12 20 ns

–025

Min Max

–035

Min Max

Units

25 35 ns
20 25 ns
20 25 ns
15 20 ns
20 25 ns

0 0 ns
0 0 ns

10 20 ns
0 0 ns
0 0 ns

SRAM Truth Table

Mode SCE OE SWE Data I/O Power

Standby H X X High Z Standby

Read L L H Data Out Active

Output Disable L H H High Z Active

Write L X L Data In Active

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3

Timing Diagrams — SRAM

Read Cycle Timing Diagrams

Read Cycle 1 (SCE = OE = VIL, SWE = VIH)

tRC

A0-18

tAA

tOH

DI/O

Read Cycle 2 (SWE = VIH)

tRC

A0-18

tAA

SCE

OE

DI/O

tCLZ

SEE NOTE

tOLZ

SEE NOTE

High Z

tACE

OE

t

SEE NOTE

Data Valid

Data ValidPrevious Data Valid

tCHZ

t

OHZ

SEE NOTE

Write Cycle Timing Diagrams

Write Cycle (SWE Controlled, OE = VIH)

tWC

A0-18

tAW tAH

tWHZ

tCW

tDW

Data Valid

tWC

tAW

tCW

tWP

tDW

Data Valid

SCE

tAS tWP

SWE

DI/O

Write Cycle (SCE

A0-18

tAS

SCE

SWE

DI/O

SEE NOTE

Controlled, OE = VIH )

tDW

tDH

tAH

tDH

UNDEFINED

DON’T CARE

Note: Guaranteed by design, but not tested.

AC Test Circuit

Current Source

IOL

Z ~ 1.5 V (Bipolar Supply)

To Device Under Test

C

L = 50 pF

Current Source

V

OH

I

Input and Output Timing Reference Level 1.5 V

Notes:

1) V

Z is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance

Z

O =75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance

load circuit. 6) ATE Tester includes jig capacitance.

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4

AC Test Conditions

Parameter Typical Units

Input Pulse Level 0 – 3.0 V

Input Rise and Fall 5 ns

Flash AC Characteristics – Read Only Operations

(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)

Parameter

Read Cycle Time tAVAV tRC 60 70 90 ns
Address Access Time t
Chip Enable Access Time t
Output Enable to Output Valid t
Chip Enable to Output High Z (1) t
Output Enable High to Output High Z(1) t
Output Hold from Address, CE
Note 1. Guaranteed by design, but not tested

or OE Change, Whichever is First tAXQX tOH 0 0 0 ns

Symbol

JEDEC Stand’d

AVQV tACC 60 70 90 ns
ELQV tCE 60 70 90 ns
GLQV tOE 30 35 40 ns
EHQZ tDF 20 20 25 ns
GHQZ tDF 20 20 25 ns

–60

Min Max

–70

Min Max

–90

Min Max

Units

Flash AC Characteristics – Write/Erase/Program Operations, FWE Controlled

(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)

Parameter

Write Cycle Time tAVAC tWC 60 70 90 ns
Chip Enable Setup Time t
Write Enable Pulse Width t
Address Setup Time t
Data Setup Time t
Data Hold Time t
Address Hold Time t
Chip Enable Hold Time t
Write Enable Pulse Width High t
Duration of Byte Programming Operation t
Sector Erase Time t
Chip Erase Time t
Read Recovery Time before Write t
Vcc Setup Time t
Output Enable Setup Time t
Output Enable Hold Time
Note: 1. For Toggle and Data Polling.

1

tOEH 10 10 10 ns

Symbol

JEDEC Stand’d

ELWL tCE 0 0 0 ns

WLWH tWP 30 35 45 ns

AVWL tAS 0 0 0 ns
DVWH tDS 30 30 45 ns
WHDX tDH 0 0 0 ns

WLAX tAH 45 45 45 ns
WHEH tCH 0 0 0 ns
WHWL tWPH 20 20 20 ns

WHWH1 14 TYP 14 TYP 14 TYP µs
WHWH2 60 60 60 Sec

WHWH3 120 120 120 Sec

GHWL 0 0 0 µs

VCE 50 50 50 µs
OES 12.5 12.5 12.5 Sec

–60

Min Max

–70

Min Max

–90

Min Max

Units

Flash AC Characteristics – Write/Erase/Program Operations, FCE Controlled

(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)

Parameter

Write Cycle Time tAVAC tWC 60 70 90 ns
Write Enable Setup Time t
Chip Enable Pulse Width t
Address Setup Time t
Data Setup Time t
Data Hold Time t
Address Hold Time t
Write Enable Hold from Write Enable High t
Chip Enable Pulse Width High t
Duration of Byte Programming t
Sector Erase Time t
Chip Erase Time t
Read Recovery Time
Chip Programming Time 12.5 12.5 12.5 Sec

Symbol

JEDEC Stand’d

WLEL tWS 0 0 0 ns

ELEH tCP 35 35 50 ns
AVEL tAS 0 0 0 ns
DVEH tDS 30 30 50 ns
EHDX tDH 0 0 0 ns
ELAX tAH 45 45 50 ns

EHWH tWH 0 0 0 ns

EHEL tCPH 20 20 20 ns
WHWH1 14 TYP 14 TYP 14 TYP µs
WHWH2 60 60 60 Sec
WHWH3 120 120 120 Sec

tGHEL 0 0 0 ns

–60

Min Max

–70

Min Max

–90

Min Max

Units

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5

AC Waveforms for Flash Memory Read Operations

tRC

Addresses Addresses Stable

tACC

FCE

tDF

OE

FWE

Outputs

Write/Erase/Program
Operation for Flash Memory, F

Addresses

FCE

OE

5555H PA

tWC

tAS

tGHWL

tAH

tOE

WE Controlled

Data

Polling

Output Valid

PA

tOHtCE

High ZHigh Z

tRC

tWP

FWE

Data

5.0V

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.

3. D7 is the 0utput of the complement of the data written to the deviced.

4. Dout is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

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tCE

tDS

tWPH

tDH

t

WHWH1

6

D7

tOE

tDF

DOUTPDAOH

tOH

tCE

AC Waveforms Chip/Sector
Erase Operations for Flash Memory

tAS

AH

t

Data

Polling

Addresses

FCE

OE

FWE

Data

CC

V

5555H

tGHWL

tWP

tWPH

tCE

tDH

55H AAH80H 55H 10H/30HAAH

tDS

tVCE

Notes:

1. SA is the sector address for sector erase.

5555H 5555H SA2AAAH 2AAAH

AC Waveforms for Data Polling
During Embedded Algorithm Operations for Flash Memory

FCE

OE

FWE

tCH

DQ7

DQ0-DQ6

tOEH

tOE

tDF

tCE

tOH

*

DQ

7

DQ7=

Valid Data

tWHWH1 or 2

DQ0–DQ6=Invalid

DQ0–DQ6
Valid Data

tOE

* DQ7=Valid Data (The device has completed the Embedded operation).

High Z

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Write/Erase/Program Operation for Flash Memory, FCE Controlled

Data

Polling

Addresses

FWE

OE

FCE

Data

5.0V

5555H

tWC

PA

tAHtAS

tGHWL

tWS

tCP

tCPH

t

WHWH1

tDH

tDS

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.
is the 0utput of the complement of the data written to the device.

3. D7

OUT is the output of the data written to the device.

4. D

5. Figure indicates last two bus cycles of four bus cycle sequence.

PA

D7

DOUTPDAOH

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8

Pin Numbers & Functions

All dimensions in inches

66 Pins — PGA-Type

Pin # Function Pin # Function Pin # Function Pin # Function

1 SI/O
2 SI/O9 19 Vcc 36 FI/O10 53 FCE1
3 SI/O10 20 SCE1 37 A6 54 GND
4 A
5 A14 22 SI/O3 39 NC 56 FI/O15
6 A15 23 SI/O15 40 A8 57 FI/O14
7 A16 24 SI/O14 41 A9 58 FI/O13
8 NC 25 SI/O13 42 FI/O0 59 FI/O12

9 SI/O0 26 SI/O12 43 FI/O1 60 A0
10 SI/O1 27 OE 44 FI/O2 61 A1
11 SI/O2 28 NC 45 VCC 62 A2
12 SWE2 29 SWE1 46 FCE2 63 FI/O7
13 SCE2 30 SI/O7 47 FWE2 64 FI/O6
14 GND 31 SI/O6 48 FI/O11 65 FI/O5
15 SI/O11 32 SI/O5 49 A3 66 FI/O4
16 A10 33 SI/O4 50 A4
17 A11 34 FI/O8 51 A5

8 18 A12 35 FI/O9 52 FWE1

13 21 NC 38 A7 55 FI/O3

"P3" — 1.08" SQ PGA Type (without shoulder) Package
"P7" — 1.08" SQ PGA Type (with shoulder) Package

Bottom View (P7 & P3)

1.030

1.040

Side View

(P7)

.180

TYP

.185
MAX

.025
.035

.050

.100

.020
.016

Side View

1.030

1.040

(P3)

.160
MAX

.180

TYP

.100

.020
.016

Pin 56

Pin 66

1.085 SQ
MAX

1.000
.600

.100

Pin 1

1.000

Pin 11

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9

Pin Numbers & Functions

68 Pins — Dual-Cavity CQFP

Pin # Function Pin # Function Pin # Function Pin # Function

1 GND 18 GND 35 OE
2 FCE

1 19 SI/O8 36 SCE2 53 FI/O7

3 A5 20 SI/O9 37 NC 54 FI/O6
4 A4 21 SI/O10 38 SWE2 55 FI/O5
5 A3 22 SI/O11 39 FWE1 56 FI/O4
6 A2 23 SI/O12 40 FWE2 57 FI/O3
7 A1 24 SI/O13 41 NC 58 FI/O2
8 A0 25 SI/O14 42 NC 59 FI/O1

9 NC 26 SI/O15 43 NC 60 FI/O0
10 SI/O0 27 Vcc 44 FI/O15 61 VCC
11 SI/O1 28 A11 45 FI/O14 62 A10
12 SI/O2 29 A12 46 FI/O13 63 A9
13 SI/O3 30 A13 47 FI/O12 64 A8
14 SI/O4 31 A14 48 FI/O11 65 A7
15 SI/O5 32 A15 49 FI/O10 66 A6
16 SI/O6 33 A16 50 FI/O9 67 SWE1
17 SI/O7 34 SCE1 51 FI/O8 68 FCE2

52 GND

"F18" — CQFP Package

.990 SQ
±.010

.940 SQ

Pin 9

Pin 10

Pin 26

±.010

.800 REF

Pin 61

Pin 60

Pin 44

Pin 43Pin 27

.015

±.002

.900 SQ

REF

.140

MAX

.640 SQ

REF

.008

±.002

.040

Detail “A”

Metal spacer

.010

±.008

.015

±.002

See Detail “A”

All dimensions in inches

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10

CIRCUIT TECHNOLOGY

Ordering Information

Model Number DESC SMD Number Speed Package

ACT–SF128K16N –26P3Q
ACT–SF128K16N –37P3Q
ACT–SF128K16N –39P3Q
ACT–SF128K16N –26P7Q
ACT–SF128K16N –37P7Q
ACT–SF128K16N –39P7Q
ACT–SF128K16N –26F18Q
ACT–SF128K16N –37F18Q
ACT–SF128K16N –39F18Q

Note: (S) = Speed for SRAM, (F) = Speed for FLASH
* Pending

ACT– S F 128K 16 N– 26 P7 Q

Aeroflex Circuit
Technology

Memory Type

S (SRAM) & F (FLASH) Combo

Memory Depth
Options, N = none

Memory Width, Bits
Memory Speed cODE

26 = 25ns SRAM & 60ns FLASH
37 = 35ns SRAM & 70ns FLASH
39 = 35ns SRAM & 90ns FLASH

5462-96900* 25(S) / 60(F) ns 1.08"SQ PGA-Type
5462-96900* 35(S) / 70(F) ns 1.08"SQ PGA-Type
5462-96900* 35(S) / 90(F) ns 1.08"SQ PGA-Type
5462-96900* 25(S) / 60(F) ns 1.08"SQ PGA-Type
5462-96900* 35(S) / 70(F) ns 1.08"SQ PGA-Type
5462-96900* 35(S) / 90(F) ns 1.08"SQ PGA-Type
5462-96900* 25(S) / 60(F) ns .94"sq CQFP
5462-96900* 35(S) / 70(F) ns .94"sq CQFP
5462-96900* 35(S) / 90(F) ns .94"sq CQFP

Part Number Breakdown

C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screening
Q = MIL-PRF-38534 Compliant / SMD

Surface Mount Packages Thru-Hole Packages

F18 = .94"SQ 68 Lead Dual-Cavity
CQFP

Screening

Package Type & Size

P3 = 1.085"SQ PGA 66 Pins

with out shoulder

P7 = 1.085"SQ PGA 66 Pins

with shoulder

* Screened to the individual test methods of MIL-STD-883

*

Specification subject to change without notice

Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830

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Telephone: [phone]

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