Datasheet ACTS541T Datasheet (Intersil Corporation)

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ACTS541T
Data Sheet July 1999 File Number
Radiation Hardened Octal Three-State Buffer/Line Driver
Intersil’sSatellite Applications FlowTM(SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability.
The Intersil ACTS541T is a Radiation Hardened Octal Buffer/Line Driver, with three-state outputs. The output enable pins
OE1, OE2 control the three-state outputs. If either enable is high the output will be in a high impedance state. For data output both enables must be low.
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACTS541T are contained in SMD 5962-96726. A “hot-link” is provided from our website for downloading.
www.intersil.com/spacedefense/newsafc lasst.asp
Intersil’s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website.
www.semi.intersil.com/quality/manuals.asp
Ordering Information
TEMP.
ORDERING
NUMBER
5962R9672602TRC ACTS541DTR-02 -55 to 125
PART
NUMBER
RANGE
(oC)
4612.1
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
5
- Gamma Dose (γ) 1 x 10
RAD(Si)
- Latch-Up Free Under Any Conditions
- Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day (Typ)
- SEU LET Threshold . . . . . . . . . . . . .>100 MEV-cm
2
/mg
• 1.25 Micron Radiation Hardened SOS CMOS
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range. . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
-VIL = 0.8V Max
-V
= VCC/2 Min
IH
• Fast Propagation Delay . . . . . . . . 21ns (Max), 14ns (Typ)
Pinouts
ACTS541T (SBDIP), CDIP2-T20
TOP VIEW
OE1
A0 A1 A2 A3 A4 A5 A6 A7
GND
1 2 3 4 5 6 7 8 9
10
V
20
CC
OE2
19
Y0
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
13 12
Y6
11
Y7
5962R9672602TXC ACTS541KTR-02 -55 to 125
NOTE:
Minimumorderquantity for -T is 150 units through
distribution, or 450 units direct
.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
ACTS541T (FLATPACK), CDFP4-F20
TOP VIEW
OE1
A0 A1 A2 A3 A4 A5 A6 A7
GND
www.intersil.com or 407-727-9207
120 2 3 4 5 6 7 8 9 10
V
CC
19 18 17 16 15 14 13 12 11
OE2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
| Copyright © Intersil Corporation 1999
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Functional Diagram
19
OE2
OE1
ACTS541T
V
2
A0
1
3
A1
4
A2
5
A3
6
A4
7
A5
CC
GND V
CC
GND V
CC
GND V
CC
GND V
CC
GND V
CC
18
Y0
17
Y1
16
Y2
15
Y3
14
Y4
13
Y5
8
A6
GND
V
CC
10
20
A7
9
TRUTH TABLE
INPUTS OUTPUTS
OE1 OE2 An Yn
LLHH
LLLL HXXZ XHXZ
NOTE: L = Low Logic Level, H = High Logic Level, Z = High Impedance.
GND V
CC
GND V
CC
GND
12
Y6
11
Y7
2
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Die Characteristics
ACTS541T
DIE DIMENSIONS:
(2600µm x 2600µm x 533µm ±51µm) 102 x 102 x 21mils ±2mil
METALLIZATION:
Type: Al Si Cu Thickness: 10.0k
Å ±2kÅ
SUBSTRATE POTENTIAL:
Unbiased (Silicon on Sapphire) Bond Pad #20 (V
CC
) First
BACKSIDE FINISH:
Sapphire
Metallization Mask Layout
(3) A1
(2) A0
ACTS541T
(1) OE1
PASSIVATION:
Type: Silox (S Thickness: 8.0k
)
iO2
Å ±1.0kÅ
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
182
PROCESS:
CMOS SOS
CC
OE2
(20) V
(19)
(18) YO
A2 (4)
A3 (5)
NC
NC
A4 (6)
A5 (7)
A6 (8)
A7 (9)
GND (10)
Y7 (11)
Y6 (12)
Y5 (13)
(17) Y1
(16) Y2
NC
NC
(15) Y3
(14) Y4
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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