Datasheet ACT-5270PC-200F17T, ACT-5270PC-200F17M, ACT-5270PC-150F17I, ACT-5270PC Datasheet (ACT)

ACT5270

64-Bit Superscaler Microprocessor

Features

Full militarized QED RM5270 microprocessor

■

Dual Issue superscalar microprocessor - can issue one

■

integer and one floating-point instruction per cyc le

133, 150, 200 MHz operating frequencies – Consult Factory for

●

lates t speeds

260 Dhrystone2.1 MIPS

●

SPECInt95 5.0, SPECfp95 5.3

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High performance system interfa ce com patible with RM5260,

■

R4600, R4700 and R5000

64-bit multiplexed system address/data bus for optimum price/

●

performance with up to 100 MHz operating frequency

High performance write protocols maximize uncached write

●

bandwidth

Supports clock divisors (2, 3, 4, 5, 6, 7, 8)

●

5V compatible I/O’s

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IEEE 1149.1 JTA G boundary scan

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Integrated on-c hip caches

■

16KB instruction - 2 way set associative

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16KB data - 2 way set associative

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Virtually indexed, physically tagged

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Write-back and write-through on per page basis

●

Pipeline restart on first double for data cache misses

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Integrated memory management unit

■

Fully associative joint TLB (shared by I and D translations)

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48 dual entries map 96 pa ges

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Variable page size (4KB to 16MB in 4x increments)

●

Integrated secondary cache controll er (R5000 compatible)

■

Supports 512K or 2MByte block write-through secondary

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High-performance floating point unit

■

Single cycle repeat rate for common single precision operations

●

and some double precision operations

Two cycle repeat rate for double precision multiply and double

●

precision combined multiply-add operations

Single cycle repeat rate for single precision combined multiply-

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add operation

MIPS IV instructi on set

■

Floating point multiply-add instruction increases performance in

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signal processing and graphics applications

Conditional moves to reduce branch frequency

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Index address modes (register + register)

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Embedded application enhancements

■

Specialized DSP integer Multiply-Accumulate instruction and 3

●

operand multiply instruction

I and D cache locking by set

●

Optional dedicated exception vector for interrupts

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Fully static CMOS design with power down logic

■

Standby reduced power mode with WAIT instruction

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6 Watts typical at 3.3V 200 MHz

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208-lead CQFP, cavity-up package (F17)

■

208-lead CQFP, inverted footprint (F24), Intended to duplicate

■

the commercial QED footprint
179-pin PGA package (

■

Future Product

) (P10)

BLOCK DIAGRAM

Preliminary

eroflex Circuit

Technology

– RISC TurboEngines For The Future © SCD5270 REV 1 12/22/98

DESCRIPTION

The AC T5270 is a hig hly inte grated supers calar
micropro cessor that imp lements a sup erset of the
MIPS IV I nstruc tion Se t Archit ecture(I SA). It has a
high performance 64-bit integer unit, a high
throughpu t, ful ly pip elin ed 64 -bit f loat ing po int un it,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 16
KByte 2-way set associative instruction cache, a 16
KByte 2-way set associative data cache, and a
high-performance 64-bit system interface with
support for an optional ex ternal second ary cache.
The ACT5270 can issue both an integer and a
floating p oint instruction in the same c y cl e.

The ACT5270 is ideally suited for high-end
emb edded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.The ACT5270 is also applicable to the
low end workstation market where its balanced
integer and floating-point performance and direct
support for a large secondary cache (up to 2MB)
provide outstanding price/performance

HARDWARE OVERVIEW

The ACT5270 offers a high-level of integration
targeted at high-performance embedded
applications. The key elements of the ACT5270 are
briefly desc ribed below.

Superscalar Dispatch

The ACT5270 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer ins t ruction an d a floating- point comput at ion
instruction simultaneously. With respect to
superscal ar issue, i nteger ins tructions in clude alu ,
branch, load/store, and floating-point load/ store,
while floating-point computation instructions
include floating-point add, subtract, combined
multiply-a dd, conver ts, etc. In c ombinatio n with its
high throughput fully pipelined floating-point
execution unit, the superscalar capability of the
ACT527 0 pro vide s un pa rallele d p rice /perfo rman ce
in computationally intensive embedded
applications.

CPU Registers

Like all MIPS ISA processors, the ACT5270 CPU
has a simple, clean user visible state consisting of
32 gene ral purpo se regi sters, two sp ecial pu rpose
registers for integer multiplication and division, a
program counter, and no condition code bits.

Pipeline

For integ er operations, loa ds, stores, and oth er
non-floating-point operations, the ACT5270 uses
the simple 5-stage pipeline also found in the
ACT52xx family, R4600, R4700, and R5000. In
addition to this standard pipeline, the ACT5270
uses an extended seven stage pipeline for

floating-point operations. Like the R5000, the
ACT5270 does virtual to physical translation in
parallel with cache access.

Integer Unit

As part of the ACT52xx family, the ACT5270
implements the MIPS IV Instruction Set
Architecture, and is therefore fully upward
compatible with applications that run on processors
implementing the earlier generation MIPS I-III
instruction sets. Addi tionally, the ACT5270 inc ludes
two im plementa tion spec ific instru ctions no t found
in the base line MIPS IV ISA but that are useful in
the em bedde d m arke t pla ce. Desc ribed in deta il in
the QED RM5270 datasheet, these instructions are
integer m ultiply-a ccumul ate and 3-o peran d intege r
multipl y.

The ACT5270 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/
divide unit. Additional register resources include:
the HI/LO result registers for the two-operand
integer m ultiply/divid e operations , a nd t he program
counte r(PC).

Register File

The ACT5270 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registers are used for scalar integer
operations and address calculation. The register
file has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.

ALU

The ACT5270 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations.
Each of these units is optimized to perform all
operations in a single processor cycle.

For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark ACT5270, 64-Bit Superscalar
Microprocessor see the latest QED datasheet
(Revision 1.1 July 1998).

Aeroflex Circuit Technology SCD5270 REV 1 12/22/98 Plainview NY [phone]

2

Package Information – "F17" – CQFP 208 Leads

1.131 (28.727) SQ

1.109 (28.169) SQ

10453

52

105

.0236 ( .51)

1.009 (25.63)
.9998 (25.37)

51 Spaces at .0197

(51 Spaces at .50)

Pin 1 Chamfer

Detail "A"

.005 (.127)

.008 (.258)

.010R MIN

.010R MIN

.0158 ( .49)

0°±5°

.100 (2.540)
.080 (2.032)

.015 (.381)
.009 (.229)

.130 (3.302)

MAX

.009 (.253)
.007 (.178)

.035 (.889)
.025 (.635)

Detail "A"

1

208

.960 (24.384) SQ

REF

1.331 (33.807)

1.269 (32.233)

Note: Pin rot ation is opposite of QEDs PQUAD due to cavity-up construction.

156

157

.055 (1.397)

REF

.055 (1.397)
.045 (1.143)

.115 (2.921)

MAX

Units: Inches (Millimeters)

Future Package – "P10" – PGA 179 Pins

(Advanced)

Bottom View Side View

123456789101112131415161718

V
U
T
R
P
N
M
L

1.840

K
J
H
G
F
E
D
C
B
A

1.700
BSC

1.880

1.700
BSC

1.840

1.880

Aeroflex Circuit Technology SCD5270 REV 1 12/22/98 Plainview NY [phone]

3

.100
BSC

.018

.050

.221
MAX

ACT5270 Microprocessor CQFP Pinouts – "F17"

Pin # Function Pin # Function Pin # Function Pin # Fu nct i on

1 Vcc (3.3V) 53 NC 105 Vcc (3.3V) 157 NC
2 NC 54 NC 106 NMI* 158 NC
3 NC 55 NC 107 ExtRqst* 159 NC
4 Vcc (3.3V) 56 Vcc (3.3V) 108 Reset* 160 NC
5 Vss 57 Vss 109 ColdReset* 161 Vcc (3.3V)
6 SysAD4 58 ModeIn 110 VccOK 162 Vss
7 SysAD36 59 RdRdy* 111 BigEndian 163 SysAD28
8 SysAD5 60 WrRdy* 112 Vcc (3.3V) 164 SysAD60

9 SysAD37 61 V alidIn* 113 Vss 165 SysAD29
10 Vcc (3.3V) 62 ValidOut* 114 SysAD16 166 SysAD61
11 Vss 63 Release* 115 SysAD48 167 Vcc (3.3V)
12 SysAD6 64 VccP 116 Vcc (3.3V) 168 Vss
13 SysAD38 65 VssP 117 Vss 169 SysAD30
14 Vcc (3.3V) 66 SysClock 118 SysAD17 170 SysAD62
15 Vss 67 Vcc (3.3V) 119 SysAD49 171 Vcc (3.3V)
16 SysAD7 68 Vss 120 SysAD18 172 Vss
17 SysAD39 69 Vcc (3.3V) 121 SysAD50 173 SysAD31
18 SysAD8 70 Vss 122 Vcc (3.3V) 174 SysAD63
19 SysAD40 71 Vcc (3.3V) 123 Vss 175 SysADC2
20 Vcc (3.3V) 72 Vss 124 SysAD19 176 SysADC6
21 Vss 73 SysCmd0 125 SysAD51 177 Vcc (3.3V)
22 SysAD9 74 SysCmd1 126 Vcc (3.3V) 178 Vss
23 SysAD41 75 SysCmd2 127 Vss 179 SysADC3
24 Vcc (3.3V) 76 SysCmd3 128 SysAD20 1 8 0 SysADC7
25 Vss 77 Vcc (3.3V) 129 SysAD52 181 Vcc (3.3V)
26 SysAD10 78 Vss 130 SysAD21 182 Vss
27 SysAD42 79 SysCmd4 131 SysAD53 183 SysADC0
28 SysAD11 80 SysCmd5 132 Vcc (3.3V) 184 SysADC4
29 SysAD43 81 Vcc (3.3V) 133 Vss 185 Vcc (3.3V)
30 Vcc (3.3V) 82 Vss 134 SysAD22 186 Vss
31 Vss 83 SysCmd6 135 SysAD54 187 SysADC1
32 SysAD12 84 SysCmd7 136 Vcc (3.3V) 188 SysADC5
33 SysAD44 85 SysCmd8 137 Vss 189 SysAD0
34 Vcc (3.3V) 86 SysCmdP 138 SysAD23 1 9 0 SysAD32
35 Vss 87 Vcc (3.3V) 139 SysAD55 191 Vcc (3.3V)
36 SysAD13 88 Vss 140 SysAD24 192 Vss
37 SysAD45 89 Vcc (3.3V) 141 SysAD56 193 SysAD1
38 SysAD14 90 Vss 142 Vcc (3.3V) 194 SysAD33
39 SysAD46 91 Vcc (3.3V) 143 Vss 195 Vcc (3.3V)
40 Vcc (3.3V) 92 Vss 144 SysAD25 196 Vss
41 Vss 93 Int0* 145 SysAD57 197 SysAD2
42 SysAD15 94 Int1* 146 Vcc (3.3V) 198 SysAD34
43 SysAD47 95 Int2* 147 Vss 199 SysAD3
44 Vcc (3.3V) 96 Int3* 148 SysAD26 200 SysAD35
45 Vss 97 Int4* 149 SysAD58 201 Vcc (3.3V)
46 ModeClock 98 Int5* 150 SysAD27 202 Vss
47 JTDO 99 Vcc (3.3V) 151 SysAD59 2 0 3 NC
48 JTDI 100 Vss 152 Vcc (3.3V) 204 NC
49 JTCK 101 NC 153 Vss 205 NC
50 JTMS 102 NC 154 NC 206 NC
51 Vcc (3.3V) 103 NC 155 NC 207 Vcc (3.3V)
52 Vss 104 NC 156 Vss 208 Vss

Aeroflex Circuit Technology SCD5270 REV 1 12/22/98 Plainview NY [phone]

4

CIRCUIT TECHNOLOGY

Sample Ordering Informa tion

Part Number Screening Speed (MHz) Package

ACT-5270PC-133F17C Commercial Temperature 133 208 Lead CQFP
ACT-5270PC-150F17I Industrial Temperature 150 208 Lead CQFP
ACT-5270PC-200F17T Military Temperature 200 208 Lead CQFP
ACT-5270PC-200F17M Military Screened 200 208 Lead CQFP

Part Number Brea kd own

ACT– 5270 PC – 200 F17 M

Aeroflex Circuit
Technology

Base Processor Type

Cache Style

PC = Primary Cache

Maximum Pipeline Freq.

133 = 133MHz
150 = 150MHz
200 = 200MHz

Specificatio ns subject to chang e without notice.

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35 South Service Road
Plainview New York 11803

C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screened
Q = MIL-PRF-38534 Compliant/SMD if applicable

F17 = 1.12 0" SQ 208 Lead CQFP
F24 = 1. 120" SQ Inverted 20 8 Lead CQFP

P10 = 1.86"SQ PGA 179 pins with shoulder (Advanced)

Screened to the individual test methods of MIL-STD-883

*

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Toll Free Inquiries: [phone]

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5

Screening

*

Package Type & Size

Surface Mount Package

Thru-Hole Packa ge