The AC T5270 is a hig hly inte grated supers calar
micropro cessor that imp lements a sup erset of the
MIPS IV I nstruc tion Se t Archit ecture(I SA). It has a
high performance 64-bit integer unit, a high
throughpu t, ful ly pip elin ed 64 -bit f loat ing po int un it,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 16
KByte 2-way set associative instruction cache, a 16
KByte 2-way set associative data cache, and a
high-performance 64-bit system interface with
support for an optional ex ternal second ary cache.
The ACT5270 can issue both an integer and a
floating p oint instruction in the same c y cl e.
The ACT5270 is ideally suited for high-end
emb edded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.The ACT5270 is also applicable to the
low end workstation market where its balanced
integer and floating-point performance and direct
support for a large secondary cache (up to 2MB)
provide outstanding price/performance
HARDWARE OVERVIEW
The ACT5270 offers a high-level of integration
targeted at high-performance embedded
applications. The key elements of the ACT5270 are
briefly desc ribed below.
Superscalar Dispatch
The ACT5270 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer ins t ruction an d a floating- point comput at ion
instruction simultaneously. With respect to
superscal ar issue, i nteger ins tructions in clude alu ,
branch, load/store, and floating-point load/ store,
while floating-point computation instructions
include floating-point add, subtract, combined
multiply-a dd, conver ts, etc. In c ombinatio n with its
high throughput fully pipelined floating-point
execution unit, the superscalar capability of the
ACT527 0 pro vide s un pa rallele d p rice /perfo rman ce
in computationally intensive embedded
applications.
CPU Registers
Like all MIPS ISA processors, the ACT5270 CPU
has a simple, clean user visible state consisting of
32 gene ral purpo se regi sters, two sp ecial pu rpose
registers for integer multiplication and division, a
program counter, and no condition code bits.
Pipeline
For integ er operations, loa ds, stores, and oth er
non-floating-point operations, the ACT5270 uses
the simple 5-stage pipeline also found in the
ACT52xx family, R4600, R4700, and R5000. In
addition to this standard pipeline, the ACT5270
uses an extended seven stage pipeline for
floating-point operations. Like the R5000, the
ACT5270 does virtual to physical translation in
parallel with cache access.
Integer Unit
As part of the ACT52xx family, the ACT5270
implements the MIPS IV Instruction Set
Architecture, and is therefore fully upward
compatible with applications that run on processors
implementing the earlier generation MIPS I-III
instruction sets. Addi tionally, the ACT5270 inc ludes
two im plementa tion spec ific instru ctions no t found
in the base line MIPS IV ISA but that are useful in
the em bedde d m arke t pla ce. Desc ribed in deta il in
the QED RM5270 datasheet, these instructions are
integer m ultiply-a ccumul ate and 3-o peran d intege r
multipl y.
The ACT5270 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/
divide unit. Additional register resources include:
the HI/LO result registers for the two-operand
integer m ultiply/divid e operations , a nd t he program
counte r(PC).
Register File
The ACT5270 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registers are used for scalar integer
operations and address calculation. The register
file has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.
ALU
The ACT5270 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations.
Each of these units is optimized to perform all
operations in a single processor cycle.
For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark ACT5270, 64-Bit Superscalar
Microprocessor see the latest QED datasheet
(Revision 1.1 July 1998).
Aeroflex Circuit TechnologySCD5270 REV 1 12/22/98 Plainview NY (516) 694-6700
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Page 3
Package Information – "F17" – CQFP 208 Leads
1.131 (28.727) SQ
1.109 (28.169) SQ
10453
52
105
.0236 ( .51)
1.009 (25.63)
.9998 (25.37)
51 Spaces at .0197
(51 Spaces at .50)
Pin 1 Chamfer
Detail "A"
.005 (.127)
.008 (.258)
.010R MIN
.010R MIN
.0158 ( .49)
0°±5°
.100 (2.540)
.080 (2.032)
.015 (.381)
.009 (.229)
.130 (3.302)
MAX
.009 (.253)
.007 (.178)
.035 (.889)
.025 (.635)
Detail "A"
1
208
.960 (24.384) SQ
REF
1.331 (33.807)
1.269 (32.233)
Note: Pin rot ation is opposite of QEDs PQUAD due to cavity-up construction.
156
157
.055 (1.397)
REF
.055 (1.397)
.045 (1.143)
.115 (2.921)
MAX
Units: Inches (Millimeters)
Future Package – "P10" – PGA 179 Pins
(Advanced)
Bottom ViewSide View
123456789101112131415161718
V
U
T
R
P
N
M
L
1.840
K
J
H
G
F
E
D
C
B
A
1.700
BSC
1.880
1.700
BSC
1.840
1.880
Aeroflex Circuit TechnologySCD5270 REV 1 12/22/98 Plainview NY (516) 694-6700
3
.100
BSC
.018
.050
.221
MAX
Page 4
ACT5270 Microprocessor CQFP Pinouts – "F17"
Pin #FunctionPin #FunctionPin # FunctionPin # Fu nct i on
Aeroflex Circuit TechnologySCD5270 REV 1 12/22/98 Plainview NY (516) 694-6700
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CIRCUIT TECHNOLOGY
Sample Ordering Informa tion
Part NumberScreeningSpeed (MHz)Package
ACT-5270PC-133F17C Commercial Temperature133 208 Lead CQFP
ACT-5270PC-150F17IIndustrial Temperature150 208 Lead CQFP
ACT-5270PC-200F17TMilitary Temperature200 208 Lead CQFP
ACT-5270PC-200F17MMilitary Screened200 208 Lead CQFP
Part Number Brea kd own
ACT– 5270 PC –200 F17 M
Aeroflex Circuit
Technology
Base Processor Type
Cache Style
PC = Primary Cache
Maximum Pipeline Freq.
133 = 133MHz
150 = 150MHz
200 = 200MHz
Specificatio ns subject to chang e without notice.
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11803
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screened
Q = MIL-PRF-38534 Compliant/SMD if applicable
F17 = 1.12 0" SQ 208 Lead CQFP
F24 = 1. 120" SQ Inverted 20 8 Lead CQFP
P10 = 1.86"SQ PGA 179 pins with shoulder (Advanced)
Screened to the individual test methods of MIL-STD-883