Datasheet ACT-5231PC-200F22M, ACT-5231PC-150F22T, ACT-5231PC Datasheet (ACT)

ACT5231

32-Bit Superscaler Micropr ocessor

Features

Full militarized QED RM5231 microprocessor

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Pinout compatibl e wit h popular RM5230 with split power sup

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plies (2.5V and 3.3V)
Dual Issue superscalar microprocessor - can issue one

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integer and one floating-point instruction per cyc le

133, 150 and 200 MHz operating frequencies – Consult Factory for

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lates t speeds

325 Dhrystone2.1 MIPS

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SPECInt95 5.0, SPECfp95 5.25

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System interface optimized for embedded applications

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32-bit system interface lowers total system cost

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High performance write protocols maximize uncached write

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bandwidth with 600 MB per second peak throughput

Operates at processor clock divisors 2, 2.5, 3, 3.5,4, 4.5, 5, 6, 7, 8, 9

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IEEE 1149.1 JTA G boundary scan

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Integrated on-c hip caches

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32KB instruction and 32KB data - 2 way set associative and per

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set locking

Virtually indexed, physically tagged

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Write-back and write-through on per page basis

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Pipeline restart on first double for data cache misses

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Integrated memory management unit

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Fully associative joint TLB (shared by I and D translations)

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48 dual entries map 96 pa ges

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Variable page size (4KB to 16MB in 4x increments)

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High-performance floating point unit

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532 MFLOPS single-precision performance

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Single cycle repeat rate for common single precision opera-tions

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and some double precision operations

Two cycle repeat rate for double precision multiply and double

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precision combined multiply-add operations

Single cycle repeat rate for single precision combined multiply-

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add operation

MIPS IV instructi on set

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Floating point multiply-add instruction increases performance in

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signal processing and graphics applications

Conditional moves to reduce branch frequency

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Index address modes (register + register)

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Embedded application enhancements

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Specialized DSP integer Multiply-Accumulate instruction and 3

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operand multiply instruction

I and D cache locking by set

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Optional dedicated exception vector for interrupts

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Fully static CMOS design with power down logic

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Standby reduced power mode with WAIT instruction

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2.7 W typical power @ 200MHz

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2.5V core with 3.3V IO’s

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128-pin Power Quad-4 package (F22),

Consult Fac tory for

package conf iguration

Block Diagram

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Technology

Preliminary

– RISC TurboEngines For The Future © SCD5231 REV 1 12/22/98

DESCRIPTION

Integer Unit

The AC T5231 is a hig hly inte grated supers calar
micropro cessor that imp lements a sup erset of the
MIPS IV I nstruc tion Se t Archit ecture(I SA). It has a
high performance 64-bit integer unit, a high
throughpu t, ful ly pip elin ed 64 -bit f loat ing po int un it,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 32KB
2-way set associative instruction cache, a 32KB
2-way set a ssociative da ta cache, and a n efficient
32-bit system interface. The ACT5231 can issue
both an integer and a floating point instruction in the
same cycle.

The ACT5231 is ideally suited for high-end
embedded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.

HARDWARE OVERVIEW

The ACT5231 offers a high-level of integration
targeted at high-performance embedded
applications. The key elements of the ACT5231 are
briefly desc ribed below .

Superscalar Dispatch

The ACT5231 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer ins t ruction and a floa tin g-point com putatio n
instruction simultaneously. With respect to
superscal ar issue, i nteger ins tructions in clude alu ,
branch, load/store, and floating-point load/ store,
while floating-point computation instructions
include floating-point add, subtract, combined
multiply-a dd, conver ts, etc. In c ombinatio n with its
high throughput fully pipelined floating-point
execution unit, the superscalar capability of the
ACT523 1 pro vide s un pa rallele d p rice /perfo rman ce
in computationally intensive embedded
applications.

The ACT5231 implements the MIPS IV
Instruction Set Architecture, and is ther efore fully
upward compatible with applications that run on
processors implementing the earlier generation
MIPS I-III instruction sets. Additionally, the
ACT5231 includes two implementation specific
instruct ions no t found in t he base line MIPS IV ISA
but tha t are u seful in t he em bedded marke t place.
Described in det ail in the QE D R M 5231 dat as heet,
these instructions are integer multipl y-accumulate
and 3-operand integer multiply.

The ACT5231 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/
divide unit. Additional register resources include:
the HI/LO result registers for the two-operand
integer m ultiply/divide operat ions, and the program
counte r(PC).

Register File

The ACT5231 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registersi ch allo are used for s calar in teger
operations and address calculation. The register
file has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.

ALU

The ACT5231 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations.
Each of these units is optimized to perf orm all ti o ns
in a single processo r c y cl e.

CPU Registers

Like all MIPS ISA processors, the ACT5231 CPU
has a simple, clean user visible state consisting of
32 gene ral purpo se regi sters, two sp ecial pu rpose
registers for integer multiplication and division, a
program c ounter, and no condition code bits .

For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark RM 5231, 32-Bit Superscalar
Microp roc essor see th e lat est QED da ta s heet.

Pipeline

For integ er operations, loa ds, stores, and oth er
non-floating-point operations, the ACT5231 uses
the simple 5-stage pipeline also found in the
ACT52xx family, R4600, R4700, and R5000. In
addition to this standard pipeline, the ACT5231
uses an extended seven stage pipeline for
floating-point operations. The ACT5231 does
virtual to ph ysical t ranslatio n in par allel with c ache
access.

Aeroflex Circuit Technology SCD5231 REV 1 12/22/98 Plainview NY [phone]

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ACT5231 Microprocessor PQUAD Pinouts

(Pinouts subject to change – Contact Factory)

Pin # Function Pin # Function Pin # Function Pin # Fu nct i on

1 Vcc 53 NC 105 Vcc 157 NC
2 NC 54 NC 106 NMI* 158 NC
3 NC 55 NC 107 ExtRqst* 159 NC
4 Vcc 56 Vcc 108 Reset* 160 NC
5 Vss 57 Vss 109 ColdReset* 161 Vcc
6 SysAD4 58 ModeIn 110 VccOK 162 Vss
7 SysAD36 59 RdRdy* 111 BigEndian 163 SysAD28
8 SysAD5 60 WrRdy * 112 Vcc 164 S ysAD60

9 SysAD37 61 ValidIn* 113 Vss 165 SysAD29
10 Vcc† 62 ValidOut* 114 SysAD16 166 SysAD61
11 Vss 63 Rel ease* 115 SysAD48 167 Vcc†
12 SysAD6 64 VccP 116 Vcc† 168 Vss
13 SysAD38 65 VssP 117 Vss 169 SysAD30
14 Vcc 66 SysClock 118 SysAD17 170 SysAD62
15 Vss 67 V cc† 119 SysAD49 171 Vcc
16 SysAD7 68 V ss 120 SysAD18 172 Vss
17 SysAD39 69 Vcc 121 SysAD50 173 SysAD31

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18 SysAD8 70 V ss 122 Vcc 174 SysAD63
19 SysAD40 71 Vcc† 123 Vss 175 SysADC2
20 Vcc† 72 Vss 124 SysAD19 176 SysADC6
21 Vss 73 SysCmd0 125 SysAD51 177 Vcc†
22 SysAD9 74 SysCmd1 126 Vcc† 178 Vss

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23 SysAD41 75 SysCmd2 127 Vss 179 SysADC3
24 Vcc 76 SysCmd3 128 SysAD20 180 SysADC7

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25 Vss 77 Vcc 129 SysAD52 181 Vcc
26 SysAD10 78 Vss 130 SysAD21 182 Vss
27 SysAD42 79 SysCmd4 131 SysAD53 183 SysADC0
28 SysAD11 80 SysCmd5 132 Vcc 184 SysADC4
29 SysAD43 81 Vcc 133 Vss 185 Vcc†
30 Vcc† 82 Vss 134 SysAD22 186 Vss
31 Vss 83 SysCmd6 135 SysAD54 187 SysADC1
32 SysAD12 84 SysCmd7 136 Vcc† 188 SysADC5
33 SysAD44 85 SysCmd8 137 Vss 189 SysAD0
34 Vcc 86 S ysC mdP 138 SysAD23 190 SysAD32
35 Vss 87 V cc† 139 SysAD55 191 Vcc
36 SysAD13 88 Vss 140 SysAD24 192 Vss
37 SysAD45 89 Vcc† 141 SysAD56 193 SysAD1
38 SysAD14 90 Vss 142 Vcc 194 SysAD33
39 SysAD46 91 Vcc 143 Vss 195 Vcc†
40 Vcc† 92 Vss 144 SysAD25 196 Vss
41 Vss 93 Int0* 145 SysAD57 197 SysAD2
42 SysAD15 94 Int1* 146 V cc† 198 SysAD34
43 SysAD47 95 Int2* 147 V ss 199 SysAD3
44 Vcc 96 Int3* 148 SysAD26 200 SysAD35
45 Vss 97 Int4* 149 SysAD58 201 Vcc
46 ModeClock 98 Int5* 150 SysAD27 202 Vss
47 JTDO 99 Vcc 151 SysAD59 203 NC
48 JTDI 100 Vss 152 Vcc 204 NC
49 J TCK 101 NC 153 Vss 205 NC
50 JTMS 102 NC 154 NC 206 NC
51 Vcc 103 NC 155 NC 207 Vcc
52 Vss 104 NC 156 Vss 208 Vss

† These VCC pins may be 2.5V in future higher performanc e device s

Aeroflex Circuit Technology SCD5231 REV 1 12/22/98 Plainview NY [phone]

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CIRCUIT TECHNOLOGY

Sample Ordering Informati on

Part Number Screening Speed (MHz) Package

ACT-5231PC-133F22C Co mm ercial Temperature 133 128 Lead PQUAD
ACT-5231PC-150F22T Military Temperature 150 128 Lead PQUAD
ACT-5231PC-200F22M Military Screening 200 128 Lead PQUAD

Part Number Brea kd own

ACT– 5231 PC – 200 F22 M

Aeroflex Circuit
Technology

Base Processor Type

Cache Style

PC = Primary Cache

Maximum Pipeline Freq.

133 = 150MHz
150 = 150MHz
200 = 200MHz

Specificatio ns subject to chang e without notice.

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Plainview New York 11803

C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screened
Q = MIL-PRF-38534 Compliant/SMD if applicable

F22 = 1. 10" SQ 128 Lead PQUAD

Screened to the individual test methods of MIL-STD-883

*

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Toll Free Inquiries: [phone]

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Screening

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Package Type & Size

Surface Mount Package