Datasheet ACT-5230PC-200F22T, ACT-5230PC-200F22M, ACT-5230PC-150F22C, ACT-5230PC Datasheet (ACT)
Page 1
ACT5230
32-Bit Superscaler Micropr ocessor
Features
■
Full militarized QED RM5230 microprocessor
■
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
100, 133 and 150 MHz operating frequency – Consult
●
Factory for latest speeds
228 Dhrystone2.1 MIPS
●
SPECInt95 4.2 SPECfp95 4.5
●
■
System interface optomized for embedded
applications
32-bit system interface lower s total system cost wit h up to
●
87.5 MHz operating frequency
High performance write protocols maximize uncached
●
write bandwidth
Operates at processor clock divisors 2 through 8
●
5V tolerant I/O's
●
IEEE 1149.1 JTAG boundary scan
●
■
Integrated on-chip caches
16KB instruction - 2 way set associative
●
16KB data - 2 way set associative
●
Virtually indexed, physically tagged
●
Write-back and wri te-through on per page basis
●
Early restart on dat a cache misses
●
■
Integrated memory management unit
Fully associative joint TLB (shared by I and D translati ons)
●
48 dual entries map 96 pages
●
Va riable page size (4KB to 16MB in 4x increments)
●
■
High-performance floating point unit
Single cycle repeat rate for common si ngle precision
●
operations and some double precision operations
Two cycle repeat rate for double precision multiply and
●
double precision combined multiply-add operations
Single cycle repeat rate for single precision combined
●
multiply-add operation
■
MIPS IV instruction set
Floating point multiply-add instruction increases
●
performa nce in si gnal processing and graphics
applications
Conditional moves to reduce branch frequen cy
●
Index address modes (register + regist er)
●
■
Embedded application enhancements
Specialized DSP int eger Mu ltiply-Accumul ate instruction
●
and 3 operand multiply instruction
I and D cache lockin g by set
●
Optional dedicated exception vector for interrupts
●
■
Fully static CMOS design with power down logic
Standby reduced pow er mode with WAIT instruction
●
2.5 Wat ts typical with less than 70 mA standby current
●
■
128-pin Power Quad-4 package (F22),
Consult Fac tory for
package conf iguration
Block Diagram
Data Set A
Store B u ffer
Write Bu ffe r
Read Buffer
Data Set B
Control
Floating-point
Register File
Unpacker/Packer
Floati ng-point
MAdd, Add, Sub,Cvt
Div, SqRt
DBus
Sys AD
FPIBus
Floating point Control
Phase Lock Loop
Data Tag A
DTLB Physical
Data Tag B
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Tag Aux Tag
Joint TLB
Coprocessor 0
System/Memory
Control
PC Incrementer
Branch Adder
Instruction TLB Virtual
Program Counter
Instruction Set A
Instruction Select
Integer Instruction Register
FP Instruction Register
Instruction Set B
Integer/Address Adder
Integer Control
DVA
IVA
Integer Multiply, Divide
IntIBus
Load Aligner
Integer Register File
Data TLB Virtual
Sh ift e r/ S t o r e A l ig ner
Logic Unit
ABus
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Technology
Preliminary
– RISC TurboEngines For The Future © SCD5230 REV 1 12/22/98
Page 2
DESCRIPTION
The ACT5230 is a highly integrated superscalar
microprocessor that implements a superset of the
MIPS IV Instruction Set Architecture(ISA). It has a
high performance 64-bit integer unit, a high
throughput, fully pipelined 64-bit floating point unit,
an opera ting system frie ndly memory ma nagement
unit with a 48-entry fully associative TLB, a 16 KByte
2-way set assoc iative ins tructio n cache , a 16 K Byte
2-way set associative data cache, and a
high-performance 32-bit system interface. The
ACT5230 can issue both an integer and a floating
point instruction in the same cycle.
The ACT5230 is ideally suited for high-end
embedded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.
HARDWARE OVERVIEW
The ACT5230 offers a high-level of integration
targeted at high-performance embedded
applications. Some of the key elements of the
ACT523 0 are briefly des c ribed below.
Superscalar Dispatch
The ACT5230 has an efficient asymmetric
superscal ar disp atch u nit w hic h allo ws it to i ssu e an
integer instruction and a floating-point computation
instruction simultaneously. With respect to
superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/store,
while flo ating-poin t computat ion instruc tions inc lude
floating- point add, subtra ct, combined m ultiply-add,
converts, etc. In combination with its hig h throughput
fully pipelined floating-point execution unit, the
superscalar capability of the ACT5230 provides
unparalleled price/performance in computationally
intensive embedded applications.
CPU Registers
Like all M IPS ISA proce ssors, the A CT5230 CPU
has a simple, clean user visible state consisting of 32
general purpose registers, two special purpose
registers for integer multiplication and division, a
program c ounter, and no conditio n c ode bits.
therefore fully upward compatible with applications
that run on processors implementing the earlier
generation MIPS I-III instruction sets. Additionally,
the ACT5230 includes two implementation specific
instruct ions not foun d in the base line MIPS IV ISA
but that are useful in the embedded market place.
Describe d in detail in the QED RM5230 datasheet,,
these instructions are integer multiply-accumulate
and 3-operand integer multiply.
The ACT5230 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/divide
unit. Additional register resources include: the HI/LO
result r egisters for the t wo-op erand in teger m ultiply/
divide operations, and the prog ram counte r(PC).
Register File
The ACT5230 has thirty-two general purpose
registe rs with registe r locat ion 0 h ard wired to zero.
These registers are used for scalar integer
operatio ns a nd addr ess cal cula tion. T he r eg ister f ile
has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.
ALU
The ACT5230 ALU consists of the integer adder/
subtra ctor, the logic un it, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in
a single processor cycle
For Detail Information regarding the operation of
the Quantum Effect Design (QED) RISCMark
RM5230, 32-Bit Superscalar Microprocessor see
the QED dat asheet (R ev is ion 1.2 July 1998).
Pipeline
For integer operations, loads, stores, and other
non-floating-point operations, the ACT5230 uses the
simple 5-stage pipeline also found in the QED
circuits R4600, R4700, and R5000. In addition to this
standard pipeline, the ACT5230 uses an extended
seven stage pipeline for floating-point operations.
Like the QED R5000, th e ACT5230 d oes virtual to
physical t ranslation in p arallel with ca c he access.
Integer Unit
Like the QED R5000, the ACT5230 implements
the MIPS IV Instruction Set Architecture, and is
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SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
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Absolute Maximum Ratings
1
Symbol Rating Range Units
T
TERM
T
CASE
T
BIAS
T
STG
I
IN
I
OUT
Notes:
1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. V
minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +5.5 Volts.
IN
3. When V
4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.
IN
Terminal Voltage with respect to GND
Operating Temperature
Case Temperature under Bias
Storage Temperature
DC Input Current
DC Output Current
< 0V or VIN > Vcc.
2
-0.5
to 4.6 V
0 to +85 °C
-55 to +125 °C
-55 to +125 °C
3
20
mA
50 mA
Recommended Operating Conditions
Symbol Parameter Minimum Maximum Units
V
CC
V
IH
V
IL
T
C
Power Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature Case (Commercial)
+3.135 +3.465 V
0.7V
CC
-0.5 0.2V
V
+ 0.5 V
CC
CC
0 +85 °C
V
DC Characteristics
(VCC = 3.3V ±5%; T
Parameter Sym Conditions
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
Input Current
Input Current
Input Current
Input Capacitance
Output Capacitance
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V
V
V
V
C
OL1
OH1
OL2
OH2
V
V
I
IN1
I
IN2
I
IN3
C
OUT
IOL = 20 µA
IOL = 20 µA
IOL = 4 mA
IOL = 4 mA
IH
IL
V
= 0V
IN
V
= V
IN
CC
V
= 5.5V
IN
IN
CASE
= 0°C to +85°C)
3
133 / 150MHz
Min
Max
Units
0.1 V
Vcc - 0.1 V
0.4 V
2.4 V
0.7V
-0.5 0.2V
CC
V
+ 0.5 V
CC
CC
V
-20 +20 µA
-20 +20 µA
-250 +250 µA
10 pF
10 pF
SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
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Power Consumption
Parameter Symbol Conditions
Active Operating
Supply Current
Standby Current
Notes:
5. Typical integer instruction mix and cache miss rates.
I
CC1
I
CC2
I
CC3
I
SB1
I
SB1
CL = 0pF, 150/75MHz, No SysAD
activity
CL = 50pF, 150/75MHz, R4000 write
protocol without FPU operation
CL = 50pF, 150/75MHz, write
re-issue or pipelined writes
CL = 0pF, 150/75MHz
CL = 50pF, 150/75MHz
AC Characteristics
(VCC = 3.3V ±5%; T
Capacitive Load Deration
Symbol Parameter
CASE
= 0°C to +85°C)
133MHz, 3.3V 150MHz, 3.3V
Typ
5
Max
Typ5
Max
Units
TBD TBD TBD TBD mA
1000 1750 1150 1950 mA
1100 2000 1250 2250 mA
TBD TBD mA
TBD TBD mA
133 / 150MHz
Units
Minimum Maximum
LD
C
Load Derate
Clo ck Parameters
Parameter Symbol Test Conditions
SysClock High
SysClock Low
SysClock Frequency
6
SysClock Period
Clock Jitter for SysClock
SysClock Rise Time
SysClock Fall Time
ModeClock Period
t
SCHigh
t
SCLow
t
SCP
t
JitterIn
t
SCRise
t
SCFall
t
ModeCKP
Transition < 5ns
Transition < 5ns
2 ns/25pF
133/150MHz
Units
Min
Max
4ns
4ns
33 75 MHz
30 ns
±250 ps
5ns
5ns
256*t
SCP
ns
JTA Cloc k Period
Notes:
6. Operation of the ACT5230 is only guaranteed with the Phase Loop enabled.
Aeroflex Cir cuit Technology
t
JTAGCKP
4*t
SCP
4
SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
ns
Page 5
System Interface Parameters
7
Parameter Symbol Test Conditions
Data Output
Data Setup
Data Hold
Notes:
7. Timmings are are measured from from 1.5V of the clock to 1.5V of the signal.
8. Capacitive load for all output timing is 50pF.
8
t
DO
t
DS
t
DH
mode
mode
mode
mode
t
RISE
t
FALL
14...13
= 10 (fastest)
14...13
= 11
14...13
= 00
14...13
= 01 (slowe s t )
= 5ns
= 5ns
Boot Time Interface Parameters
Parameter Symbol Test Conditions
133MHz 150MHz
Units
Min
Max
Min
Max
TBD TBD TBD TBD ns
TBD TBD TBD TBD ns
1.0 8.0 1.0 8.0 ns
TBD TBD TBD TBD ns
4.0 4.0 ns
00ns
133/150MHz
Units
Min
Max
Mode Data Setup
Mode Data Hold
t
t
DS
DH
4 SysClock cycles
0 SysClock cycles
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SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
Page 6
ACT5230 Microprocessor – PQUAD Pinouts
Pin # Funct i on Pin # Function Pin # Function Pin # Fu nct i on
1 Vcc 53 NC 105 Vcc 157 NC
2 NC 54 NC 106 NMI* 158 NC
3 NC 55 NC 107 ExtRqst* 159 NC
4 Vcc 56 Vcc 108 Reset* 160 NC
5 Vss 57 Vss 109 ColdReset* 161 Vcc
6 SysA D4 58 ModeIn 110 VccOK 162 Vss
7 NC 59 RdRdy* 111 BigEndian 163 S ysAD28
8 SysAD5 60 WrRdy* 112 Vcc 164 NC
9 NC 61 ValidIn* 113 Vss 165 S ysAD29
10 Vcc 62 ValidOut* 114 SysAD16 166 NC
11 Vss 63 Release* 115 NC 167 Vcc
12 SysAD6 64 VccP 116 Vcc 168 Vss
13 NC 65 V ssP 117 Vss 169 SysAD30
14 Vcc 66 SysClock 118 SysAD17 170 NC
15 Vss 67 Vcc 119 NC 171 Vc c
C
o
n
ta
16 SysAD7 68 Vss 120 SysAD18 172 Vs s
17 NC 69 Vcc 121 NC 173 SysAD31
18 SysAD8 70 V ss 122 V cc 174 NC
19 NC 71 Vcc 123 Vss 175 SysADC2
20 Vcc 72 Vss 124 SysAD19 176 SysADC6
21 Vss 73 SysCmd0 125 NC 177 Vcc
22 SysAD9 74 Sys Cmd1 126 Vcc 178 Vss
23 NC 75 SysCmd2 127 Vss 179 SysADC3
24 Vcc 76 SysCmd3 128 SysAD20 180 SysADC7
25 Vss 77 Vcc 129 NC 181 Vc c
e
P
&
26 SysAD10 78 Vss 130 SysAD21 182 Vss
27 NC 79 SysCmd4 131 NC 183 SysADC0
28 SysAD11 80 SysCmd5 132 Vcc 184 SysADC4
29 NC 81 Vcc 133 V ss 185 Vcc
30 Vcc 82 Vss 134 SysAD22 186 Vss
31 Vss 83 SysCmd6 135 NC 187 SysADC1
32 SysAD12 84 SysCmd7 136 Vcc 188 SysADC5
33 NC 85 SysCmd8 137 Vss 189 SysAD0
34 Vcc 86 SysCmdP 138 SysAD23 190 NC
35 Vss 87 Vcc 139 NC 191 Vc c
36 SysAD13 88 Vss 140 SysAD24 192 Vss
37 NC 89 Vcc 141 NC 193 SysAD1
38 SysAD14 90 Vss 142 Vcc 194 NC
39 NC 91 Vcc 143 V ss 195 Vcc
40 Vcc 92 Vss 144 SysAD25 196 Vss
41 Vss 93 Int0* 145 NC 197 SysA D2
42 SysAD15 94 Int1* 146 V cc 198 NC
43 NC 95 Int2* 147 Vss 199 SysAD3
44 Vcc 96 Int3* 148 SysAD26 200 NC
45 Vss 97 Int4* 149 NC 201 Vcc
46 ModeClock 98 Int5* 150 SysAD27 202 V ss
47 JTDO 99 Vcc 151 NC 203 NC
48 JTDI 100 Vss 152 Vcc 204 NC
49 JTCK 101 NC 153 Vss 205 NC
50 JTMS 102 NC 154 NC 206 NC
51 Vcc 103 NC 155 NC 207 Vcc
52 Vss 104 NC 156 Vss 208 Vss
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Aeroflex Cir cuit Technology
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SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
Page 7
CIRCUIT TECHNOLOGY
Sample Ordering Informati on
Part Number Screening Speed (MHz) Package
ACT-5230PC-133F22I Industrial Temperature 133 128 Lead PQUAD
ACT-5230PC-150F22C Comm ercial Temperature 150 128 Lead PQUAD
ACT-5230PC-200F22T Military Temperature 200 128 Lead PQUAD
ACT-5230PC-200F22M Military Screening 200 128 Lead PQUAD
Part Number Breakdown
ACT– 5230 PC – 133 F22 M
Aeroflex Circuit
Technology
Base Processor Type
Cache Style
PC = Primary Cache
Maximum Pipeline Freq.
133 = 133MHz
150 = 150MHz
200 = 200MHz
Specifications subject to change without notice.
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11803
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screened
Q = MIL-PRF-38534 Compliant/SMD if applicable
F22 = 1.10" SQ 128 Lead PQUAD
Screened to the individual test methods of MIL-STD-883
*
Telephone: (516) 694-6700
FAX: (516) 694-6715
Toll Free Inquiries: (800) 843-1553
Screening
*
Package Type & Size
Surface Mount Package
www.aeroflex.com/act1.htm E-Mail: sales-act@aeroflex.com
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7
SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
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