• Significant Power Reduction Compared to ALSTTL
Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current ≤1µA at VOL, VOH
Description
The Intersil ACS86MS is a radiation hardened quad 2-input
exclusive OR gate. A high logic level on both inputs forces
the output to a logic low state.
The ACS86MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C
TOP VIEW
A1
1
2
B1
3
Y1
4
A2
5
B2
6
Y2
7
GND
14 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
1
2
3
4
5
6
7
14
VCC
13
B4
12
A4
11
Y4
10
B3
9
A3
8
Y3
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
Ordering Information
PART NUMBERTEMPERATURE RANGESCREENING LEVELPACKAGE
ACS86DMSR-55oC to +125oCIntersil Class S Equivalent14 Lead SBDIP
ACS86KMSR-55oC to +125oCIntersil Class S Equivalent14 Lead Ceramic Flatpack
ACS86D/Sample+25oCSample14 Lead SBDIP
ACS86K/Sample+25oCSample14 Lead Ceramic Flatpack
ACS86HMSR+25oCDieDie
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Time at 4.5V VCC (TR, TF). . . . . . .10ns/V Max
1. The parameters listed in T able 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TPHLVCC = 4.5V, VIH = 4.5V,
TPLHVCC = 4.5V, VIH = 4.5V,
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
CPDVCC = 5.0V, VIH = 5.0V,
CONDITIONS
VIL = 0V
VIL = 0V
VIL = 0V, f = 1MHz
VIL = 0V, f = 1MHz
A SUB-
GROUPSTEMPERATURE
9+25oC212ns
10, 11+125oC, -55oC213ns
1+25oC1+125oC1+25oC--10pF
1+125oC--10pF
LIMITS
LIMITS
TBD
TBD
UNITSMINMAX
UNITSMINTYPMAX
-pF
-pF
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
RAD
(NOTE 1)
PARAMETERSYMBOL
Supply CurrentICCVCC = 5.5V, VIN = VCC or GND+25oC-100µA
Output Current
(Source)
Output Current (Sink)IOLVCC = VIH = 4.5V,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull Method 2023
100% Internal Visual Inspection Method 2010
100% Temperature Cycling Method 1010 Condition C
(-65
o
to +150oC)
100% Constant Acceleration
100% PIND Testing
100% External Visual Inspection
100% Serialization
100% Initial Electrical Test
o
100% Static Burn-In 1 Method 1015, 24 Hours at +125
C Min
100% Interim Electrical Test 1 (Note 1)
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number , Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min
100% Interim Electrical Test 2 (Note 1)
100% Dynamic Burn-In Method 1015, 240 Hours at +125
or 180 Hours at +135
o
C
100% Interim Electrical Test 3 (Note 1)
100% Final Electrical Test
100% Fine and Gross Seal Method 1014
100% Radiographics Method 2012 (2 Views)
100% External Visual Method 2009
Group A (All Tests) Method 5005 (Class S)
Group B (Optional) Method 5005 (Class S) (Note 2)
Group D (Optional) Method 5005 (Class S) (Note 2)
CSI and/or GSI (Optional) (Note 2)
Data Package Generation (Note 3)
o
C
Propagation Delay Timing Diagram and Load Circuit
VIH
TPLH
INPUT
VS
TPHL
OUTPUT
PARAMETERACSUNITS
VCC4.50V
VIH4.50V
VS2.25V
VIL0V
GND0V
5
VS
VSS
VOH
VOL
DUTTEST
CL
50pF
AC VOLTAGE LEVELS
POINT
RL
500Ω
Spec Number 518849
Page 6
Die Characteristics
ACS86MS
DIE DIMENSIONS:
88 mils x 88 mils
2.24mm x 2.24mm
METALLIZATION:
Type: AlSiCu
Metal 1 Thickness: 6.75k
Metal 2 Thickness: 9k
Å (Min), 8.25kÅ (Max)
Å (Min), 11kÅ (Max)
GLASSIVATION:
Type: SiO
2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
DIE ATTACH:
Material: Silver Glass or JM7000 Polymer after 7/1/95
WORST CASE CURRENT DENSITY:
< 2.0 x 10
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110µm x 110µm
ACS86MS
(2)(1)(13)
A1B4B1
VCC
(14)
5
A/cm
2
Y1 (3)
A2 (4)
NC
B2 (5)
(6)(7)(8)
GNDY3Y2
(9)
A3
(12) A4
(11) Y4
NC
(10) B3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518849
6
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