2.5 Amp Output Current IGBT Gate Driver Optocoupler
with Integrated (VCE) Desaturation Detection, UVLO
Fault Status Feedback and Active Miller Clamping
Data Sheet
Description
The ACPL-332J is an advanced 2.5 A output current,
easy-to-use, intelligent gate driver which makes IGBT
VCE fault protection compact, aordable, and easy-to
implement. Features such as integrated VCE detection,
under voltage lockout (UVLO), “soft” IGBT turn-o, isolated
open collector fault feedback and active Miller clamping
provide maximum design exibility and circuit protection.
The ACPL-332J contains a GaAsP LED. The LED is optically
coupled to an integrated circuit with a power output
stage. ACPL-332J is ideally suited for driving power IGBTs
and MOSFETs used in motor control inverter applications.
The voltage and current supplied by these optocouplers
make them ideally suited for directly driving IGBTs with
ratings up to 1200 V and 150 A. For IGBTs with higher
ratings, the ACPL-332J can be used to drive a discrete
power stage which drives the IGBT gate. The ACPL-332J
has an insulation voltage of V
Block Diagram
Features
• Under Voltage Lock-Out Protection (UVLO) with
Hysteresis
• Desaturation Detection
• Miller Clamping
• Open Collector Isolated fault feedback
• “Soft” IGBT Turn-o
• Fault Reset by next LED turn-on (low to high) after
fault mute period
• Available in SO-16 package
• Safety approvals: UL approved, 3750 V
CSA approved, IEC/EN/DIN-EN 60747-5-2 approved
V
= 891 V
IORM
PEAK
Specications
• 2.5 A maximum peak output current
= 891 V
IORM
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
PEAK
.
• 2.0 A minimum peak output current
• 250 ns maximum propagation delay over temperature
range
• 100 ns maximum pulse width distortion (PWD)
• 15 kV/µs minimum common mode rejection (CMR) at
VCM = 1500 V
• I
< 5 mA maximum supply current
CC(max)
• Wide VCC operating range: 15 V to 30 V over
temperature range
• 1.7 A Miller Clamp. Clamp pin short to VEE if not used
• Wide operating temperature range: –40°C to 100°C
Applications
• Isolated IGBT/Power MOSFET gate drive
• AC and brushless DC motor drives
• Industrial inverters and Uninterruptible Power Supply
(UPS)
for 1 minute,
RMS
Page 2
Pin Description
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
PinSymbolDescription
1V
2V
S
CC1
3FAULTFault output. FAULT changes from a high impedance state
4V
S
5CATHODECathode
6ANODEAnode
7ANODEAnode
8CATHODECathode
9V
10V
11V
12V
13V
EE
CLAMP
OUT
EE
CC2
14DESATDesaturation voltage input. When the voltage on DESAT
15V
16V
LED
E
Input Ground
Positive input supply voltage. (4.5 V to 5.5 V)
to a logic low output within 5 µs of the voltage on the
DESAT pin exceeding an internal reference voltage of 7 V.
FAULT output is an open collector which allows the FAULT
outputs from all ACPL-332J in a circuit to be connected
together in a “wired OR” forming a single fault bus for interfacing directly to the micro-controller.
Input Ground
Output supply voltage.
Miller clamp
Gate drive voltage output
Output supply voltage.
Positive output supply voltage
exceeds an internal reference voltage of 6.5 V while the
IGBT is on, FAULT output is changed from a high impedance
state to a logic low state within 5 µs.
LED anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing
only)
Common (IGBT emitter) output supply voltage.
Ordering Information
ACPL-332J is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part number
ACPL-332J-000ESO-16XX45 per tube
-500E
Package
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-332J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-2 Safety Approval in RoHS compliant.
Example 2:
ACPL-332J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-
2 Safety Approval and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
Surface
MountTape& Reel
XXX
IEC/EN/DIN EN
60747-5-2QuantityRoHS Compliant
850 per reel
2
Page 3
Package Outline Drawings
9
0.295 ± 0.010
(7.493 ± 0.254)
10111213141516
87654321
0.018
(0.457)
0.138 ± 0.005
(3.505 ± 0.127)
9°
0.406 ± 0.10
(10.312 ± 0.254)
0.408 ± 0.010
(10.363 ± 0.254)
0.025 MIN.
0.008 ± 0.003
(0.203 ± 0.076)
STANDOFF
0.345 ± 0.010
(8.763 ± 0.254)
0- 8 °
0.018
(0.457)
0.050
(1.270)
ALL LEADS
TO BE
COPLANAR
± 0.002
A 332J
YYWW
TYPE NUMBER
DATE CODE
0.458 (11.63)
0.085 (2.16)
0.025 (0.64)
LAND PATTERN RECOMMENDATION
ACPL-332J 16-Lead Surface Mount Package
Dimensions in inches (millimeters)
Notes: Initial and continued variation in the color of the ACPL-332J’s white mold compound is normal and does note aect device performance or
reliability.
Floating Lead Protrusion is 0.25 mm (10 mils) max.
NO TES:
THE TIME FROM 25°C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200 °C, T
smin
= 150 °C
Note: Non-halide ux should be used.
Recommended Pb-Free IR Prole
Note: Non-halide ux should be used.
4
Page 5
Regulatory Information
The ACPL-332J is approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
Approval under:
IEC 60747-5-2 :1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
UL
Approval under UL 1577, component recognition
program up to V
= 3750 V
ISO
. File E55361.
RMS
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
DescriptionSymbolCharacteristicUnit
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 V
for rated mains voltage ≤ 300 V
for rated mains voltage ≤ 600 V
rms
rms
rms
Climatic Classication55/100/21
Pollution Degree (DIN VDE 0110/1.89)2
Maximum Working Insulation VoltageV
Input to Output Test Voltage, Method b**,
V
x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
IORM
Input to Output Test Voltage, Method a**,
V
x 1.5=VPR, Type and Sample Test, tm=60 sec, Partial discharge < 5 pC
IORM
Highest Allowable Overvoltage (Transient Overvoltage t
= 10 sec)V
ini
V
V
IORM
PR
PR
IOTM
Safety-limiting values – maximum values allowed in the event of a failure.
Case TemperatureT
Input CurrentI
Output PowerP
Insulation Resistance at TS, VIO = 500 VR
S
S, INPUT
S, OUTPUT
S
I – IV
I – IV
I – III
891V
1670V
1336V
6000V
175
400mA
1200mW
9
>10
peak
peak
peak
peak
°C
W
* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classication is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test proles.
Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)
5
Page 6
Table 2. Insulation and Safety Related Specications
ParameterSymbolACPL-332JUnitsConditions
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
Isolation GroupIIIaMaterial Group (DIN VDE 0110, 1/89, Table 1)
L(101)8.3MmMeasured from input terminals to output terminals,
shortest distance through air.
L(102)8.3MmMeasured from input terminals to output terminals,
shortest distance path along body.
0.5MmThrough insulation distance conductor to conductor,
usually the straight line distance thickness between
the emitter and detector.
CTI>175VDIN IEC 112/VDE 0303 Part 1
Table 3. Absolute Maximum Ratings
ParameterSymbolMin.Max.UnitsNote
Storage TemperatureT
Operating TemperatureT
Output IC Junction TemperatureT
Average Input CurrentI
Peak Transient Input Current,
S
A
J
F(AVG)
I
F(TRAN)
(<1 µs pulse width, 300pps)
Reverse Input VoltageV
“High” Peak Output CurrentI
“Low” Peak Output CurrentI
Positive Input Supply VoltageV
FAULT Output CurrentI
FAULT Pin VoltageV
Total Output Supply Voltage(V
R
OH(PEAK)
OL(PEAK)
CC1
FAULT
FAULT
- VEE)-0.533V
CC2
Negative Output Supply Voltage(VE - VEE)-0.515V6
Positive Output Supply Voltage(V
Gate Drive Output VoltageV
Peak Clamping Sinking CurrentI
Miller Clamping Pin VoltageV
DESAT VoltageV
Output IC Power DissipationP
Input IC Power DissipationP
- VE)-0.533 - (VE - VEE)V
CC2
O(PEAK)
Clamp
Clamp
DESAT
O
I
Solder Reow Temperature ProleSee Package Outline Drawings section
-55125°C
-40100°C2
125°C2
25mA1
1.0A
5V
2.5A3
2.5A3
-0.55.5V
8.0mA
-0.5V
-0.5V
CC1
CC2
V
V
1.7A
-0.5V
V
E
CC2
VE + 10V
V
600mW2
150mW2
Table 4. Recommended Operating Conditions
ParameterSymbolMin.Max.UnitsNote
Operating TemperatureT
Total Output Supply Voltage(V
A
- VEE)1530V7
CC2
Negative Output Supply Voltage(VE - VEE)015V4
Positive Output Supply Voltage(V
Input Current (ON)I
Input Voltage (OFF)V
- VE)1530 - (VE - VEE)V
CC2
F(ON)
F(OFF)
6
- 40100°C2
812mA
- 3.60.8V
Page 7
Table 5. Electrical Specications (DC)
Unless otherwise noted, all typical values at TA = 25°C, V
- VEE = 30 V, VE - VEE = 0 V;
CC2
all Minimum/Maximum specications are at Recommended Operating Conditions. Positive Supply Voltage used.
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. In order to achieve the absolute maximum power dissipation specied, pins 4, 9, and 10 require ground plane connections and may require
airow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air ow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require derating.
3. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. Derate
linearly from 3.0 A at +25°C to 2.5 A at +100°C. This compensates for increased I
4. This supply is optional. Required only when negative gate drive is implemented.
5. Maximum pulse width = 50 µs.
6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
7. 15 V is the recommended minimum operating positive supply voltage (V
threshold of 12.5V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero units.
8. Maximum pulse width = 1.0 ms.
9. Once VO of the ACPL-332J is allowed to go high (V
IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
DESAT detection and UVLO features of the ACPL-332J work in conjunction to ensure constant IGBT protection.
10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.
11. This is the “increasing” (i.e. turn-on or “positive going” direction) of V
12. This is the “decreasing” (i.e. turn-o or “negative going” direction) of V
13. This load condition approximates the gate load of a 1200 V/150A IGBT.
14. Pulse Width Distortion (PWD) is dened as |t
15. As measured from IF to VO.
16. The dierence between t
17. As measured from ANODE, CATHODE of LED to V
18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
19. This is the amount of time the DESAT threshold must be exceeded before V
voltage dependent.
20. Auto Reset: This is the amount of time when V
Reset) topic in the application information section.
21. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 2.1 kΩ pull-up resistor is needed in fault detection mode.
22. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 µA
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
PHL
and t
V
ISO
3750V
rms
RH < 50%, t = 1 min.,
TA = 25°C
9
I-O
I-O
q
09-10
CC2
- t
PHL
PLH
between any two ACPL-332J parts under the same test conditions.
PLH
OUT
will be asserted low after DESAT threshold is exceeded. See the Description of Operation (Auto
OUT
> 10
1.3pFfreq=1 MHz
30°C/WTA = 25°C
- VE > V
| for any given unit.
), the DESAT detection feature of the ACPL-332J will be the primary source of
UVLO
UVLO+
- V
CC2
CC2
W
OPEAK
- VE) to ensure adequate margin in excess of the maximum V
CC2
> 12.5 V, DESAT will remain functional until V
E
- V
E
begins to go low, and the FAULT output to go low. This is supply
OUT
V
I-O
due to changes in VOL over temperature.
= 500 V7
< 9.2 V. Thus, the
UVLO-
6, 7
UVLO+
9
Page 10
1.0
1.5
2.0
2.5
3.0
-40-20020406080100
TA- TEMPERATURE -oC
I
OH
- OUTPUT HIGH CURRENT - A
0
1
2
3
4
5
-40-20020406080100
TA- TEMPERATURE -oC
I
OL
- OUTPUT LOW CURRENT
-----V
OUT=VEE
+15V
___V
OUT=VEE
+2.5V
-3
-2.5
-2
-1.5
-1
-0.5
0
-40-20020406080100
TA- TEMPERATURE -oC
(V
OH
- V
CC
) - HIGH OUTPUT VOLTAGE DROP - V
------I
OUT
= -100mA
____I
OUT
= -650uA
0
0.05
0.1
0.15
0.2
0.25
-40-20020406080100
TA- TEMPERATURE -oC
V
OL
- OUTPUT LOW VOLTAGE - V
Figure 1. VOUT propagation delay waveforms
I
F
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
Figure 2. IOH vs. temperatureFigure 3. IOL vs. temperature
Figure 4. VOH vs. temperatureFigure 5. VOL vs. temperature
10
Page 11
0
1
2
3
4
-40-20020406080100
TA-TEMPERATURE-oC
I
CL
- CLAMP LOW LEVEN SINKING CURRENT
15202530
2.25
2.35
2.45
2.55
2.65
V
CC2
- OUTPUR SUPPLY VOLTAGE - V
I
CC2
- OUTPUT SUPPLY CURRENT - mA
---------I
Cc 2H
_
________
I
CC2L
2.00
2.25
2.50
2.75
3.00
3.25
3.50
-40-20020406080100
TA - TEMPERATURE - oC
I
CC2
- OUTPUT SUPPLY CURRENT - mA
----- ----I
CC2 H
_
________
I
CC2L
-0.35
-0.30
-0.25
-0.20
-40-20020406080100
TA- TEMPERATURE -oC
I
CH
- BLANKING CAPACITOR
CHARGING CURRENT - mA
28.0
28.5
29.0
29.5
30.0
00.20.40.60.81
IOH - OUTPUT HIGH CURRENT - A
V
OH
- HIGH OUTPUT VOLTAGE DROP - V
_ _ _ _ 100oC
______ 25oC
--------- -40oC
Figure 6. VOH vs. I
0
1
2
3
4
5
6
7
8
00.511.522.5
IoL - OUTPUT LOW CURRENT - A
V
OL
- LOW OUTPUT VOLTAGE DROP - V
_ _ _ _ 100oC
______ 25oC
--------- -40oC
OH
Figure 7. VOL vs. I
OL
Figure 8. ICL vs. temperature
Figure 10. I
11
vs. V
CC2
CC2
Figure 9. I
Figure 11. I
vs. temperature
CC2
vs. temperature
CHG
Page 12
100
150
200
250
300
15202530
Vcc - SUPPLY VOLTAGE - V
T
P
- PROPAGATION DELAY - ns
----------t
PLH
_______t
PHL
100
150
200
250
300
01020304050
LOAD RESISTANCE - ohm
T
P
- PROPAGATION DELAY - ms
----------t
PLH
_______t
PHL
0
100
200
300
01020304050
LOAD CAPACITANCE - nF
----------t
PLH
_______t
PHL
T
P
- PROPAGATION DELAY - ms
Figure 12. DESAT threshold vs. temperature
6.0
6.5
7.0
7.5
-40-20020406080100
TA- TEMPERATURE -oC
V
DESAT
- DESAT THRESHOLD - V
100
150
200
250
300
-40-20020406080100
TA- TEMPERATURE -oC
T
P
- PROPAGATION DELAY - ns
----------t
PLH
_______t
PHL
Figure 13. Propagation delay vs. temperature
Figure 14. Propagation delay vs. supply voltage
Figure 16. Propagation delay vs. load capacitance
12
Figure 15. Propagation delay vs. load resistance
Page 13
1.0
1.5
2.0
2.5
3.0
-40-20020406080100
TA- TEMPERATURE -oC
T
DESAT
- DESAT Sense to 10% Vo Delay - us
-------V
cc2
=15V
_____V
cc2
=30V
0.0
1.0
2.0
3.0
4.0
1020304050
LOAD RESISTANCE - ohm
-------V
cc2
=15V
_____V
cc2
=30V
T
DESAT10%
- DESAT Sense to 10% Vo Delay - us
0.000
0.004
0.008
0.012
01020304050
LOAD CAPACITANCE - nF
-------V
cc2
=15V
_____V
cc2
=30V
T
DESAT10%
- DESAT Sense to 10% Vo Delay - ms
100
150
200
250
300
-40-20020406080100
TA- TEMPERATURE -oC
T
DESAT90%
- DESAT Sense to 90% Vo Delay - ns
Figure 17. DESAT sense to 90% VOUT delay vs. temperature
Figure 18. DESAT sense to 10% VOUT delay vs. temperature
Figure 19. DESAT sense to 10% VOUT delay vs. load resistance
13
Figure 20. DESAT sense to 10% VOUT delay vs. load capacitance
Page 14
Figure 21. IOH Pulsed test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
10mA
+
_
0.1µF
0.1µF
15V Pulsed
I
OUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
10mA
+
_
0.1µF0.1µF
0.1µF0.1µF
15V Pulsed
I
OUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
+
_
0.1µF
0.1µF
15V Pulsed
I
OUT
30V
+
_
0.1µF
0.1µF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
100mA
V
OUT
30V
10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
100mA
V
OUT
30V
10mA10mA
Figure 22. IOL Pulsed test circuit
Figure 23. VOH Pulsed test circuit
14
Page 15
Figure 24. VOL Pulsed test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
100mA
V
OUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
100mA
V
OUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
I
CC2
30V
10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
I
CC2
30V
10mA10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
30V
I
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
30V
I
CC2
Figure 25. I
Figure 26. I
15
CC2H
CC2L
test circuit
test circuit
Page 16
Figure 27. I
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
I
CHG
30V
10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
I
CHG
30V
10mA10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
7V
30V
+
_
IDSCHG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
7V
30V
+
_
IDSCHG
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
V
OUT
30V
10Ω
10mA, 10kHz,
50% Duty Cycle
10nF10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
V
OUT
30V
10mA, 10kHz,
50% Duty Cycle
Pulsed test circuit
CHG
Figure 28. I
Figure 29. t
16
DSCHG
, t
PLH
test circuit
, tf, tr, test circuit
PHL
Page 17
V
CM
10
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
430Ω
2.1kΩ
0.1µF
15pF
5V
V
CM
10Ω
10nF10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF0.1µF
SCOPE
30V
0.1µF0.1µF
15pF15pF
5V5V
V
CM
10Ω
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
430Ω
2.1kΩ
0.1µF
15pF
5V
V
CM
10nF10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF0.1µF
SCOPE
30V
0.1µF0.1µF
15pF15pF
5V5V
Figure 30. t
10nF
+
_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
5V
0.1µF
0.1µF
V
OUT
30V
10Ω
V
IN
2.1kΩ
V
FAULT
10mA
10nF
+
_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
5V
0.1µF0.1µF
0.1µF0.1µF
V
OUT
30V
V
IN
V
FAULT
10mA10mA
fault test circuit
DESAT
Figure 31. CMR Test circuit LED2 o
Figure 32. CMR Test Circuit LED2 on
17
Page 18
10
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
V
CM
430Ω
2.1kΩ
0.1µF
15pF
5V
1010Ω
10nF10nF
0.1µF0.1µF
SCOPE
30V
V
CM
10
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
430
2.1k
0.1µF
15pF
5V
SCOPE
2.1kΩ
0.1µF
15pF
5V
Ω
Ω
Figure 33. CMR Test circuit LED1 o
Figure 34. CMR Test Circuit LED1 on
18
Page 19
SHIELD
SHIELD
D
R
I
V
E
R
V
E
DESAT
V
CC2
V
OUT
V
CLAMP
V
EE
V
CC1
V
S
FAULT
ANODE
CATHODE
V
CLAMP
V
LED
6, 7
5, 8
2
3
1, 4
13
11
14
9, 12
10
16
15
DESAT
UVLO
LED1
LED2
SHIELD
SHIELD
D
R
I
V
E
R
V
E
DESAT
V
CC2
V
OUT
V
CLAMP
V
EE
V
CC1
V
S
FAULT
ANODE
CATHODE
V
CLAMP
V
LED
6, 7
5, 8
2
3
1, 4
13
11
14
9, 12
10
16
15
DESAT
UVLO
LED1
LED2
Application Information
Product Overview Description
The ACPL-332J is a highly integrated power control device
that incorporates all the necessary components for a
complete, isolated IGBT / MOSFET gate drive circuit with
fault protection and feedback into one SO-16 package.
Active Miller clamp function eliminates the need of
negative gate drive in most application and allows the
use of simple bootstrap supply for high side driver. An
optically isolated power output stage drives IGBTs with
power ratings of up to 150 A and 1200 V. A high speed
internal optical link minimizes the propagation delays
between the microcontroller and the IGBT while allowing
the two systems to operate at very large common mode
voltage dierences that are common in industrial motor
drives and other power switching applications. An output
IC provides local protection for the IGBT to prevent
damage during over current, and a second optical link
provides a fully isolated fault status feedback signal for
the microcontroller. A built in “watchdog” circuit, UVLO
monitors the power stage supply voltage to prevent IGBT
caused by insucient gate drive voltages. This integrated
IGBT gate driver is designed to increase the performance
and reliability of a motor drive without the cost, size, and
complexity of a discrete design.
Two light emitting diodes and two integrated circuits
housed in the same SO-16 package provide the input
control circuitry, the output power stage, and two optical
channels. The output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS process.
The forward optical signal path, as indicated by LED1,
transmits the gate control signal. The return optical signal
path, as indicated by LED2, transmits the fault status
feedback signal.
Under normal operation, the LED1 directly controls the
IGBT gate through the isolated output detector IC, and
LED2 remains o. When an IGBT fault is detected, the
output detector IC immediately begins a “soft” shutdown
sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from
inductive over voltages. Simultaneously, this fault status
is transmitted back to the input via LED2, where the fault
latch disables the gate control input and the active low
fault output alerts the microcontroller.
During power-up, the Under Voltage Lockout (UVLO)
feature prevents the application of insucient gate
voltage to the IGBT, by forcing the ACPL-332J’s output
low. Once the output is in the high state, the DESAT (VCE)
detection feature of the ACPL-332J provides IGBT protection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.
19
Figure 35. Block Diagram of ACPL-332J
Recommended Application Circuit
The ACPL-332J has an LED input gate control, and an
open collector fault output suitable for wired ‘OR’ applications. The recommended application circuit shown
in Figure 36 illustrates a typical gate drive implementation using the ACPL-332J. The following describes about
driving IGBT. However, it is also applicable to MOSFET.
Depending upon the MOSFET or IGBT gate threshold requirements, designers may want to adjust the VCC supply
voltage (Recommended VCC = 17.5V for IGBT and 12.5V
for MOSFET).
The two supply bypass capacitors (0.1 µF) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the charging
currents, a low current (5mA) power supply suces. The
desaturation diode D
trr below 75ns (e.g. ERA34-10) and capacitor C
necessary external components for the fault detection
circuitry. The gate resistor RG serves to limit gate charge
current and controls the IGBT collector voltage rise
and fall times. The open collector fault output has a
passive pull-up resistor RF (2.1 kW) and a 330 pF ltering
capacitor, CF. A 47 kW pull down resistor R
V
provides a predictable high level output voltage
OUT
(VOH). In this application, the IGBT gate driver will shut
down when a fault is detected and fault reset by next
cycle of IGBT turn on. Application notes are mentioned at
the end of this datasheet.
600V/1200V fast recovery type,
DESAT
PULL-DOWN
BLANK
are
on
Page 20
Figure 36. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp
+
_
+
_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
R
G
100 Ω
C
BLANK
D
DESAT
Q1
Q2
+
V
CE
-
R
F
R
R
PULL-DOWN
+ HVDC
- HVDC
3-PHASE
AC
+
V
CE
-
0.1µF 0.1µF
0.1µF
C
F
7
+
_
-
I
F
V
DESAT
V
OUT
FAULT
6.5V
50%
t
DESAT(LOW)
10%
t
DESAT(10%)
90%
t
DESAT(90%)
50%
t
DESAT(FAULT)
t
DESAT(MUTE))
50%
t
RESET(FAULT)
Reset done
during the
next LED
turn-on
I
F
V
DESAT
V
OUT
FAULTFAULT
6.5V
50%
t
DESAT(LOW)
10%
t
DESAT(10%)
90%
t
DESAT(90%)
50%
t
DESAT(FAULT)
t
DESAT(MUTE))
50%
t
RESET(FAULT)
Reset done
during the
next LED
turn-on
Description of Operation
Normal Operation
During normal operation, V
of the ACPL-332J is con-
OUT
trolled by input LED current IF (pins 5, 6, 7 and 8), with
the IGBT collector-to-emitter voltage being monitored
through DDESAT. The FAULT output is high. See Figure 37.
Fault Condition
The DESAT pin monitors the IGBT Vce voltage. When the
voltage on the DESAT pin exceeds 6.5 V while the IGBT is
on, V
the IGBT and prevent large di/dt induced voltages. Also
Figure 37. Fault Timing diagram
20
is slowly brought low in order to “softly” turn-o
OUT
activated is an internal feedback channel which brings
the FAULT output low for the purpose of notifying the
micro-controller of the fault condition.
Fault Reset
Once fault is detected, the output will be muted for 5 µs
(minimum). All input LED signals will be ignored during
the mute period to allow the driver to completely soft
shut-down the IGBT. The fault mechanism can be reset by
the next LED turn-on after the 5us (minimum) mute time.
See Figure 37.
Page 21
Output Control
Slow IGBT Gate Discharge during Fault Condition
The outputs (V
and FAULT) of the ACPL-332J are con-
OUT
trolled by the combination of IF, UVLO and a detected
IGBT Desat condition. Once UVLO is not active (V
> V
), VOUT is allowed to go high, and the DESAT (pin
UVLO
CC2
- VE
14) detection feature of the ACPL-332J will be the primary
source of IGBT protection. UVLO is needed to ensure
DESAT is functional. Once V
remain functional until V
UVLO-
> 10.5 V, DESAT will
UVLO+
< 11.1 V. Thus, the DESAT
detection and UVLO features of the ACPL-332J work in
conjunction to ensure constant IGBT protection.
Desaturation Detection and High Current Protection
The ACPL-332J satises these criteria by combining a high
speed, high output current driver, high voltage optical
isolation between the input and output, local IGBT desaturation detection and shut down, and an optically
isolated fault status feedback signal into a single 16-pin
surface mount package.
The fault detection method, which is adopted in the
ACPL-332J, is to monitor the saturation (collector)
voltage of the IGBT and to trigger a local fault shutdown
sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly
reduces the high short circuit IGBT current to prevent
damaging voltage spikes. Before the dissipated energy
can reach destructive levels, the IGBT is shut o. During
the o state of the IGBT, the fault detect circuitry is simply
disabled to prevent false ‘fault’ signals.
The alternative protection scheme of measuring IGBT
current to prevent desaturation is eective if the short
circuit capability of the power device is known, but
this method will fail if the gate drive voltage decreases
enough to only partially turn on the IGBT. By directly
measuring the collector voltage, the ACPL-332J limits the
power dissipation in the IGBT even with insucient gate
drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in
the IGBT is monitored, while the current sense method
relies on a preset current threshold to predict the safe
limit of operation. Therefore, an overly conservative over
current threshold is not needed to protect the IGBT.
When a desaturation fault is detected, a weak pull-down
device in the ACPL-332J output drive stage will turn on
to ‘softly’ turn o the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current
that could cause damaging voltage spikes due to lead
and wire inductance. During the slow turn o, the large
output pull-down device remains o until the output
voltage falls below VEE + 2 Volts, at which time the large
pull down device clamps the IGBT gate to VEE.
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
threshold. This time period, called the DESAT blanking
time is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor.
The nominal blanking time is calculated in terms of
external capacitance (C
(V
C
), and DESAT charge current (I
DESAT
BLANK
x V
DESAT
/ I
CHG
the recommended 100pF capacitor is 100pF * 6.5 V / 240
µA = 2.7 µsec.
The capacitance value can be scaled slightly to adjust the
blanking time, though a value smaller than 100 pF is not
recommended. This nominal blanking time represents
the longest time it will take for the ACPL-332J to respond
to a DESAT fault condition. If the IGBT is turned on while
the collector and emitter are shorted to the supply rails
(switching into a short), the soft shut-down sequence
will begin after approximately 3 µsec. If the IGBT collector
and emitter are shorted to the supply rails after the IGBT
is already on, the response time will be much quicker due
to the parasitic parallel capacitance of the DESAT diode.
The recommended 100pF capacitor should provide
adequate blanking as well as fault response times for
most applications.
), FAULT threshold voltage
BLANK
CHG
) as t
BLANK
=
. The nominal blanking time with
I
F
XActiveXXLow
XXYesLowLow
OFFXXXLow
ONNot ActiveNoHighHigh
UVLO (V
– VE)Desat Condition Detected on Pin 14Pin 3 (FAULT) OutputV
CC2
21
OUT
Page 22
Under Voltage Lockout
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
R
G
R
PULL-DOWN
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
R
G
R
PULL-DOWN
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
R
G
V
CC
100 Ω
100pF
D
DESAT
The ACPL-332J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insucient gate
voltage to the IGBT by forcing the ACPL-332J output
low during power-up. IGBTs typically require gate
voltages of 15 V to achieve their rated V
At gate voltages below 13 V typically, the V
CE(ON)
CE(ON)
voltage.
voltage
increases dramatically, especially at higher currents. At
very low gate voltages (below 10 V), the IGBT may operate
in the linear region and quickly overheat. The UVLO
function causes the output to be clamped whenever insucient operating supply (V
exceeds V
(the positive-going UVLO threshold), the
UVLO+
) is applied. Once V
CC2
CC2
UVLO clamp is released to allow the device output to turn
on in response to input signals. As V
0 V (at some level below V
UVLO+
tion circuitry becomes active. As V
(above V
), the UVLO clamp is released. Before the
UVLO+
is increased from
CC2
), rst the DESAT protec-
is further increased
CC2
time the UVLO clamp is released, the DESAT protection
is already active. Therefore, the UVLO and DESAT Fault
detection feature work together to provide seamless protection regardless of supply voltage (V
CC2
).
Active Miller Clamp
A Miller clamp allows the control of the Miller current
during a high dV/dt situation and can eliminate the use
of a negative supply voltage in most of the applications.
During turn-o, the gate voltage is monitored and the
clamp output is activated when gate voltage goes below
2V (relative to VEE). The clamp voltage is VOL+2.5V typ
for a Miller current up to 1100mA. The clamp is disabled
when the LED input is triggered again.
Figure 38. Output pull-down resistor.
DESAT Pin Protection Resistor
The freewheeling of yback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substantial current out of the driver if protection is not used. To
limit this current to levels that will not damage the driver
IC, a 100 ohm resistor should be inserted in series with
the DESAT diode. The added resistance will not alter the
DESAT threshold or the DESAT blanking time.
Other Recommended Components
The application circuit in Figure 36 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor, and a FAULT pin pullup resistor and
Active Miller Clamp connection.
Output Pull-Down Resistor
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of V
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly V
to V
the output voltage to V
R
to sink a static current of several 650 µA while the output
is high. Pull-down resistor values are dependent on the
amount of positive supply and can be adjusted according
to the formula, R
within a period of several microseconds. To limit
CC2
PULL-DOWN
between the output and VEE is recommended
pull-down
-3(VBE), a pull-down resistor,
CC2
= [V
-3 * (VBE)] / 650 µA.
CC2
22
. If the output
CC2
CC2
-3(VBE)
Figure 39. DESAT pin protection.
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can aect the fault pin
voltage while the fault output is in the high state. A 330
pF capacitor should be connected between the fault pin
and ground to achieve adequate CMOS noise margins at
the specied CMR value of 15 kV/µs. The added capacitance does not increase the fault output delay when a
desaturation condition is detected.
Page 23
Pull-up Resistor on FAULT Pin
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
+
_
R
G
Q1
Q2
+
V
CE
-
R
PULL-DOWN
+ HVDC
- HVDC
3-PHASE
AC
+
V
CE
-
0.1µF 0.1µF
0.1µF
Optional R
1
Optional R
2
R
G
Optional R
1
Optional R
2
*
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
+
_
R
G
Q1
Q2
+
V
CE
-
R
PULL-DOWN
+ HVDC
- HVDC
3-PHASE
AC
+
V
CE
-
0.1µF 0.1µF
0.1µF
Optional R
1
Optional R
2
R
3
9
R
G
Optional R
1
Optional R
2
R
3
*
The FAULT pin is an open collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Also the FAULT output can be wire ‘OR’ed together with
other types of protection (e.g. over-temperature, overvoltage, over-current ) to alert the microcontroller.
Other Possible Application Circuit (Output Stage)
Figure 40. IGBT drive with negative gate drive, external booster and desaturation detection (V
should be connected to VEE when it is not used)
CLAMP
VCLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology
Figure 41. Large IGBT drive with negative gate drive, external booster. V
23
control secondary discharge path for higher power application.
CLAMP
Page 24
Related Application Notes
AN5314 – Active Miller Clamp
AN5315 – “Soft” Turn-o Feature
AN1087 – Thermal Data for Optocouplers
AN1043 – Common-Mode Noise : Sources and Solutions
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