Datasheet ACD82124 Datasheet (ACD)

Advanced

Communication

Devices

Data Sheet: ACD82124

24 Ports 10/100 Fast Ethernet Switch Controller

Data Sheet: ACD82124

Rev .1.1.1.F

Last Update: November 5, 1998

Subject to Change

Please check ACD’s website for

update information before starting a design

Web site: http://www.acdcorp.com

or Contact ACD at:

Email: [e-mail]

T el: 408-433-9898x1 15

Fax: [phone]

INTRODUCTORY

ACD Confidential Material

For ACD authorized customer use only . No reproduction or redistribution without ACD’s prior permission.

1

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Table of Contents

Data Sheet: ACD82124

Section

1 General Description 3
2 Main Features 3
3 System Block Diagram 3
4System Description 4
5 Functional Description 4
6 Inter fac e De scription 10
7 Register Description 16
8 Pin Description 27
9 Timing Descripti on 32
10 Electr ical Specifications 38
11 Packaging 39

Appendix

A1 Address Resolution Logic 40

(The built -in AR L)

Page

INTRODUCTORY

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2

1. GENERAL DESCRIPTION

2. FEA TURES

The ACD82124 is a single chip implementation of a 24
port 10/100 Ethernet switch system intended for IEEE

802.3 and 802.3u compatible networks. The device
includes 24 independent 10/100 MACs. Each MAC
interfaces with an external PMD/PHY device through a
standard MII interface. Speed can be automatically
configured through the MDIO port. Each port can op­erate at either 10Mbps or 100Mbps. The core logic of
the ACD82124, implemented with patent pending
BASIQ (Bandwidth Assured Switching with Intelligent
Queuing) technology , can simultaneously process 24
asynchronous 10/100Mbps port traffic. The Queue
Manager inside the ACD82124 provides the capability
of routing traffic with the same order of sequence,
without any packet loss.

A complete 24 port 10/100 switch can be built with the
use of the ACD82124, 10/100 PHY and ASRAM. The
MAC addresses can be expanded from the built-in 2K
to 11K by the use of ACD’s external ARL chip
(ACD80800 Address Resolution Logic). Advanced net­work management features can be supported with the
use of ACD’s MIB (ACD80900 Management Informa­tion Base) chip.

• 24 ports 10/100 auto-sensing with MII interface

• Half-duplex operation, with optional full-duplex con-

figuration by combining 2 adjacent ports

• 2.4 Gbps aggregated throughput

• True non-blocking switch architecture

• Flexible port configuration (up to 12 full duplex 10/

100 ports, up to 24 half duplex 10/100 ports)

• Built-in storage of 2,000 MAC address

• Automatic source address learning

• Zero-Packet Loss back-pressure flow control

• Store-and-forward switch mode

• Port based V-LAN support

• UART type CPU management interface

• Supports up to 11K MAC addresses with the

ACD80800

• RMON and SNMP support with ACD80900

• Status LEDs: Link, Speed, Full Duplex, Transmit,

Receive, Collision and Frame Error

• Reversible MII option for CPU and expansion port
interface

• Wire speed forwarding rate

• 576 pin BGA package

• 3.3V power supply , 3.3V I/O with 5V tolerance

Data Sheet: ACD82124

3. SYSTEM BLOCK DIAGRAM

PMD/

PHY-0

PMD/

PHY-1

PMD/

PHY-22

PMD/

PHY-23

FIFO

MAC-0

FIFO

FIFO

MAC-1

FIFO

FIFO

MAC-22

FIFO

FIFO

MAC-23

FIFO

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

MX

DMX

ACD82124

Lookup Engine

(2K MAC Addr.)

ARL Interface

INTRODUCTORY

LED ControllerBIST Handler

Queue Manager

SRAM Interface MIB Interface

ARL

ACD80800

(11K MAC Addr.)

(optional)

SRAM

MIB

ACD80900

(optional)

3

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4. SYSTEM DESCRIPTION

The ACD82124 is a single chip implementation of a
24-port Fast Ethernet switch. Together with external
ASRAM and transceiver devices, it can be used to
build a complete desktop class Fast Ethernet switch.
Each individual port can be either auto-sensed or manu­ally selected to run at 10 Mbps or 100 Mbps speed
rate, under Half Duplex mode.

The ACD82124 Ethernet switch contains three major
functional blocks: the Media Access Controller (MAC),
the Queue Manager, and the Lookup Engine.

There are 24 independent MACs within the ACD82124.
The MAC controls the receiving, transmitting, and de­ferring process of each individual port, in accordance
to IEEE 802.3 and 802.3u standard. The MAC logic
also provides framing, FCS checking, error handling,
status indication and back-pressure flow control func­tions. Each MAC interfaces with an external transceiver
through standard MII interface.

The device utilizes ACD’s proprietary BASIQ (Band­width Assured Switching with Intelligent Queuing) tech­nology. It is a technology to enforce the first-in-first­out rule of Ethernet Bridge-type devices in a very effi­cient way. The technology enables a true non-block­ing frame switching operation at wire speed for a high
throughput and high port density Ethernet switch.

The on-chip 2,000 MAC addresses Lookup Engine
maps each destination address into a destination port.
Each port’s MAC address is automatically learned by
the Lookup Engine when it receives a frame with no
error. Therefore, the ACD82124 alone can be used to
build a desktop class Fast Ethernet switch without any
additional switching devices.

The MAC address space can be expanded from 2,000
to 8,000 per system by using the ACD80800. The
ACD82124 has a proprietary ARL interface that allows
direct connection with ACD80800. System designers
can also use this ARL interface to implement a ven­dor-specific address resolution algorithm.

The ACD82124 provides management support through
its MIB (Management Information Base) interface. The
MIB interface can be used to monitor all traffic activi­ties of the switch system. ACD’s supporting chip (the
ACD80900) provides a full set of statistical counters to
support both SNMP and RMON network management.
The MIB interface can also be used by system de­signers to implement vendor-specific network manage­ment functionality .

Among the 24 MII interfaces, 10 of them can be con­figured as reversed MII, to connect directly with stand­alone MAC controller devices. A MAC in the ACD82124
can be viewed logically as a PHY device if it is config­ured as a reversed MII interface. The reversed MII is
intended for a CPU network interface, or expansion
port interface.

A system CPU can access various registers inside
the ACD82124 through a serial CPU management
interface. The CPU can configure the switch by
writing into the appropriate registers, or retrieve the
status of the switch by reading the corresponding
registers. The CPU can also access the registers of
external transceiver (PHY) devices through the CPU
management interface.

Data Sheet: ACD82124

INTRODUCTORY

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4

5. FUNCTIONAL DESCRIPTION

Start of Frame Detection

The MAC controller performs transmit, receive, and
defer functions, in accordance to IEEE 802.3 and

802.3u standard specification. The MAC logic also
handles frame detection, frame generation, error de­tection, error handling, status indication and flow con­trol functions.

Frame Format
The ACD82124 assumes that the received data packet

will have the following format:

Preamble SFD DA SA Type/Len Data FCS

Where,

•

Preamble

any length with nibble alignment.

•

SFD

tet pattern of 1010101 1.

•

DA

fies the MAC address of the destined DTE. If the
first bit of DA is 1, the ACD82124 will treat the
frame as a broadcast/multicast frame and will for­ward the frame to all ports within the source port’s
VLAN except the source port itself or BPDU ad­dress.

is a repetitive pattern of ‘1010….’ of

(Start Frame Delimiter) is defined as an oc-

(Destination Address) is a 48-bit field that speci-

When a port’s MAC is idle, assertion of the RXDV in
the MII interface will cause the port to go into the re­ceive state. The MII presents the received data in 4-bit
nibbles that are synchronous to the receive clock
(25Mhz or 2.5MHz). The ACD82124 will convert this
data into a serial bit stream, and attempt to detect the
occurrence of the SFD (10101011) pattern. All data
prior to the detection of SFD are discarded. Once SFD
is detected, the following frame data are forwarded
and stored in the buffer of the switch.

Frame Reception
Under normal operating conditions, the ACD82124

expects a received frame to have a minimum inter frame
gap (IFG). The minimum IFG required by the device is
80 BT (Bit Time).

In the event the ACD82124 receives a packet with IFG
less than 80BT , the ACD82124 does not guarantee to
be able to receive the frame. The packet will be dropped
if the ACD82124 cannot receive the frame.

The device will check all received frames for errors
such as symbol error, FCS error, short event, runt,
long event, jabber etc. Frames with any kind of error
will not be forwarded to any port.

Preamble Bit Processing

Data Sheet: ACD82124

INTRODUCTORY

•

SA

(Source Address) is a 48-bit field that con­tains the MAC address of the source DTE that is
transmitting the frame to the ACD82124. After a
frame is received with no error, the SA is learned
as the port’s MAC address.

•

Type/Len

type (DIX Ethernet frame) or length (IEEE 802.3
frame) of the frame. The ACD82124 does not pro­cess this information.

•

Data

Ethernet Packet. The ACD82124 does not pro­cess any of the data information in this field.

•

FCS

a CRC (Cyclic Redundancy Check) value based
on the destination address, the source address,
the type/length and the data field. The ACD82124
will verify the FCS field for each frame. The pro­cedure of computing FCS is described in section
of “FCS Calculation.”

field is a 2-byte field that specifies the

is the encapsulated information within the

(Frame Check Sequence) is a 32-bit field of

The preamble bit in the header of each frame will be
used to synchronize the MAC logic with the incoming
bit stream. The minimum length of the preamble is 0
bits and there is no limitation on the maximum length of
preamble. After the receive data valid signal RXDV is
asserted by the external PHY device, the port will wait
for the occurrence of the SFD pattern (1010101 1) and
then start a frame receiving process.

Source Address and Destination Address
After a frame is received by the ACD82124, the em-

bedded destination address and source address are
retrieved. The destination address is passed to the
lookup table to find the destination port. The source
address is automatically stored into the address lookup
table. For applications that use an external ARL, the
ACD82124 will disable the internal lookup table and
pass the DA and SA to the external ARL for address
lookup and learning.

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5

A port’s MAC address register is cleared on power­up, hardware reset, or when the port enters into Link
Fail state. If the SA aging option is enabled

16 bit 4)

reappear within five minutes.
During the receive process, the Lookup Engine will

attempt to match the destination address with the ad­dresses stored in the address table. If a match is found,
a link between the source port and the destination port
is established. If an external ARL is used, the ACD82124
indicates the presence of a 48-bit DA through the sta­tus line of the ARL interface. The external ARL will use
the value of DA for address comparison and return a
result of the lookup to the ACD82124.

Frame Data

, the learned SA will be cleared if it does not

(Register-

is less then 64 bytes, the frame is flagged with runt
error.

In order to support an application where extra byte
length is required, an Extra-Long-Frame option is pro­vided. When the Extra long frame option is enabled

(T able 12: CFG7)

are marked with a long event error. Frame length is
measured from the first byte of DA to the last byte of
FCS.

Frame Filtering
Frames with any kind of error will be filtered. Types of

error include code error (indicated by assertion of
RXER signal), FCS error, alignment error , short event,
runt, and long event.

, only frames longer than 1530 bytes

Data Sheet: ACD82124

Frame data are transparent to the ACD82124. The
ACD82124 will forward the data to the destination
port(s) without interpreting the content of the frame
data field.

FCS Calculation
Each port of the ACD82124 has CRC checking logic

to verify if the received frame has a correct FCS value.
A wrong FCS value is an indication of a fragmented
frame or a frame with frame bit error. The method of
calculating the CRC value is using the following poly­nomial,

G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x

10

+ x

as a divider to divide the bit sequence of the incoming
frame, beginning with the first bit of the destination
address field, to the end of the data field. The result of
the calculation, which is the residue after the polyno­mial division, is the value of the frame check sequence.
This value should be equal to the FCS field appended
at the end of the frame. If the value does not match the
FCS field of the frame, the Frame Bit Error LED of the
port will be turned on once and the packet will be
dropped.

Frame Length
During the receiving process, the MAC will monitor the

length of the received frame. Legal Ethernet frames
should have a length of not less than 64 bytes and no
more than 1518 bytes. If the carrier sense signal of a
frame is asserted for less than 76 BT, the frame is
flagged with short event error. If the length of a frame

+ x8 + x7 + x5 + x4 + x2 + x + 1

11

Any frame heading to its own source port will be fil­tered. If external ARL is used, the ACD82124 will filter
the frame as directed by the external ARL.

If the

Spanning Tree Support

containing DA equal to any reserved Bridge Manage­ment Group Address specified in Table 3.5 of IEEE

802.1d will not be forwarded to any ports, except the
Port-23, which may receive BPDU frames. If span­ning tree support is not enabled, frames with DA equal
to the reserved Group Address for PBDU will be broad­casted to all ports in the same VLAN of the source
port.

Jabber Lockup Protection
If a receiving port is active continuously for more than

50,000 BT, the port is considered to be jabbering. A
jabbering port will automatically be partitioned from the
switch system in order to prevent it from impairing the
performance of the network. The partitioned port will
be re-activated as soon as the offending signal dis­continues.

Excessive Collision
In the event that there are more than 16 consecutive

collision, the ACD82124 will reset the counter to zero
and retransmit the packet. This implementation insures
there is no packet loss even under channel capture
situation. However, ACD82124 has an option to drop
the packet on excessive collision. When this option is
enabled
after 16 consecutive collisions.

(Table 12: CG11)

option is enabled, frames

, the frame will be dropped

INTRODUCTORY

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6

False Carrier Events
If the RXER signal in the MII interface is asserted when

the receive data valid (RXDV) signal is not asserted,
the port is considered to have a false carrier event. If
a port has more than two consecutive false carrier
events, the port will automatically be partitioned from
the switch system. The partitioned port will be re-acti­vated if it has been idling for 33,000 BT or it has re­ceived a valid frame.

Frame Forwarding
If the first bit of the destination address is 0, the frame

is handled as a unicast frame. The destination ad­dress is passed to the Address Resolution Logic, which
returns a destination port number to identify which port
the frame should be forwarded to. If Address Resolu­tion Logic cannot find any match for the destination
address, the frame will be treated as a frame with un­known DA. The frame will be processed in one of two
ways. If the option flood-to-all-port is enabled, the
switch will forward the frame to all ports within the same
VLAN of the source port, except the source port itself.
If the option is not enabled, the frame will be forwarded
to the ‘dumping port’ of the source port VLAN only.
The dumping port is determined by the VLAN ID of the
source port. If the source port belongs to multiple
VLANs, a frame with unknown DA will then be for­warded to multiple dumping ports of the VLANs.

If the first bit of the destination address is a 1, the
frame is handled as a multicast or broadcast frame.
The ACD82124 does not differentiate a multicast packet
from a broadcast packet except the reserved bridge
management group address, as specified in table 3.5
of the IEEE 802.1d standard. The destination ports of
the broadcast frame is all ports within the same VLAN
except the source port itself.

The order of all broadcast frames with respect to the
unicast frames is strictly enforced by the ACD82124.

Frame Transmission

tional 32 BT before starting the transmit process. In
the event that the carrier sense signal is asserted by
the MII during the wait period, the MAC logic will gen­erate a JAM signal to cause a forced collision.

The MAC logic will abort the transmit process if a colli­sion is detected through the assertion of the Col signal
of the MII. Re-transmission of the frame is scheduled
in accordance to IEEE 802.3’s truncated binary expo­nential backoff algorithm. If the transmit process has
encountered 16 consecutive collisions, an excessive
collision error is reported, and the ACD82124 will try
to re-transmit the frame, unless the drop-on-exces­sive-collision option of the port is enabled. It will first
reset the number of collisions to zero and then start
the transmission after 96 BT of interframe gap. If drop­on-excessive-collision is enabled, the ACD82124 will
not try to re-transmit the frame after 16 consecutive
collisions. If a collision is detected after 512 BT of the
transmission, a late collision error will be reported, but
the frame will still be retransmitted after proper backoff
time.

Frame Generation
During a transmit process, frame data is read out from

the memory buffer and is forwarded to the destination
port’s PHY device in nibbles. 7 bytes of preamble sig­nal (10101010) will be generated first followed by the
SFD (1010101 1), and then the frame data and 4 bytes
of FCS are sent out last.

Frame Buffer
All ports of the ACD82124 work in Store-And-Forward

mode so that all ports can support both 10Mbps and
100Mbps data speed. The ACD82124 utilizes a global
memory buffer pool, which is shared by all ports. The
device has a unique architecture that inherits the ad­vantage of both output buffer-based and input buffer­based switches. An output buffer-based switch stores
the received data only once into the memory , and hence
has a short latency. Whereas an input buffer-based
switch typically has more efficient flow control.

Data Sheet: ACD82124

INTRODUCTORY

The ACD82124 transmits all frames in accordance to
IEEE 802.3 standard. The ACD82124 will send the
frames with a guaranteed minimum interframe gap of
96 BT, even if the received frames have an IFG less
than the minimum requirement. Before the transmit
process is started, the MAC logic will check if the chan­nel has been silent for more than 64 BT . Within the 64
BT silent window, the transmission process will defer
on any receiving process. If the channel has been
silent for more than 64 BT, the MAC will wait an addi-

Flow Control
Under half duplex mode of operation, when the switch

cannot handle the receiving of an incoming frame, a
collision is generated by sending a jam pattern to the
sending party to force it to back off and re-transmit the
frame later. Back pressure flow control is applied to a
port when its reserved-buffer is full and no more shared
buffer is available, or when starvation control is active.

7

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This process is used to ensure that there are no
dropped frames.
disabled by setting the corresponding bit of the

Backpressure flow control

can be

regis-

ter-21.

VLAN Support

(register 23 & 24)

802.3 standard. The ACD82124 will direct the follow­ing frames to the dumping port:

• frame with unicast destination address that does
not match with any port’s source address within
the VLAN of the source port

• frame with broadcast/multicast destination address*

The ACD82124 can support up to 4 port-based secu­rity VLANs. Each port of the ACD82124 can be as­signed up to four VLAN. On power up, every port is
assigned to VLAN-0 as default VLAN. Frames from
the source port will only be forwarded to destination
ports within the same VLAN domain. A broadcast/
multicast frame will be forwarded to all ports within the
VLAN(s) of the source port. A unicast frame will be
forwarded to the destination port only if the destination
port is in the same VLAN as the source port. Other­wise, the frame will be treated as a frame with un­known DA. Each VLAN can be assigned with a dedi­cated dumping port. Multiple VLANs can also share a
dumping port. Unicast frames with unknown destina­tion addresses will be forwarded to the dumping port
of the source port VLAN.

Security VLAN can be disabled by setting the corre­sponding bit in the system configuration register (bit 8
of

Register 16

VLAN becomes a leaky VLAN and is equivalent to a
broadcast domain. Four dumping ports of four differ­ent virtual VLAN can be grouped together to form a fat
pipe uplink (For example, if port 0&1, port 2&3, port
3&4, port 5&6 are combined to form 4 full duplex ports
with 200Mbps per port throughput, these 4 full duplex
ports can be grouped to form an 800 Mbps uplink port).
When multiple dumping ports are grouped as a single
pipe, each port has to be assigned to one and only
one VLAN. A unicast frame with a matched DA will be
forwarded to any destination, even if the VLAN ID is
different. All unmatched DA packets will be forwarded
to the designated dumping port of the source port
VLAN. The broadcast and multicast packets will only
be forwarded to the ports in the same VLAN of the
source port. Therefore, a 200 to 800 Mbps pipe can
be established by carefully grouping the dumping ports,
and connects directly with the segmentation switches.

Dumping Port
Each VLAN can be assigned with a dedicated dump-

ing port. Multiple VLANs can share a dumping port.
Each dumping port can be used for up-link connec­tion or for DTE connection. That is, the dumping port
can be used to connect the switch with a computer
repeater hub, a workgroup switch, a router, or any
type of interconnecting device compliant with the IEEE

). When security VLAN is disabled, each

* See

Spanning T ree Support

If the device is configured to work under Flood-to-All­Port mode
be forwarded to all the ports in the VLAN(s) of the
source port except the source port itself.

Mode of Operation
By default, all ports of the ACD82124 work in half du-

plex mode. A full-duplex port can be configured by
combining two half-duplex ports. In this case, the op­eration mode of the port is determined by the port’s
PHY device through auto-negotiation. The mode of a
port can also be assigned by the duplex mode indica­tion/assignment register

Spanning Tree Support
The ACD82124 supports Spanning Tree protocol.

When Spanning Tree Support is enabled

bit 1)

equal to the reserved Bridge Management Group Ad­dress for BPDU will be forwarded to the port specified
by the CPU. Frames from all other ports with a DA
equal to the Reserved Group Address for BPDU will be
forwarded to the CPU port if the port is in the same
VLAN of the CPU port. Port 23 is designed as the
default CPU port. When Spanning Tree Support is dis­abled, all reserved group addresses for Bridge Man­agement is treated as broadcast address.

Every port of the ACD82124 can be set to block-and­listen mode through the CPU interface. In this mode,
incoming frames with DA equal to the reserved Group
Address for BPDU will be forwarded to the CPU port.
Incoming frames with all other DA value will be dropped.
Outgoing frames with DA value equal to the Group Ad­dress for BPDU will be forwarded to the attached PHY
device; all other outgoing frames will be filtered.

Queue Management
Each port of the ACD82124 has its own individual

transmission queue. All frames coming into the
ACD82124 are stored into the shared memory buffer,

(Register 25, bit 8)

, frames listed above will

(Register 27)

.

(Register 16

, frames from the CPU port (port 23) having a DA

Data Sheet: ACD82124

INTRODUCTORY

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8

and are lined up in the transmission queues of the
corresponding destination port. The order of all frames,
unicast or broadcast, is strictly enforced by the
ACD82124. The ACD82124 is designed with a non­blocking switching architecture. It is capable of achiev­ing wire-speed frame forwarding rate and handling
maximum traffic load.

MII Interface
The MAC of each port of the ACD82124 interfaces

with the port’s PHY device through the standard MII
interface. For reception, the received data (RXD) can
be sampled by the rising edge (default) or the falling
edge of the receive clock (RXCLK). Assertion of the
receive data valid (RXDV) signal will cause the MAC to
look for start of Frame Delimiter (SFD). For transmis­sion, the transmit data enable (TXEN) signal is as­serted when the first preamble nibble is sent on the
transmit data (TXD) lines. The transmit data are clocked
out by the falling edge of the transmit clock (TXCLK).

The ACD82124 supports PHY device management
through the serial MDIO and MDC signal lines. The
ACD82124 can continuously poll the status of the PHY
devices through the serial management interface, with­out CPU intervention. The ACD82124 will also config­ures the PHY capability field to ensure proper opera­tion of the link. The ACD82124 also enables the CPU
to access any registers in the PHY devices through
the CPU interface.

Reversed MII Interface

CPU Interface
The ACD82124 does not require a microprocessor for

operation. Initialization and most configurations can
be done with the use of external hardware pins. How­ever, the ACD82124 provides a CPU interface for a
microprocessor to access some of its control regis­ters and status registers. The microprocessor can send
a read command to retrieve the status of the switch, or
send a write command to configure the switch through
a serial interface. This interface is a commonly used
UART type interface. The CPU interface can also be
used to access the registers inside each PHY device
connected with the ACD82124.

ARL Interface
The ACD82124 has a built-in ARL that can store up to

2,000 MAC addresses. It is actually a subset of the full
ACD80800 ARL IC. For detailed description, please
refer to the ACD80800 Data Sheet. The UARTID for
this built-in ARL is shared with the ACD82124 (CFG16
& 17).

The ACD82124 also provides an ARL interface

12: CFG9)

Through the ARL interface, the external ARL
(ACD80800) device can tap the value of DA out from
the data bus in the ASRAM interface, and execute a
lookup process to map the value of DA into a port
number. The external ARL device also learns the SA
values embedded in the received frames via the ARL
interface. The value of SA is used to build up the ad­dress lookup table.

for supporting additional MAC addresses.

(T able

Data Sheet: ACD82124

INTRODUCTORY

Ten ports of the ACD82124 can be configured as re­versed MII interface. Reversed MII behaves as a PHY
MII, that the TXCLK, COL, RXD<3:0>, RXCLK, RXDV ,
CRS signals (names specified by IEEE 802.3u) be­come output signals of the ACD82124, and the TXER,
TXD<3:0>, TXEN, RXER, signals (names specified by
IEEE 802.3u) become input signals of the ACD82124.
Reversed MII interface enables an external MAC de­vice to be connected directly with the ACD82124.

ASRAM Interface
The ACD82124 requires the use of asynchronous

SRAM as a memory buffer. Each read or write cycle
takes up to 20 ns. An ASRAM chip with access speed
at 12 ns or faster should be used. The ASRAM inter­face contains a 52-bit data bus, a 17-bit address bus
and 4 chip-select signals.

MIB Interface
Traffic activities on all ports of the ACD82124 can be

monitored through the MIB interface. Through the MIB
interface, a MIB device can view what the source port
is receiving, or what the destination port is transmit­ting. Therefore, the MIB device can maintain a record
of traffic statistics for each port to support network
management. Since all received data are stored into
the memory buffer, and all transmitted data are re­trieved from the memory buffer , the data of the activi­ties can also be captured from the data bus of ASRAM
interface. The status of each data transaction between
the ACD82124 and the ASRAM is displayed by some
dedicated status signal pins of the ACD82124.

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9

LED Interface
The ACD82124 provides a wide variety of LED indica-

tors for simple system management. The update of the
LED is completely autonomous and merely requires
low speed TTL or CMOS devices as LED drivers. The
status display is designed to be flexible to allow the
system designer to choose those indicators appropri­ate for the specification of the equipment.

There are two LED control signals, LEDVLD0 and
LEDVLD1, used to indicate the start and end of the
LED data signal. LEDCLK signal is a 2.5MHz clock
signal. The rising edge of LEDCLK should be used to
latch the LED data signal into the LED driver circuitry .

The LED data signals contain Lnk, Xmt, Rcv , Col, Err ,
Adr, Fdx and Spd, which represent Link status, T rans­mit status, Receive status, Collision indication, Frame
error indication, Port Address learning status, Full du­plex operation and Operational Speed status respec­tively. These status signals are sent out sequentially
from port 23 to port 0, once every 50ms. For details
about the timing diagrams of the LED signals, refer to
the chapter of “Timing Description ”

Data Sheet: ACD82124

Life Pulse
The ACD82124 continuously sends out life pulses to

the WCHDOG pin when it is operating properly . In a
catastrophic event, the ACD82124 will not send the
life pulse to cause the external watchdog circuitry to
time-up and reset the switch system.

INTRODUCTORY

10

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

6. INTERFACE DESCRIPTION

MII Interface (MII)
The ACD82124 communicates with the external 10/

100 Ethernet transceivers through standard MII inter­face. The signals of MII interface are described in

table-6.1

:

Table-6. 1: MII Interface Signals

Name Type De scription

PxCRS I Carrier sense
PxRXDV I Receive data valid
PxRXCLK I Receive clock (25/2.5 M Hz)
PxRXERR I Receive error
PxRXD0 I Receive data bit 0
PxRXD1 I Receive data bit 1
PxRXD2 I Receive data bit 2
PxRXD3 I Receive data bit 3
PxCOL I Collision indication
PxTXEN O Transmit data valid
PxTXCLK I Transmit clock (25/2.5 MHz)
PxTXD0 O Transmit data bit 0
PxTXD1 O Transmit data bit 1
PxTXD2 O Transmit data bit 2
PxTXD3 O Transmit data bit 3

Table-6. 2: Reversed MII Inter face Signals

Name Type De scription

PxCRSR O Carri er sense
PxRXDVR I Transmit data valid
PxRXCLKR O Transmit clock (25/2.5 MHz)
PxRXERR I Not-Ready (Input)
PxRXD0R I Transmit data bit 0
PxRXD1R I Transmit data bit 1
PxRXD2R I Transmit data bit 2
PxRXD3R I Transmit data bit 3

PxCOLR O
PxTXENR O Receive data valid

PxTXCLKR O Receive clock (25/2.5 MHz)
PxTXD0R O Receive data bit 0
PxTXD1R O Receive data bit 1
PxTXD2R O Receive data bit 2
PxTXD3R O Receive data bit 3

Collision I ndication/
Not-Ready (Output)

For reversed MII interface, signal PxRXDVR, and
PxRXD0R through PxRXD3R are clocked out by the
falling edge of PxRXCLKR. Signal PxTXENR, and
PxTXD0R through PxTXD3R can be sampled by the
falling edge or rising edge of PxTXCLKR, depends on
the setting of bit 9 of

Register 16

. The timing behavior

is described in the chapter of “Timing Description.“

Data Sheet: ACD82124

For MII interface, signal PxRXDV, PxRXER and
PxRXD0 through PxRXD3 are sampled by the rising
edge of PxRXCLK. Signal PxTXEN, and PxTXD0
through PxTXD3 are clocked out by the falling edge of
PxTXCLK. The detailed timing requirement is described
in the chapter of “Timing Description”

PHY Management Interface
All control and status registers of the PHY devices are

accessible through the PHY management interface.
The interface consists of two signals: MDC and MDIO,
which are described in

Table-6.3

.

Ports 0,1, 2, 3, 4, 5, 6, 7, 22 and 23 can be config­ured as reversed MII ports (
MII Enable register). These ports, when configured as
“normal” MII, have the same characteristics as all other
MII ports. However, when configured as reversed MII

Register 28

, the Reversed

Table-6. 3: PHY Management Interface Signals

Name Type D escription

M DC O PH Y management clock (1.25MHz)
M DIO I/O PHY management data

interface, they will behave logically like a PHY device,
and can interface directly with a MAC device. The
signal of reversed MII interface are described by

6.2

:

Note: *

Not-Ready (output)

Collision Indication

for full duplex mode.

for half-duplex mode.

table-

Frames transmitted on MDIO has the following format
(

Table-6.4

):

Table-6 .4: MDIO For mat

Oper ation PRE ST OP PHY-ID REG-AD TA DATA IDLE

Wr ite 1…1 01 01 aaaaa rrrrr 10 d…d Z
Read 1…1 01 1 0 a aa aa rrrrr Z0 d …d Z

INTRODUCTORY

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11

Prior to any transaction, the ACD82124 will output
thirty-two bits of ‘1’ as a preamble signal. After the
preamble, a ‘01’ signal is used to indicate the start of
the frame.

A command sent by CPU comes through the CPUDI
line. The command consists of 9 octets. Command
frames transmitted on CPUDI have the following for­mat (

T able-6.6

):

For a write operation, the device will send a ‘01’ to
signal a write operation. Following the ‘01’ write signal
will be the 5 bit ID address of the PHY device and the
5 bit register address. A ‘10’ turn around signal is then
followed. After the turn around, the 16 bit of data will
be written into the register. After the completion of the
write transaction, the line will be left in a high imped­ance state.

For a read operation, the ACD82124 will output a ‘10’
to indicate read operation after the start of frame indi­cator. Following the ‘10’ read signal will be the 5-bit ID
address of the PHY device and the 5-bit register ad­dress. Then, the ACD82124 will cease driving the MDIO
line, and wait for one BT. During this time, the MDIO
should be in a high impedance state. The ACD82124
will then synchronize with the next bit of ‘0’ driven by
the PHY device, and continue on to read 16 bits of
data from the PHY device.

The system designer should set the ID of the PHY
devices as ‘1’ for port-0, ‘2’ for port-1, … and ‘24’ for
port-23. The detail timing requirement on PHY man­agement signals are described in the chapter of “Tim­ing Description.”

Table-6. 6: CPU Command Format

Ope r ation Command Register Inde x Data Che cksum

W r it e 0010XX11 8-bit 8-bit 24-bit 8-bit
Read 0010XX01 8-bit 8-bit 24- bit 8-bit

The byte order of data in all fields follows the big-endian
convention, i.e. most significant octet first. The bit or­der is least significant order first. The Command octet
specifies the type of the operation. Bit 2 and bit 3 of
the command octet is used to specify the device ID of
the chip. They are set by bit 16 and bit 17 of the

ister 25

fies the type of the register. The index octet specifies
the ID of the register in a register array. For write
operation, the Data field is a 4-octet value to specify
what to write into the register. For read operation, the
Data field is a 4-octet 0 as padded data. The checksum
value is an 8-bit value of exclusive-OR of all octets in
the frame, starting from the Command octet.

The ACD82124 will respond to each valid command
received by sending a response frame through the
CPUDO line. The response frames have the following
format (

at power on strobing. The address octet speci-

T able-6.7

):

Reg-

Data Sheet: ACD82124

INTRODUCTORY

CPU Interface
The ACD82124 includes a CPU interface to enable an

external CPU to access the internal registers of the
ACD82124. The protocol used in the CPU is the asyn­chronous serial signal (UART). The baud rate can be
from 1200 bps to 76800 bps. The ACD82124 auto­matically detects the baud rate for each command,
and returns the result at the same baud rate. The sig­nals in CPU interface are described in

Table-6.5

.

Table-6. 5: CPU Interface Signals

Name Type De scription

CPUDI I CPU data input
CPUDO O CPU data output
CPUIRQ O CPU interrupt request

Table-6. 7: Response Format

Re sponse C ommand Re sult Data Checksum

W r it e 00100011 8- bit 24-bit 8-bit
Read 00100001 8-bit 24-bit 8-bit

The command octet specifies the type of the response.
The result octet specifies the result of the execution.

The Result field in a response frame is defined as:

• 00 for no error

• 01 for Checksum

• 10 for address incorrect

• 1 1 for MDIO waiting time-out

For response to a read operation, the Data field is a 3­octet value to indicate the content of the register. For
response to a write operation, the Data field is 24 bits
of 0. The checksum value is an 8-bit value of exclu­sive-OR of all octets in the response frame, starting
from the Command octet.

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12

CPUIRQ is used to inform the CPU of some special
status has been encountered by the ACD82124, like
port partition, fatal system error, etc. By clearing the
appropriate bit in the interrupt mask register, one can
stop the specific source from generating an interrupt
request. Reading the interrupt source register retrieves
the source of the interrupt and clears the interrupt
source register.

ASRAM Interface
All received frames are stored into the shared memory

buffer through the ASRAM interface. When the desti­nation port is ready to transmit the frame, data is read
from the shared memory buffer through the ASRAM
interface. The signals in ASRAM interface are de­scribed in

Table-6.8

.

Table-6. 8: ASRAM Interface

Name T ype De scription

DATA0-DATA51 I/O memory data bus
ADDR0-ADDR16 O m emory address bus
nOE O output enable, low active
nWE O write enable, low active
nCS0 - nCS3 O chip select signals, low active.

Data is written into the ASRAM or read from the ASRAM
in 52-bit wide words. The data is a 48-bit wide value
and the control is a 4 bit-wide value. ADDR specifies
the address of the word, and DA TA contains the con­tent of the word. Bit 0 ~ 47 of DATA bus are used to
pass 48-bit frame data. Bit 48 are used to indicate the
start and end of a frame. Bit 49 ~ 51 are used to
indicate the length of actual data presented on DA T A0
~ DA TA47.

nOE and nWE are used to control the timing of read
or write operation respectively. nCSx selects the
ASRAM chip corresponding to the word address. The
timing requirement on ASRAM access is described in
the chapter-9 “Timing Description”.

ARL Interface
ARL interface provides a communication path between

the ACD82124 and an ARL device, which can provide
up to 8K of additional address lookup function. As the
ACD82124 receives a frame, the destination address
and source address of the frame are displayed on the
ARLDO data lines for the external ARL device. After
the external ARL finds the corresponding destination
port, it returns the result through the ARLDIx lines to

the ACD82124. The timing requirement on ARL sig­nals is described in

Table-6.9

shows the associated signals in ARL inter-

Chapter-9

“Timing Description.”

face.

Table-6. 9: ARL Interface Signals

Name Type Description

ARLDO0-RLDO51 O ARL data output, shared with

DATA 0 - DATA 5 1

ARLDIR1-ARLDIR0 O ARL data direction indicator

00 for idle
01 for receive
10 for transmit

11 for control
ARLSYNC O ARL port synchronization
ARLSTAT0-

ARLSTAT3
ARLCLK O ARL clock

ARLDI0 - ARLDI3 I ARL data input
ARLDIV I ARL input data valid

O ARL data state indicator

The data signal is tapped from the DA T A bus of ASRAM
interface. Since all data of the received frames will be
written into the shared memory through the DA T A bus,
the bus can be used to monitor occurrences of DA
and SA values, indicated by the status signal of
ARLST A T . Therefore, ARLD0 through ARLD51 are the
same signals of DA T A0 through DA T A47.

ARLDIR1 and ARLDIR0 are used to indicate the di­rection of data on the ARLDO bus:

• 00: Idle

• 01: for receiving data

• 10: for transmitting data

• 1 1: Header

ARLSYNC is used to indicate port 0 is driving the DA TA
bus. Since the bus is pre-allocated in time division
multiplexing manner, the ARL device can determine
which port is driving the DA TA bus.

ARLSTAT are used to indicate the status of the data
shown on the first 48 bits of DATA bus. The 4-bit status
is defined as:

• 0000 - Idle

• 0001 - First word (DA)

• 0010 - Second word (SA)

• 001 1 - Third through last word

• 0100 - Filter Event

• 0101 - Drop Event

• 0110 - Jabber

• 01 11 - False Carrier/Deferred T ransmission*

• 1000 - Alignment error/Single Collision*

Data Sheet: ACD82124

INTRODUCTORY

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13

Table-11: LED Interface Signals

Name Type Description Signal Group 1 Signal Group 2

LEDVLD0 O LED signal valid #0 1 0
LEDVLD1 O LED signal valid #1 0 1
nLEDCLK O 2.5 M Hz LED clock - ­nLED0 O Dual purpose indicator address learning status frame error indicator
nLED1 O Dual purpose indicator full duplex indication collision indication
nLED2 O Dual purpose indicator port speed (1=10Mbps,0=100Mbps) receiving activity
nLED3 O Dual purpose indicator Link status transmit activity

Data Sheet: ACD82124

• 1001 - Flow Control/Multiple Collision*

• 1010 - Short Event/Excessive Collision

• 101 1 - Runt/Late Collision

• 1100 - Symbol Error

• 1101 - FCS Error

• 1 1 10 - Long Event

• 1111 - Reserved

*

Note: error type depends on whether the port is re-

*

*

ceiving or transmitting.

ARLDIx is used to receive the lookup result from the
external ARL. Result is returned by external ARL de­vice through the ARLDIx lines. Returned data is sampled
by the rising edge of ARLCLK. The ARL result has the
following format:

SI D RSLT DID

Where

• SID is a 5-bit ID of the source port (0 - 23)

• RSL T is a 2-bit result, defined as:

00 - reserved
01 - matched
10 - not matched
11 - forced discard

• DID is a 5-bit ID of the destination port (0 - 23)

LED Interface
The signals in the LED interface is described in

6.10

:

The status of each port is displayed on the LED inter­face for every 50ms. LEDVLD0 and LEDVLD1 are
used to indicate the start and end of the LED data.
LED data is clocked out by the falling edge of LEDCLK,
and should be sampled by the rising edge of LEDCLK.
LED data of port 23 are clocked out first, followed by
port 22 down to port 0. All LED signals are low active.

table-

INTRODUCTORY

The start of each ARL result is indicated by assertion
of ARLDIV signal.

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14

Configuration Interface

Other Interface (

T able-6.12

)

There are 20 pins whose pull-up or pull-down state will
be used as Power-On-Strobing configuration data

ister 25, & CFG0 - CFG19)

to specify various working

(Reg-

modes of the ACD82124. The CFG pins are shared
with other functional pins of the ACD82124. The pull­high or pull-low status of the CFG pins are used to
indicate specific configuration settings, described in

Table-6.11

vide more details about the

ter

.

. The register description section will pro-

POS Configuration regis-

Table-6.11: Configuration Interface

Pin Nam e Register # Bit # Setting

P7TXD0 0
P7TXD1 1

P7TXD2 2
P7TXD3 3
P6TXD0 4
P6TXD1 5
P6TXD2 6
P6TXD3 7

LEDCLK 8
LEDVLD0 9
LEDVLD1 10

nLED3 11
nLED2 12
nLED1 13

nLED0 14
P5TXD0 15
P5TXD1 16
P5TXD2 17
P5TXD3 18
P2TxD0 0
P2TxD1 1
P2TxD2 2
P2TxD3 3
P3TxD0 4
P3TxD1 5
P3TxD2 6
P3TxD3 7
P4TxD0 8
P4TxD1 9
P4TxD2 10
P4TxD3 11
P0TXD0 0
P0TXD1 1
P0TXD2 2
P0TXD3 3
P1TXD0 4
P1TXD1 5
P1TXD2 6
P1TXD3 7

P23TXD0R 0
P23TXD1R 1
P23TXD2R 2
P23TXD3R 3

25

26

30

20, inside the

Internal

ARL

See Table-

7.25

See Table-

7.26

See Table-

7.30

See Appendix-

A1

0

Table-6. 12: Other Interface

Name Type D e script ion

CLK50 I 50 MHz clock input
nRESET I hardware reset
WCHDOG O watch dog life pulse signal
VDD - 3.3 V power
VSS - ground

CLK50 should come from a clock oscillator, with 0.01%
(100 ppm) accuracy.

Assertion of the nRESET pin will cause the ACD82124
to go through the power-up initialization process. All
registers are set to their default value after reset.

When the ACD82124 is working properly , it will gener­ate pulses from the WCHDOG pin continuously. It is
used as a safeguard, so that in case something unex­pected happens, the external watchdog circuit will re­set the switch system.

VDD is 3.3V power supply . VSS is power ground.

Data Sheet: ACD82124

INTRODUCTORY

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15

7. REGISTER DESCRIPTION

Registers in the ACD82124 are used to define the op­eration mode of various function modules of the switch
controller and the peripheral devices. Default values at
power-on are defined by the factory. The manage­ment CPU (optional) can read the content of all regis­ters and modify some of the registers to change the
operation mode. T able-7.0 lists all the registers inside
the switch controller.

Table-7. 1: INTSRC Register

Bit De script ion D efault

0 System initialization completed 0
1 System error occurred 0
2 Port partition occurred 0
3 ARL Interrupt 0
4 Reserved 0
5 Reserved 0
6 Reserved 0
7 Reserved 0

Data Sheet: ACD82124

INTSRC register (register 1)
The INTSRC register indicates the source of the inter-

rupt request. Before the CPU starts to respond to an
interrupt request, it should read this register to find out
the interrupt source. This register is automatically
cleared after each read. Table-7.1 lists all the bits of
this register.

SYSERR register (register 2)
The SYSERR register indicates the presence of sys-

T able-7.2 lists all kind of system error.

Table-7.2: SYSERR Register

Bit Description Default

0 BIST failure indication 0
1 Reserved 0
2 Reserved 0
3 Reserved 0
4 Reserved 0
5 Reserved 0
6 Reserved 0
7 Reserved 0
8 Reserved 0

Table-7.0: R egister List

Address N ame Type Size Depth D escription

tem errors. It is automatically cleared after each read.

0
1 I NTSRC R 8 Bit 1 Interrupt Source
2 SY SERR R 24 Bit 1 System Error
3 PA R R 24 Bit 1 Port Partiti on Indica t ion
4 PMERR R 24 Bit 1 PH Y Management Error
5 ACT R 24 Bi t 1 Port A vtivity

6-15

16 SYSCFG R/W 16 Bit 1 System Configuration
17 INT MSK R/W 8 Bit 1 Interrupt Mask
18 SPEED R/W 24 Bit 1 Port Speed
19 LINK R/W 24 Bit 1 Port Link
20 nFWD R/W 24 Bit 1 Port Forward Disable
21 nBP R/W 24 Bit 1 Port Back Pressure Disable
22 nPORT R/W 24 Bit 1 Port Disable
23 PVID R/W 4 Bit 24 Port VLAN ID
24 VPID R/W 5 Bit 4 VLAN Dumping Port
25 POSCFG R/W 19 Bit 1 Power-On-Strobe Configuration
26 nPAUSE R/W 24 Bit 1 Port Pause Frame Disable
27 DPLX R/W 24 Bit 1 Port Duplex Mode
28 RVSMII R/W 5 Bit 1 Reversed MII Selection
29 nPM R/W 24 Bit 1 Port PHY Management Disable
30 ERRMSK R/W 8 Bit 1 Error Mask
31 CLKADJ R/W 4 Bit 1 ARL Clock Delay Adjustment

32-6 3 PHYREG R/W 16 Bit 24 Registers in PH Y de vice, (REG # - 32)

Reserved

Reserved

INTRODUCTORY

16

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PAR register (register 3)

PMERR register (register 4)

The PAR register indicates the presence of the parti­tioned ports and the port ID. A port can be automati­cally partitioned if there is a consecutive false carrier
event, an excessive collision or a jabber. This register
is automatically cleared after each read. T able-7.3 lists
all the bits of this register.

Table-7. 3: PAR Register

Bit De fault

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Description

0 - Port 0 not partitioned.
1 - Port 0 partitioned.
0 - Port 1 not partitioned.
1 - Port 1 partitioned.
0 - Port 2 not partitioned.
1 - Port 2 partitioned.
0 - Port 3 not partitioned.
1 - Port 3 partitioned.
0 - Port 4 not partitioned.
1 - Port 4 partitioned.
0 - Port 5 not partitioned.
1 - Port 5 partitioned.
0 - Port 6 not partitioned.
1 - Port 6 partitioned.
0 - Port 7 not partitioned.
1 - Port 7 partitioned.
0 - Port 8 not partitioned.
1 - Port 8 partitioned.
0 - Port 9 not partitioned.
1 - Port 9 partitioned.
0 - Port 10 not partitioned.
1 - Port 10 partitioned.
0 - Port 11 not partitioned.
1 - Port 11 partitioned.
0 - Port 12 not partitioned.
1 - Port 12 partitioned.
0 - Port 13 not partitioned.
1 - Port 13 partitioned.
0 - Port 14 not partitioned.
1 - Port 14 partitioned.
0 - Port 15 not partitioned.
1 - Port 15 partitioned.
0 - Port 16 not partitioned.
1 - Port 16 partitioned.
0 - Port 17 not partitioned.
1 - Port 17 partitioned.
0 - Port 18 not partitioned.
1 - Port 18 partitioned.
0 - Port 19 not partitioned.
1 - Port 19 partitioned.
0 - Port 20 not partitioned.
1 - Port 20 partitioned.
0 - Port 21 not partitioned.
1 - Port 21 partitioned.
0 - Port 22 not partitioned.
1 - Port 22 partitioned.
0 - Port 23 not partitioned.
1 - Port 23 partitioned.

0

The PMERR register indicates the presence of PHYs
that have failed to respond to the PHY Management
command issued through the MDIO line. This register
is automatically cleared after each read. Table-7.4
describes all the bit of this register.

Table- 7.4: PMERR Register

Bit Default

0 - Port 0 PHY responded

0

1 - Port 0 PHY failed to respond
0 - Port 1 PHY responded

1

1 - Port 1 PHY failed to respond
0 - Port 2 PHY responded

2

1 - Port 2 PHY failed to respond
0 - Port 3 PHY responded

3

1 - Port 3 PHY failed to respond
0 - Port 4 PHY responded

4

1 - Port 4 PHY failed to respond
0 - Port 5 PHY responded

5

1 - Port 5 PHY failed to respond
0 - Port 6 PHY responded

6

1 - Port 6 PHY failed to respond
0 - Port 7 PHY responded

7

1 - Port 7 PHY failed to respond
0 - Port 8 PHY responded

8

1 - Port 8 PHY failed to respond
0 - Port 9 PHY responded

9

1 - Port 9 PHY failed to respond
0 - Port 10 PHY responded

10

1 - Port 10 PHY failed to respond
0 - Port 11 PHY responded

11

1 - Port 11 PHY failed to respond
0 - Port 12 PHY responded

12

1 - Port 12 PHY failed to respond
0 - Port 13 PHY responded

13

1 - Port 13 PHY failed to respond
0 - Port 14 PHY responded

14

1 - Port 14 PHY failed to respond
0 - Port 15 PHY responded

15

1 - Port 15 PHY failed to respond
0 - Port 16 PHY responded

16

1 - Port 16 PHY failed to respond
0 - Port 17 PHY responded

17

1 - Port 17 PHY failed to respond
0 - Port 18 PHY responded

18

1 - Port 18 PHY failed to respond
0 - Port 19 PHY responded

19

1 - Port 19 PHY failed to respond
0 - Port 20 PHY responded

20

1 - Port 20 PHY failed to respond
0 - Port 21 PHY responded

21

1 - Port 21 PHY failed to respond
0 - Port 22 PHY responded

22

1 - Port 22 PHY failed to respond
0 - Port 23 PHY responded

23

1 - Port 23 PHY failed to respond

Description

0

Data Sheet: ACD82124

INTRODUCTORY

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17

ACT register (register 5)

SYSCFG register (register 16)

The ACT register indicates the presence of transmit or
receive activities of each port since the register was
last read. This register is automatically cleared after
each read. Table-7.5 describes all the bits of this reg­ister.

Table-7. 5: ACT Register

Bit De fault

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Description

0 - Port 0 no activity
1 - Port 0 has activity
0 - Port 1 no activity
1 - Port 1 has activity
0 - Port 2 no activity
1 - Port 2 has activity
0 - Port 3 no activity
1 - Port 3 has activity
0 - Port 4 no activity
1 - Port 4 has activity
0 - Port 5 no activity
1 - Port 5 has activity
0 - Port 6 no activity
1 - Port 6 has activity
0 - Port 7 no activity
1 - Port 7 has activity
0 - Port 8 no activity
1 - Port 8 has activity
0 - Port 9 no activity
1 - Port 9 has activity
0 - Port 10 no activity
1 - Port 10 has activity
0 - Port 11 no activity
1 - Port 11 has activity
0 - Port 12 no activity
1 - Port 12 has activity
0 - Port 13 no activity
1 - Port 13 has activity
0 - Port 14 no activity
1 - Port 14 has activity
0 - Port 15 no activity
1 - Port 15 has activity
0 - Port 16 no activity
1 - Port 16 has activity
0 - Port 17 no activity
1 - Port 17 has activity
0 - Port 18 no activity
1 - Port 18 has activity
0 - Port 19 no activity
1 - Port 19 has activity
0 - Port 20 no activity
1 - Port 20 has activity
0 - Port 21 no activity
1 - Port 21 has activity
0 - Port 22 no activity
1 - Port 22 has activity
0 - Port 23 no activity
1 - Port 23 has activity

0

The SYSCFG register specifies certain system con­figurations. The system options are described in the
chapter of “Function Description.” T able-7.16 describes
all the bit of this register.

Table-7.16: SYSCFG Register

Bit Descripti on Default

0 0 - BIST en abled; 0

1 - BIST disabled.

1 0 - Spanning Tree support disabled; 0

1 - Spanning Tree support enabled
2 Reserved. 0
3 Reserved. 0
4 Reserved. 0
5 0 - wait for CP U. 0

1 - system ready to start

*This bit is used by the CPU w hen bit-15 of

registe r-2 5 i s set a s "0 " (fo r system with

control CPU). The system w ill wait for CPU

to set th i s bit .

6 0 - PHY Management not completed 0

1 - PHY Management completed.

*This bit is used by the CPU w hen bit-15 of

register-25 is set as "0" (for system with a

control CPU). The MAC will not start until this

bi t i s se t sy the CPU.

7 0 - Watchdog function enabled. 0

1 - Watchdog function disabled.
8 0 - Secure VLAN checking rule enforced. 0

1 - Leaky V LAN checking rule enforced.
9 0 - Rising edge of RXCLK to la tch data. 0

1 - Falling edge of RXCLK to latch data.

*For Reversed MII port only.

10 0 - Late Back-Pressure scheme disabled 0

1 - Late Back-Pressure scheme enabled

*When ena ble d , the MAC will gene rate ba ck-

pressure only after reading the first bit of DA

0 - special handling of broadcast frames

11

disabled

1 - special handling of broadcast frames

enabled

*When enabled, all broadcast frames from

non-CPU port are forw arded to the CPU port

only, and all broadcast frames from the CPU

port are forwarded to all other ports.

Software Rese t: "1" to sta rt a sy stem re set to

12

innitialize all state machin es.

Hardware Reset: "1" to stop the life pulse on

the watchdo g p in , wh ich in tu rn will trigg e r the

13

external watchdog circuitry to reset the whole

system.

14 Reserved 0
15 Reserved 0

0

0

Data Sheet: ACD82124

INTRODUCTORY

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

18

INTMSK register (register 17)
The INTMSK register defines the valid interrupt sources

allowed to assert interrupt request pin. T able-7.17 lists
all the bits of this register.

Table-7. 17: INTMSK Register

Bit Description Default

0

1

2
3 Reserved 1

4 Reserved 1
5 Reserved 1
6 Reserved 1
7 Reserved 1

Enable "system initialization

completi o n " to i n te rrup t

Enable "internal system error"

to interrupt

Enable "port partition event"

to interrupt

1

1

1

SPEED register (register 18)
The SPEED register specifies or indicates the speed

rate of each port. It is read-only, unless the bit-12 of
register-25 is set (through POS to disable automatic
PHY management). At read-only mode, it indicates
the speed achieved through PHY management. At the
write-able mode, the control CPU will be able to assign
speed rate for each port. Table-7.18 describes all the
bit of this register.

LINK register (register 19)
The LINK register specifies or indicates the link status

of each port. It is read-only, unless bit-12 of register­25 is set (through POS, to disable automatic PHY man­agement). At read-only mode, it indicates the result
achieved by PHY management. At write-able mode,

Table-7.18: SPEED Register

Bit De fault

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Description

0 - Port 0 at 10 Mbps
1 - Port 0 at 100 Mbps
0 - Port 1 at 10 Mbps
1 - Port 1 at 100 Mbps
0 - Port 2 at 10 Mbps
1 - Port 2 at 100 Mbps
0 - Port 3 at 10 Mbps
1 - Port 3 at 100 Mbps
0 - Port 4 at 10 Mbps
1 - Port 4 at 100 Mbps
0 - Port 5 at 10 Mbps
1 - Port 5 at 100 Mbps
0 - Port 6 at 10 Mbps
1 - Port 6 at 100 Mbps
0 - Port 7 at 10 Mbps
1 - Port 7 at 100 Mbps
0 - Port 8 at 10 Mbps
1 - Port 8 at 100 Mbps
0 - Port 9 at 10 Mbps
1 - Port 9 at 100 Mbps
0 - Port 10 at 10 Mbps
1 - Port 10 at 100 Mbps
0 - Port 11 at 10 Mbps
1 - Port 11 at 100 Mbps
0 - Port 12 at 10 Mbps
1 - Port 12 at 100 Mbps
0 - Port 13 at 10 Mbps
1 - Port 13 at 100 Mbps
0 - Port 14 at 10 Mbps
1 - Port 14 at 100 Mbps
0 - Port 15 at 10 Mbps
1 - Port 15 at 100 Mbps
0 - Port 16 at 10 Mbps
1 - Port 16 at 100 Mbps
0 - Port 17 at 10 Mbps
1 - Port 17 at 100 Mbps
0 - Port 18 at 10 Mbps
1 - Port 18 at 100 Mbps
0 - Port 19 at 10 Mbps
1 - Port 19 at 100 Mbps
0 - Port 20 at 10 Mbps
1 - Port 20 at 100 Mbps
0 - Port 21 at 10 Mbps
1 - Port 21 at 100 Mbps
0 - Port 22 at 10 Mbps
1 - Port 22 at 100 Mbps
0 - Port 23 at 10 Mbps
1 - Port 23 at 100 Mbps

Data Sheet: ACD82124

0

INTRODUCTORY

19

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

the control CPU can assign link status for each port.
T able-7.19 describes all the bit of this register.

nFWD register (register 20)
The nFWD register defines the forwarding mode of

each port. Under

forwarding

mode, a port can forward

Table-7. 19: LINK Register

Bit D efault

0 - Port 0 link not established

0

1 - Port 0 link established
0 - Port 1 link not established

1

1 - Port 1 link established
0 - Port 2 link not established

2

1 - Port 2 link established
0 - Port 3 link not established

3

1 - Port 3 link established
0 - Port 4 link not established

4

1 - Port 4 link established
0 - Port 5 link not established

5

1 - Port 5 link established
0 - Port 6 link not established

6

1 - Port 6 link established
0 - Port 7 link not established

7

1 - Port 7 link established
0 - Port 8 link not established

8

1 - Port 8 link established
0 - Port 9 link not established

9

1 - Port 9 link established

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0 - Port 10 link not established
1 - Port 10 link established
0 - Port 11 link not established
1 - Port 11 link established
0 - Port 12 link not established
1 - Port 12 link established
0 - Port 13 link not established
1 - Port 13 link established
0 - Port 14 link not established
1 - Port 14 link established
0 - Port 15 link not established
1 - Port 15 link established
0 - Port 16 link not established
1 - Port 16 link established
0 - Port 17 link not established
1 - Port 17 link established
0 - Port 18 link not established
1 - Port 18 link established
0 - Port 19 link not established
1 - Port 19 link established
0 - Port 20 link not established
1 - Port 20 link established
0 - Port 21 link not established
1 - Port 21 link established
0 - Port 22 link not established
1 - Port 22 link established
0 - Port 23 link not established
1 - Port 23 link established

Description

0

all frames. Under

block-and-listen

mode, a port will
not forward regular frames, except BPDU frames. If
the spanning tree algorithm discovers redundant links,
the control CPU will allow only one link remaining in

forwarding
and-listen

ister will put the port into

mode and force all other links into

block-

mode. Setting the associated bit in this reg-

block-and-listen

mode. T able-

7.20 describes all the bit of this register.

Table-7. 20: nFWD Register

Bit De fault

0 - Port 0 in forwarding state

0

1 - Port 0 in block-and-listen state
0 - Port 1 in forwarding state

1

1 - Port 1 in block-and-listen state
0 - Port 2 in forwarding state

2

1 - Port 2 in block-and-listen state
0 - Port 3 in forwarding state

3

1 - Port 3 in block-and-listen state
0 - Port 4 in forwarding state

4

1 - Port 4 in block-and-listen state
0 - Port 5 in forwarding state

5

1 - Port 5 in block-and-listen state
0 - Port 6 in forwarding state

6

1 - Port 6 in block-and-listen state
0 - Port 7 in forwarding state

7

1 - Port 7 in block-and-listen state
0 - Port 8 in forwarding state

8

1 - Port 8 in block-and-listen state
0 - Port 9 in forwarding state

9

1 - Port 9 in block-and-listen state
0 - Port 10 in forwarding state

10

1 - Port 10 in block-and-listen state
0 - Port 11 in forwarding state

11

1 - Port 11 in block-and-listen state
0 - Port 12 in forwarding state

12

1 - Port 12 in block-and-listen state
0 - Port 13 in forwarding state

13

1 - Port 13 in block-and-listen state
0 - Port 14 in forwarding state

14

1 - Port 14 in block-and-listen state
0 - Port 15 in forwarding state

15

1 - Port 15 in block-and-listen state
0 - Port 16 in forwarding state

16

1 - Port 16 in block-and-listen state
0 - Port 17 in forwarding state

17

1 - Port 17 in block-and-listen state
0 - Port 18 in forwarding state

18

1 - Port 18 in block-and-listen state
0 - Port 19 in forwarding state

19

1 - Port 19 in block-and-listen state
0 - Port 20 in forwarding state

20

1 - Port 20 in block-and-listen state
0 - Port 21 in forwarding state

21

1 - Port 21 in block-and-listen state
0 - Port 22 in forwarding state

22

1 - Port 22 in block-and-listen state
0 - Port 23 in forwarding state

23

1 - Port 23 in block-and-listen state

Description

0

Data Sheet: ACD82124

INTRODUCTORY

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

20

nBP register (register 21)

nPORT register (register 22)

The nBP register defines back-pressure flow control
capability for each port. Table-7.21 describes all the
bit of this register.

Table-7.21: nBP Register

Bit Default

0 - Port 0 back-pressure scheme enabled

0

1 - Port 0 back-pressure scheme disabled
0 - Port 1 back-pressure scheme enabled

1

1 - Port 1 back-pressure scheme disabled
0 - Port 2 back-pressure scheme enabled

2

1 - Port 2 back-pressure scheme disabled
0 - Port 3 back-pressure scheme enabled

3

1 - Port 3 back-pressure scheme disabled
0 - Port 4 back-pressure scheme enabled

4

1 - Port 4 back-pressure scheme disabled
0 - Port 5 back-pressure scheme enabled

5

1 - Port 5 back-pressure scheme disabled
0 - Port 6 back-pressure scheme enabled

6

1 - Port 6 back-pressure scheme disabled
0 - Port 7 back-pressure scheme enabled

7

1 - Port 7 back-pressure scheme disabled
0 - Port 8 back-pressure scheme enabled

8

1 - Port 8 back-pressure scheme disabled
0 - Port 9 back-pressure scheme enabled

9

1 - Port 9 back-pressure scheme disabled
0 - Port 10 back-pressure scheme enabled

10

1 - Port 10 back-pressure scheme disabled
0 - Port 11 back-pressure scheme enabled

11

1 - Port 11 back-pressure scheme disabled
0 - Port 12 back-pressure scheme enabled

12

1 - Port 12 back-pressure scheme disabled
0 - Port 13 back-pressure scheme enabled

13

1 - Port 13 back-pressure scheme disabled
0 - Port 14 back-pressure scheme enabled

14

1 - Port 14 back-pressure scheme disabled
0 - Port 15 back-pressure scheme enabled

15

1 - Port 15 back-pressure scheme disabled
0 - Port 16 back-pressure scheme enabled

16

1 - Port 16 back-pressure scheme disabled
0 - Port 17 back-pressure scheme enabled

17

1 - Port 17 back-pressure scheme disabled
0 - Port 18 back-pressure scheme enabled

18

1 - Port 18 back-pressure scheme disabled
0 - Port 19 back-pressure scheme enabled

19

1 - Port 19 back-pressure scheme disabled
0 - Port 20 back-pressure scheme enabled

20

1 - Port 20 back-pressure scheme disabled
0 - Port 21 back-pressure scheme enabled

21

1 - Port 21 back-pressure scheme disabled
0 - Port 22 back-pressure scheme enabled

22

1 - Port 22 back-pressure scheme disabled
0 - Port 23 back-pressure scheme enabled

23

1 - Port 23 back-pressure scheme disabled

Description

0

The nPORT register is used to isolate ports from the
network. Setting the associated bit in this register will
stop a port from receiving or transmitting any frame.
T able-7.22 describes all the bits of this register.

Table-7. 22: nPort Register

Bit Default

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Description

0 - Port 0 enabled
1 - Port 0 disabled
0 - Port 1 enabled
1 - Port 1 disabled
0 - Port 2 enabled
1 - Port 2 disabled
0 - Port 3 enabled
1 - Port 3 disabled
0 - Port 4 enabled
1 - Port 4 disabled
0 - Port 5 enabled
1 - Port 5 disabled
0 - Port 6 enabled
1 - Port 6 disabled
0 - Port 7 enabled
1 - Port 7 disabled
0 - Port 8 enabled
1 - Port 8 disabled
0 - Port 9 enabled
1 - Port 9 disabled
0 - Port 10 enabled
1 - Port 10 disabled
0 - Port 11 enabled
1 - Port 11 disabled
0 - Port 12 enabled
1 - Port 12 disabled
0 - Port 13 enabled
1 - Port 13 disabled
0 - Port 14 enabled
1 - Port 14 disabled
0 - Port 15 enabled
1 - Port 15 disabled
0 - Port 16 enabled
1 - Port 16 disabled
0 - Port 17 enabled
1 - Port 17 disabled
0 - Port 18 enabled
1 - Port 18 disabled
0 - Port 19 enabled
1 - Port 19 disabled
0 - Port 20 enabled
1 - Port 20 disabled
0 - Port 21 enabled
1 - Port 21 disabled
0 - Port 22 enabled
1 - Port 22 disabled
0 - Port 23 enabled
1 - Port 23 disabled

0

Data Sheet: ACD82124

INTRODUCTORY

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

21

PVID registers (register 23)
The PVID registers assign VLAN IDs for each port.

There are 24 PVID registers, one for each port. A
PVID consists of 4 bits, each corresponding to one of
the 4 VLANs. A port can belong to more than one
VLAN at the same time. T able-7.23 describes the bits
of one of the registers.

Data Sheet: ACD82124

Table-7. 23: PVID Registers

Bit Description Default

0 0 - port not in VLAN-I. 1

1 - port in VLAN-I.

1 0 - port not in VLAN-II. 0

1 - port in VLAN-II.

2 0 - port not in VLAN-III. 0

1 - port in VLAN-III.

3 0 - port not in VLAN-IV. 0

1 - port in VLAN-IV.

(24 registers)

VPID registers (register 24)
The VPID registers specify the dumping port for each

VLAN. There are 4 VPID 5-bit registers, one for each
VLAN. A valid VPID are “0” through “23” (other values
are reserved and should not used). Table-7.24 de­scribes the bits one of the registers.

Table-7. 24: VPID Registers

Bit Description Default

4:0 Dumping port ID for VLAN -1 "00000"
4:0 Dumping port ID for VLAN -2 "11111"
4:0 Dumping port ID for VLAN -3 dumping port
4:0 Dumping port ID for VLAN -4 not defined

(4 registers)

INTRODUCTORY

22

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Table-7. 25: POSCFG Register

Bit De scription De fault

3:0 8 timing adjustment levels for SRAM Read data latching: 0000

0000 - no delay
0001 - level 1 delay
0011 - level 2 delay
0101 - level 3 delay
0111 - level 4 delay
1001 - level 5 delay
1011 - level 6 delay
1101 - level 7 delay
1111 - level 8 delay

4 0 - Absolute address mode: 1 row of 512K words, nCS2=ADDR17, nCS3=ADDR18 0

1 - Chip-Select address mode: 4 rows of 128K words, nCS[3:0] to select 4 rows of memory

6:5 SRAM size selection: 000

00 - 64K words
01 - 128K words
10 - 256k words
11 - 512K words

7 0 - Long Event defined as frame longer than 1518 byte. 0

1 - Long Event defined as frame longer than 1530 byte.

8 0 - Frames with unknown DA forwarded to the dumping port. 0

1 - Frames with unknown DA forwarded to all ports.

9 0 - Internal ARL selected (2K MAC address entry). 0

1 - External ARL selected (11K MAC address entry).

10 0 - PHY IDs start from 1, range from 1 to 24. 0

1 - PHY I Ds start from 4, range from 4 to 27.

11 0 - Re-transmit after excessive collision. 0

1 - Drop after excessive collision.

12 0 - Automatic PHY Management enabled 0

1 - Automatic PHY Management disabled: the control CPU need to update the SPEED, LINK, DPLX and
nPAUSE registers

13 0 - Rising edge of RxClk triggering for regular MII ports 0

0 - Falling edge of RxClk triggering for regular MII ports

14 0 - Sysem errors will trigger software reset 0

1 - Sysem errors will trigger hardware reset

15 0 - System start itself without a control CPU 0

1 - System start after system-ready bit in register-16 is set by the control CPU

17:16

2-bit device I D for UA RT communication. The device responses only to UART commands with
matching ID

18 0 - Rising edge of ARLCLK to latch ARLDI. 0

1 - Falling edge of ARLCLK to latch ARLDI .

Data Sheet: ACD82124

INTRODUCTORY

00

POSCFG register (register 25)
The POSCFG register specifies a certain configura-

tion setting for the switch system. The default values of
this register can be changed through pull-up/pull-down
of specific pins, as described in the “Configuration
Interface” section of the “Interface Description” chap­ter. Table-7.25 describes all the bit of this register.

FdEn register (

register 26

)

FdEn register is used to specify if an even numbered
port has been connected as a full duplex port. The

default value of FdCfg is determined by Pull-High or
Pull-Low status of the hardware pins shown in Table­26

.

DPLX register (register 27)
The DPLX register specifies or indicates the half/full-

duplex mode of each of the 12 even-numbered ports
(

port 0, 2, 4, .. 20 and 22

). It is read-only, unless bit­12 of register-25 is set (through POS, to disable auto­matic PHY management). At read-only mode, it indi­cates the result achieved by the PHY management. At
write-able mode, the control CPU can assign a half­duplex or full-duplex mode for each of the 12 even-

23

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Table-7. 26: FdEn Register

Bit De fault

0

1

2

3

4

5

6

7

8

9

10

11

0 - Port 0 & 1 each in Half-Duplex mode
1 - Port 0 & 1 paired into ONE Full-Duplex-Capable port
0 - Port 2 & 3 each in Half-Duplex mode
1 - Port 2 & 3 paired into ONE Full-Duplex-Capable port
0 - Port 4 & 5 each in Half-Duplex mode
1 - Port 4 & 5 paired into ONE Full-Duplex-Capable port
0 - Port 6 & 7 each in Half-Duplex mode
1 - Port 6 & 7 paired into ONE Full-Duplex-Capable port
0 - Port 8 & 9 each in Half-Duplex mode
1 - Port 8 & 9 paired into ONE Full-Duplex-Capable port
0 - Port 10 & 11 each in Half-Duplex mode
1 - Port 10 & 11 paired into ONE Full-Duplex-Capable port
0 - Port 12 & 13 each in Half-Duplex mode
1 - Port 12 & 13 paired into ONE Full-Duplex-Capable port
0 - Port 14 & 15 each in Half-Duplex mode
1 - Port 14 & 15 paired into ONE Full-Duplex-Capable port
0 - Port 16 & 17 each in Half-Duplex mode
1 - Port 16 & 17 paired into ONE Full-Duplex-Capable port
0 - Port 18 & 19 each in Half-Duplex mode
1 - Port 18 & 19 paired into ONE Full-Duplex-Capable port
0 - Port 20 & 21 each in Half-Duplex mode
1 - Port 20 & 21 paired into ONE Full-Duplex-Capable port
0 - Port 22 & 23 each in Half-Duplex mode
1 - Port 22 & 23 paired into ONE Full-Duplex-Capable port

Description

Data Sheet: ACD82124

0

Table-7. 27: DPLX Register

Bit De fault

0

1

2

3

4

5

6

7

8

9

10

11

0 - Port 0 & 1 run as TWO independant Half-Duplex ports
1 - Port 0 & 1 pair run as ONE Full-Duplex port
0 - Port 2 & 3 run as TWO independant Half-Duplex ports
1 - Port 2 & 3 pair run as ONE Full-Duplex port
0 - Port 4 & 5 run as TWO independant Half-Duplex ports
1 - Port 4 & 5 pair run as ONE Full-Duplex port
0 - Port 6 & 7 run as TWO independant Half-Duplex ports
1 - Port 6 & 7 pair run as ONE Full-Duplex port
0 - Port 8 & 9 run as TWO independant Half-Duplex ports
1 - Port 8 & 9 pair run as ONE Full-Duplex port
0 - Port 10 & 11 run as TWO independant Half-Duplex ports
1 - Port 10 & 11 pair run as ONE Full-Duplex port
0 - Port 12 & 13 run as TWO independant Half-Duplex ports
1 - Port 12 & 13 pair run as ONE Full-Duplex port
0 - Port 14 & 15 run as TWO independant Half-Duplex ports
1 - Port 14 & 15 pair run as ONE Full-Duplex port
0 - Port 16 & 17 run as TWO independant Half-Duplex ports
1 - Port 16 & 17 pair run as ONE Full-Duplex port
0 - Port 18 & 19 run as TWO independant Half-Duplex ports
1 - Port 18 & 19 pair run as ONE Full-Duplex port
0 - Port 20 & 21 run as TWO independant Half-Duplex ports
1 - Port 20 & 21 pair run as ONE Full-Duplex port
0 - Port 22 & 23 run as TWO independant Half-Duplex ports
1 - Port 22 & 23 pair run as ONE Full-Duplex port

Description

INTRODUCTORY

0

24

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

number ports. Table-7.27 describes all the bits of this
register.

RVSMII register (register 28)
The RVSMII register defines the

reversed MII

mode
for each port. Table-7.28 describes all the bits of this
register.

Table-7. 28: RVSMII register

Bit De scription D efault

0 0 - Port 0 under normal MII mode 0

1 - Port 0 under reversed MII mode

1 0 - Port 1under normal MII mode 0

1 - Port 1 under reversed MII mode

2 0 - Port 2 under normal MII mode 0

1 - Port 2under reversed MII mode

3 0 - Port 3 under normal MII mode 0

1 - Port 3 under reversed MII mode

4 0 - Port 4 under normal MII mode 0

1 - Port 4 under reversed MII mode

5 1 - Port 5 under normal MII mode 0

2 - Port 5 under reversed MII mode

6 1 - Port 6 under normal MII mode 0

2 - Port 6 under reversed MII mode

7 1 - Port 7 under normal MII mode 0

2 - Port 7 under reversed MII mode

8 1 - Port 22 under normal MII mode 0

2 - Port 22 under reversed MII mode

9 1 - Port 23 under normal MII mode 0

2 - Port 23 under reversed MII mode

nPM register (register 29)
The nPM register indicates the automatic PHY man-

agement capability of each port. If a bit is set in this
register, the corresponding SPEED, LINK, DPLX, and
nPAUSE status registers of a port will remain un­changed. Table-7.29 describes all the bits of this reg­ister.

Table-7. 29: nPM Register

Bit De f ault

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0 - Port 0 status update enabled
1 - Port 0 status update disabled
0 - Port 1 status update enabled
1 - Port 1 status update disabled
0 - Port 2 status update enabled
1 - Port 2 status update disabled
0 - Port 3 status update enabled
1 - Port 3 status update disabled
0 - Port 4 status update enabled
1 - Port 4 status update disabled
0 - Port 5 status update enabled
1 - Port 5 status update disabled
0 - Port 6 status update enabled
1 - Port 6 status update disabled
0 - Port 7 status update enabled
1 - Port 7 status update disabled
0 - Port 8 status update enabled
1 - Port 8 status update disabled
0 - Port 9 status update enabled
1 - Port 9 status update disabled
0 - Port 10 status update enabled
1 - Port 10 status update disabled
0 - Port 11 status update enabled
1 - Port 11 status update disabled
0 - Port 12 status update enabled
1 - Port 12 status update disabled
0 - Port 13 status update enabled
1 - Port 13 status update disabled
0 - Port 14 status update enabled
1 - Port 14 status update disabled
0 - Port 15 status update enabled
1 - Port 15 status update disabled
0 - Port 16 status update enabled
1 - Port 16 status update disabled
0 - Port 17 status update enabled
1 - Port 17 status update disabled
0 - Port 18 status update enabled
1 - Port 18 status update disabled
0 - Port 19 status update enabled
1 - Port 19 status update disabled
0 - Port 20 status update enabled
1 - Port 20 status update disabled
0 - Port 21 status update enabled
1 - Port 21 status update disabled
0 - Port 22 status update enabled
1 - Port 22 status update disabled
0 - Port 23 status update enabled
1 - Port 23 status update disabled

Description

0

Data Sheet: ACD82124

INTRODUCTORY

25

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

ERRMSK register (register 30)

PHYREG registers (register 32-63)

The ERRMSK register defines certain errors as

tem errors

. It is reserved for factory use only. Table-

sys-

7.30 lists all the error masks specified by this register.

Table-7. 30: ERRMSK register

Bit D escription Set ting

0 Reserved
1 Reserved
2 Reserved
3 Reserved
4 Reserved
5 Reserved
6 Reserved
7 Reserved 0

All "1", unless

otherwise

advised, to

ensure proper

operation.

CLKADJ register (register 31)
The CLKADJ register defines the delay time of the

ARLCLK relative to the transition edge of the data sig­nals. The ARLCLK provides reference timing for sup­porting chips, such as the ACD80800 and the
ACD80900, which need to snoop the data bus for cer­tain activities. Table-7.31 describes all the bits of this
register.

The PHYREG refers to the registers residing on the
PHY devices. There are 24 sets of these registers.
Each port has its own corresponding set of register
32-63. The ACD82124 merely provides an access path
for the control CPU to access the registers on the
PHYs. For detailed information about these registers,
please refer to the PHY data sheet.

Since the native registers ID “0” through “31” on the
PHYs have been used by the internal registers of the
ACD82124, they need to be re-mapped into “32”
through “63” by adding “32” to each original register
ID. An index is used by the ACD82124 to specify the
PHY ID. For example, register-32 with index-4 would
refer to the control register (register-0) in the PHY-4.

Data Sheet: ACD82124

INTRODUCTORY

Table-7. 31: CLKADJ Register

Bit De scription Default

0 0 - ARLCLK not inverted 0

1 - ARLCLK inverted

3:1 ARLCLK delay levels: 000

000 - level 0 delay
001 - level 1 delay
010 - level 2 delay
011 - level 3 delay
100 - level 4 delay
101 - level 5 delay
110 - level 6 delay
111 - level 7 delay

26

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

8. PIN DESCRIPTIONS

Pin Diagram

Bottom View

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

Data Sheet: ACD82124

30

28

26

24

22

20

18

16

INTRODUCTORY

14

12

10

8

6

4

2

AK

AJ

AH

AG

AF

AE

AD

AC

AB

ABCDEFGHJKLMNPRTUVWY

AA

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

27

Pin List By Location: Part 1

Pin

A01 P23RXD0R I C13 P20RXCLK I E25 P16T XD1 O K 01 DAT A40 I/O
A02 VDD C 14 P20T XD0 O E 26 VDD K 02 DAT A39 I/O
A03 P23T XD2R O C15 P19RXD3 I E 27 P15RXC LK I K 03 ADDR2 O
A04 P22RXD3R I C16 P19RXCLK I E28 P15T XD3 O K 04 nCS3 O
A05 P22RXERR I C17 P 19T XD0 O E29 P14RXD0 I K05 VDD
A06 P22T XD1R O C18 P19CO L I E 30 P14T XEN O K06 VS S
A07 P22T XD3R O C19 P18RXD1 I F01 DAT A48 I/OK25 VSS
A08 P21RXD0 I C20 P18RXER I F02 DAT A47 I/OK26 VDD
A09 P21T XCLK I C21 P18T XD1 O F03 ARLDI3 I K 27 P13RXD0 I
A10 P21T XD0 O C 22 P17RXD2 I F 04 ARLCLK O K28 P13T XC LK I
A11 P20RXD3 I C23 P 17RXCLK I F05 ARL S Y NC O K29 P13T XD1 O
A12 P20RXD0 I C24 P17T XD2 O F06 VS S K30 P13T XD2 O
A13 P20T XCLK I C25 P17C RS I F07 P23RXERR I L01 DAT A38 I/O
A14 P20T XD2 O C 26 P16RXD0 I F 08 VS S L 02 DAT A37 I/ O
A15 P19RXD1 I C27 P16T XD3 O F09 P22RXD1R I L03 ADD R3 O
A16 P19RXD0 I C28 P15RXD2 I F 10 VS S L 04 nCS2 O
A17 P19T XCLK I C29 P15T XD0 O F11 P22CRSR I/OL05 VDD
A18 P19T XD2 O C 30 P15C O L I F 12 VS S L 06 VS S
A19 VS S D01 S T AT 3 O F13 P21CO L I L 25 P13RXD2 I
A20 P18RXDV I D02 DAT A51 I/O F 14 VS S L 26 P13RXD1 I
A21 P18T XE N O D03 ARLDI0 I F 15 P20T XD3 O L27 P13T XE N O
A22 P 18CRS I D04 P23RXD3R I F16 VS S L 28 P13T XD3 O
A23 P17RXD1 I D05 P23RXC LKR I/O F17 VS S L 29 P13COL I
A24 P17RXER I D06 P23T XD0R O F 18 P18RXD2 I L30 P12RXD1 I
A25 P17T XD3 O D07 P23CO LR I/O F 19 VS S M01 DAT A36 I/O
A26 P16RXD2 I D08 P22RXDVR I F 20 P18T XD3 O M02 DAT A35 I/O
A27 P16RXER I D09 P22T XD0R O F 21 VS S M03 nCS0 O
A28 P16T XD0 O D10 P21RXD2 I F 22 P17T XD0 O M04 ADD R16 O
A29 P 16CRS I D11 P21RXER I F23 VS S M05 VDD
A30 P15RXD0 I D12 P21T XD3 O F24 P16T XCLK I M06 VS S
B01 S T AT 0 O D13 P20RXDV I F25 VSS M25 VS S
B02 P23RXD1R I D14 P20T XEN O F26 P15RXDV I M26 VDD
B03 P23T XCLKR I/O D15 P20CRS I F27 P15T XD2 O M27 P13C RS I
B04 P23T XD3R O D16 P19RXDV I F28 P14RXD2 I M28 P12RXD0 I
B05 P22RXD2R I D17 P19T XD1 O F29 P14T XD0 O M29 P12RXDV I
B06 P22T XCLKR I/O D18 P19CRS I F30 P14T XD3 O M30 P12RXCLK I
B07 P22T XD2R O D19 P18RXD0 I G01 DAT A46 I/ O N01 DAT A34 I/O
B08 P21RXD1 I D20 P18T XCLK I G02 DAT A45 I/O N02 DAT A33 I/O
B09 P 21RXDV I D21 P18C O L I G03 ARLDIR0 O N03 VDD
B10 P 21T XEN O D22 P17RXD0 I G04 ARLDIR1 O N04 ADDR15 O
B11 P21T XD2 O D23 P17T XD1 O G05 VDD N05 VDD
B12 P20RXD1 I D24 P16RXD3 I G06 VS S N 06 VS S
B13 P 20RXE R I D25 P16RXCLK I G25 P15RXER I N25 P12RXD3 I
B14 P20T XD1 O D26 P16T XD2 O G26 P15T XD1 O N26 P12RXD2 I
B15 P19RXD2 I D27 P15RXD3 I G27 P14RXD3 I N27 P12RXER I
B16 P 19RXE R I D28 P15T XC LK I G28 P14T XCLK I N28 P12T XCLK I
B17 P 19T XEN O D29 P15CRS I G29 P14C O L I N29 P12T XEN O
B18 P19T XD3 O D30 P14RXD1 I G30 P14CRS I N30 P 12T XD0 O
B19 VDD E01 DAT A50 I/O H01 DAT A44 I/O P01 DAT A32 I/O
B20 P18RXCLK I E02 DAT A49 I/ O H02 DAT A43 I/O P02 DAT A31 I/ O
B21 P 18T XD0 O E 03 ARL DI2 I H03 ADDR0 O P 03 nWE O
B22 P 17RXD3 I E 04 ARLDI1 I H04 ARLDIV I P 04 VS S
B23 P17RXDV I E 05 VDD H05 VDD P05 VDD
B24 P17T XC LK I E06 P23RXDVR I H06 VSS P06 VS S
B25 P17CO L I E07 P23T XENR O H25 VS S P25 VS S
B26 P 16RXD1 I E 08 VDD H26 VDD P26 VDD
B27 P 16T XEN O E 09 P22RXD0R I H27 P14RXER I P27 P12T XD1 O
B28 P16CO L I E10 VDD H28 P14T XD1 O P28 P12T XD2 O
B29 P15RXD1 I E 11 P21RXD3 I H29 P13RXDV I P29 P12T XD3 O
B30 P 15T XEN O E 12 VDD H30 P13RXCLK I P30 P12COL I
C01 S T AT 1 O E 13 P21CRS I J01 DAT A42 I/ O R01 DAT A30 I/O
C02 STAT2 O E14 VDD J02 DATA41 I/O R02 DAT A29 I/ O
C03 P23RXD2R I E15 P20C O L I J03 ADDR1 O R03 ADDR4 O
C04 VS S E 16 VDD J 04 nCS 1 O R04 nOE I / O
C05 P23T XD1R O E 17 VDD J05 VDD R05 VDD
C06 P23C RS R I/ O E18 P18RXD3 I J06 VS S R06 VS S
C07 P22RXCLKR I/O E 19 VDD J25 P14RXDV I R25 P12CRS I
C08 P 22T XENR O E 20 P18T XD2 O J26 P14RXCLK I R26 P11RXD3 I
C09 P22C O LR I/O E21 VDD J27 P14T XD2 O R27 P11RXD2 I
C10 P21RXCLK I E22 P17T XE N O J28 P13RXD3 I R28 P11RXD1 I
C11 P21T XD1 O E 23 VDD J29 P13RXER I R29 P11RXD0 I
C12 P20RXD2 I E24 P16RXDV I J30 P13T XD0 O R30 P11RXDV I

Signal

Name

I/O

Type

Pin

Signal

Name

I/O

Type

Pin

Signal

Name

I/O

Type

Pin

Signal

Name

I/O

Type

Data Sheet: ACD82124

INTRODUCTORY

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

28

Pin List By Location: Part 2

Pin

T 01 DAT A28 I/O AB 01 DAT A16 I/O AF07 P0T XENR O AH19 P4RXD0R I
T 02 DAT A27 I/O AB 02 DAT A15 I/O AF08 VDD AH20 P5T XD3R I/O
T 03 ADDR5 O AB 03 VDD AF09 P1T XD3R I/ OAH21 P5TXCLKR I/O
T04ADDR14OAB04LED3I/O AF 10 VDD AH22 P 5RXD3R I
T 05 VDD AB05 VDD AF11 P1RXD3R I AH23 P6T XD1R I/O
T 06 VS S AB06 VSS AF12 VDD AH24 P 6T XCLKR I/O
T 25 VSS AB25 VSS AF13 P2RXD1R I AH25 P6RXD2R I
T 26 VDD AB 26 VDD AF 14 VDD AH26 P 7T XD3R I/O
T 27 P11RXER I AB 27 P9T XCLK I AF15 VDD AH27 VDD
T 28 P11T XC LK I AB28 P9RXCLK I AF16 P3RXD3R I AH28 P7RXD0R I
T 29 P11T XE N O AB29 P9RXDV I AF17 VDD AH29 P7RXD3R I
T 30 P11RXCLK I AB30 P9RXD0 I AF18 P4RXD2R I AH30 P8T XD2 O
U01 DAT A26 I/ O AC01 DAT A14 I/O AF19 VDD AJ01 DAT A2 I/ O
U02 DAT A25 I/ O AC02 DAT A13 I/O AF20 P5RXD1R I AJ02 DAT A1 I/O
U03 ADDR 6 O AC03 LE D2 I/OAF21 VDD AJ03 VSS
U04ADDR13OAC04LED0I/OAF22P6RXCLKRI/O AJ04 P0T XD3R I/O
U05 VDD AC05 VDD AF23 VDD AJ05 P0RXE RR I
U06 VS S AC06 VS S AF24 P7T XD1R I/ O AJ06 P0RXD1R I
U25 VS S AC25 VS S AF25 P 7RXE RR I AJ07 P1T XD2R I/O
U26 VDD AC26 VDD AF26 VDD AJ08 P1T XE NR O
U27 P11T XD3 O AC27 P9T XD3 O AF 27 P8CO L I AJ09 P1RXDVR I
U28 P11T XD2 O AC28 P9T XD0 O AF 28 P8RXCLK I AJ10 P2C O LR I/O
U29 P11T XD1 O AC29 P9T XEN O AF29 P8RXDV I AJ11 P2T XD0R I/O
U30 P11T XD0 O AC30 P9RXE R I AF30 P8RXD0 I AJ12 P2RXCLKR I/O
V01 DAT A24 I/ O AD01 DAT A12 I/ O AG01 DAT A6 I/OAJ13 P3CRSR I/O
V02 DAT A23 I/ O AD02 DAT A11 I/ O AG02 DAT A5 I/O AJ14 P3T XD1R I/O
V03 ADDR7 O AD03 L ED1 I/O AG03 CPUIRQ O AJ15 P3TXENR O
V04 ADDR12 O AD04 L EDVLD0 I/O AG04 MDC O AJ16 P3RXD0R I
V05 VDD AD 05 VDD AG05 nRES ET I AJ17 P4T XD3R I/O
V06 VSS AD06 VS S AG06 P0T XD0R I/OAJ18 P4TXENR O
V25 P10RXD0 I AD25 P8T XD0 O AG07 P0RXDVR I AJ19 P4RXDVR I
V26 P10RXD1 I AD26 P8RXER I AG08 P1CRS R I/OAJ20 P5COLR I/O
V27 P10RXD2 I AD27 P8RXD1 I AG09 P1T XC LKR I/O AJ21 P5T XD1R I/O
V28 P10RXD3 I AD28 P9COL I AG10 P1RXD1R I AJ22 P5RXERR I
V29 P11CRS I AD29 P9T XD2 O AG11 P2T XD2R I/OAJ23 P5RXDVR I

V30 P11CO L I AD30 P9T XD1 O AG 12 P2T XCLKR I/OAJ24 P6COLR I/O
W01 DAT A22 I/ O AE01 DAT A10 I/O AG13 P2RXD2R I AJ25 P6T XD0R I/O
W02 DAT A21 I/ O AE02 DAT A9 I/ O AG 14 P3T XD3R I/O AJ26 P6RXD0R I
W03 ADDR8 O AE03 L E DVL D1 I/ O AG15 P3RXERR I AJ27 P7CRS R I/O
W04 ADDR11 O AE04 LEDCLK I/O AG 16 P3RXD2R I AJ28 P7T XD0R I/ O
W05 VDD AE05 VS S I AG17 P4T XD1R I/OAJ29 P7RXDVR I
W06 VS S AE06 VSS AG18 P 4RXE RR I AJ30 P7RXD2R I
W25 VSS AE 07 P0TXD2R I/OAG19 P5CRSR I/O AK01 DAT A0 I/O
W26 VDD AE08 VS S AG 20 P5T XENR O AK02 C LK50 I
W27 P10T XCLK I AE09 P1C O LR I/O AG21 P5RXD0R I AK03 P0CO LR I/O
W28 P10RXE R I AE 10 VSS AG22 P6T XD2R I/O AK04 P0T XD1R I/O
W29 P10RXC LK I AE11 P1RXD2R I AG23 P6RXERR I AK05 P0RXC LKR I/O
W30 P10RXDV I AE12 VS S AG24 P6RXD3R I AK06 P0RXD2R I

Y01 DAT A20 I/O AE13 P 2RXD0R I AG25 P7T XD2R I/O AK07 P1T XD1R I/O

Y02 DAT A19 I/OAE14 VSS AG26P7TXCLKRI/OAK08 P1RXERR I

Y03 ADDR9 O AE15 VS S AG27 P7RXD1R I AK09 P 1RXD0R I

Y04 ADDR10 O AE16 P4CRS R I/O AG28 P8CRS I AK10 P2T XD3R I/O

Y05 VDD AE 17 VSS AG29 P8T XD1 O AK11 P2T XE NR O

Y06 VSS AE 18 P4RXD3R I AG30 P8TXEN O AK12 P2RXDVR I

Y25 P 9RXD2 I AE19 VS S AH01 DAT A4 I/ OAK13 P3COLR I/O

Y26 P9RXD3 I AE20 P5RXD2R I AH02 DAT A3 I/O AK14 P3T XD0R I/O

Y27 P10T XD2 O AE21 VSS AH03 MDIO I/OAK15 P3RXCLKR I/O

Y28 P10T XD1 O AE22 P6RXDVR I AH04 WCHDO G O AK16 P3RXDVR I

Y29 P10T XD0 O AE23 VSS AH05 P0T XCLKR I/OAK17 P4COLR I/O

Y30 P 10T XEN O AE24 VS S AH06 P0RXD0R I AK18 P4T XD0R I/O

AA01 DAT A18 I/ O AE 25 VS S AH07 P0RXD3R I AK19 P4RXCLKR I/O
AA02 DAT A17 I/ O AE26 P8T XD3 O AH08 P1T XD0R I/O AK20 P4RXD1R I
AA03 VDD AE27 P 8T XCLK I AH09 P1RXCLKR I/O AK21 P 5T XD2R I/ O
AA04 VS S AE 28 P8RXD2 I AH10 P2CRS R I/O AK22 P5T XD0R I/ O
AA05 VDD AE 29 P8RXD3 I AH11 P2T XD1R I/ OAK23 P5RXCLKR I/O
AA06 VS S AE30 P 9CRS I AH12 P2RX E RR I AK 24 P 6CRS R I/O
AA25 VS S AF01 DAT A8 I/ O AH13 P 2RXD3R I AK25 P6T XD3R I/O
AA26 VDD AF02 DAT A7 I/ O AH14 P3T XD2R I/ OAK26 P6TXENR O
AA27 P9RXD1 I AF03 C PUDI I AH15 P3T XCLKR I/ O AK27 P6RXD1R I
AA28 P10CRS I AF 04 CPUDO I/O AH16 P3RXD1R I A K28 P 7COLR I/O
AA29 P10COL I AF 05 VDD AH17 P 4T XD2R I/ OAK29 P7TXENR O
AA30 P10T X D3 O AF06 P0CRSR I/ OAH18P4TXCLKRI/OAK30 P7RXCLKR I/O

Signal

Name

I/O

Type

Pin

Signal

Name

I/O

Type

Pin

Signal

Name

I/O

Type

Pin

Signal

Name

I/O

Type

Data Sheet: ACD82124

INTRODUCTORY

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

29

Pin List By Name (With Voltage Rating): Part 1

Signal

Name

ADDR0 H03 3.3V O DAT A41 J02 3.3V I/O P03CRS R AJ13 3.3V I/O P07T XD3R AH26 3.3V I/O
ADDR01 J03 3.3V O DAT A43 H02 3.3V I/O P03RXD0R AJ16 3.3V I P08C O L AF27 3.3V I
ADDR02 K03 3.3V O DAT A44 H01 3.3V I/O P03RXD1R AH16 3.3V I P08CRS AG28 3.3V I
ADDR03 L03 3.3V O DAT A45 G02 3.3V I/O P03RXD2R AG16 3.3V I P08RXCLK AF28 3.3V I
ADDR04 R03 3.3V O DAT A46 G01 3.3V I/ O P03RXD3R AF16 3.3V I P08RXD0 AF30 3.3V I
ADDR05 T 03 3.3V O DAT A47 F02 3.3V I/O P03RXDVR AK16 3.3V I P08RXD1 AD27 3.3V I
ADDR06 U03 3.3V O DAT A48 F01 3.3V I/O P03RXERR AG15 3.3V I P08RXD2 AE28 3.3V I
ADDR07 V03 3.3V O DAT A49 E 02 3.3V I/OP03TXCLKRAH153.3VI/O P08RXD3 AE 29 3.3V I
ADDR08 W03 3.3V O DAT A50 E 01 3.3V I/O P03T XD0R AK14 3.3V I/O P08RXDV AF29 3.3V I
ADDR09 Y03 3.3V O DAT A51 D02 3.3V I/ O P 03T XD1R AJ14 3.3V I/O P08RXER AD26 3.3V I
ADDR10 Y04 3.3V O L ED0 AC04 3.3V I/O P03T XD2R AH14 3.3V I/O P08T XC LK AE 27 3.3V I
ADDR11 W04 3.3V O L ED1 AD03 3.3V I/O P 03T XD3R AG14 3.3V I/O P08T XD0 AD25 3.3V O
ADDR12 V04 3.3V O L ED2 AC 03 3.3V I/O P03T XENR AJ15 3.3V O P08T XD1 AG29 3.3V O
ADDR13 U04 3.3V O LE D3 AB04 3.3V I/O P04COL R AK17 3.3V I/O P08T XD2 AH30 3.3V O
ADDR14 T 04 3.3V O LE DC LK AE04 3.3V I/O P04CRS R AE16 3.3V I/O P08T XD3 AE26 3.3V O
ADDR15 N04 3.3V O LE DVL D0 AD04 3.3V I/OP04RXCLKRAK193.3VI/O P08T XEN AG30 3.3V O
ADDR16 M04 3.3V O L EDVLD1 AE 03 3.3V I/O P04RXD0R AH19 3.3V I P09C O L AD28 3.3V I

ARLC LK F04 3.3V O MDC AG04 3.3V O P04RXD1R AK20 3.3V I P09CRS AE 30 3.3V I

ARLDI0 D03 3.3V I MDIO AH03 3.3V I/O P04RXD2R AF18 3.3V I P09RXCLK AB28 3.3V I
ARLDI1 E 04 3.3V I nCS0 M03 3.3V O P 04RXD3R AE 18 3.3V I P09RXD0 AB30 3.3V I
ARLDI2 E 03 3.3V I nCS1 J04 3.3V O P04RXDVR AJ19 3.3V I P09RXD1 AA27 3.3V I

ARLDI3 F 03 3.3V I nC S2 L04 3.3V O P 04RXE RR AG18 3.3V I P09RXD2 Y25 3.3V I
ARLDIR0 G 03 3.3V O nC S3 K04 3.3V O P04T XCLKR AH18 3.3V I/O P09RXD3 Y26 3.3V I
ARLDIR1 G 04 3.3V O nOE R04 3.3V I/O P 04T XD0R AK18 3.3V I/O P09RXDV AB29 3.3V I

ARLDIV H04 3.3V I nRES ET AG05 3.3V I P04T XD1R AG17 3.3V I/O P09RXER AC 30 3.3V I

ARLS Y NC F05 3.3V O nWE P03 3.3V O P 04T XD2R AH17 3.3V I/O P09T XCLK AB27 3.3V I

CLK50 AK02 3.3V I P00COL R AK03 3.3V I/O P04T XD3R AJ17 3.3V I/O P 09T XD0 AC28 3.3V O

CPUDI AF03 3.3V I P00CRSR AF06 3.3V I/O P04T XENR AJ18 3.3V O P09T XD1 AD30 3.3V O
CP U DO AF 04 3.3V I/OP00RXCLKRAK053.3VI/O P05C O LR AJ20 3.3V I/O P09T XD2 AD29 3.3V O
CPUIRQ AG03 3.3V O P00RXD0R AH06 3.3V I P05C RS R AG19 3.3V I/O P 09T XD3 AC27 3.3V O

DAT A0 AK01 3.3V I/O P00RXD1R AJ06 3.3V I P05RXCLKR AK23 3.3V I/O P09T XE N AC29 3.3V O
DAT A01 AJ02 3.3V I/O P00RXD2R AK06 3.3V I P05RXD0R AG21 3.3V I P10COL AA29 3.3V I
DAT A02 AJ01 3.3V I/O P00RXD3R AH07 3.3V I P05RXD1R AF20 3.3V I P10C RS AA28 3.3V I
DAT A03 AH02 3.3V I/O P00RXDVR AG07 3.3V I P05RXD2R AE 20 3.3V I P10RXCLK W29 3.3V I
DAT A04 AH01 3.3V I/O P00RXERR AJ05 3.3V I P05RXD3R AH22 3.3V I P10RXD0 V25 3.3V I
DAT A05 AG 02 3.3V I/OP00TXCLKRAH053.3VI/O P05RXDVR AJ23 3.3V I P10RXD1 V26 3.3V I
DAT A06 AG 01 3.3V I/O P00T XD0R AG06 3.3V I/O P05RXERR AJ22 3.3V I P10RXD2 V27 3.3V I
DAT A07 AF02 3.3V I/O P00T XD1R AK04 3.3V I/OP05TXCLKRAH213.3VI/O P10RXD3 V28 3.3V I
DAT A08 AF01 3.3V I/O P00T XD2R AE07 3.3V I/O P 05T XD0R AK22 3.3V I/O P10RXDV W30 3.3V I
DAT A09 AE 02 3.3V I/O P00T XD3R AJ04 3.3V I/O P 05T XD1R AJ21 3.3V I/O P10RXER W28 3.3V I
DAT A10 AE 01 3.3V I/O P00T XE NR AF07 3.3V O P05T XD2R AK21 3.3V I/O P 10T XC LK W27 3.3V I
DAT A11 AD02 3.3V I/O P01C RS R AG08 3.3V I/O P05T XD3R AH20 3.3V I/O P10T XD0 Y29 3.3V O
DAT A12 AD01 3.3V I/OP01RXCLKRAH093.3VI/O P05T XENR AG20 3.3V O P10T XD1 Y28 3.3V O
DAT A13 AC02 3.3V I/O P01RXD0R AK09 3.3V I P06C O LR AJ24 3.3V I/O P10T XD2 Y27 3.3V O
DAT A14 AC01 3.3V I/O P01RXD1R AG 10 3.3V I P06C RS R AK24 3.3V I/O P10T XD3 AA30 3.3V O
DAT A15 AB02 3.3V I/O P01RXD2R AE11 3.3V I P06RXCLKR AF22 3.3V I/O P10T XEN Y30 3.3V O
DAT A16 AB01 3.3V I/O P01RXD3R AF11 3.3V I P06RXD0R AJ26 3.3V I P11CO L V30 3.3V I
DAT A17 AA02 3.3V I/ O P01RXDVR AJ09 3.3V I P06RXD1R AK27 3.3V I P11CRS V29 3.3V I
DAT A18 AA01 3.3V I/ O P01RXE RR AK08 3.3V I P 06RXD2R AH25 3.3V I P11RXCLK T 30 3.3V I
DAT A19 Y 02 3.3V I/ OP01TXCLKRAG093.3VI/O P06RXD3R AG24 3.3V I P11RXD0 R29 3.3V I
DAT A20 Y 01 3.3V I/ O P 01T XD0R AH08 3.3V I/O P06RXDVR AE 22 3.3V I P11RXD1 R28 3.3V I
DAT A21 W02 3.3V I/ O P01T XD1R AK07 3.3V I/O P06RXERR AG23 3.3V I P 11RXD2 R27 3.3V I
DAT A22 W01 3.3V I/ O P01T XD2R AJ07 3.3V I/OP06TXCLKRAH243.3VI/O P11RXD3 R26 3.3V I
DAT A23 V02 3.3V I/O P01T XD3R AF09 3.3V I/O P06T XD0R AJ25 3.3V I/O P11RXDV R30 3.3V I
DAT A24 V01 3.3V I/O P 01T XENR AJ08 3.3V O P06T XD1R AH23 3.3V I/O P11RXER T 27 3.3V I
DAT A25 U02 3.3V I/O P02CO LR AJ10 3.3V I/O P06T XD2R AG22 3.3V I/O P11T XCLK T 28 3.3V I
DAT A26 U01 3.3V I/O P02CRS R AH10 3.3V I/O P06T XD3R AK25 3.3V I/O P11T XD0 U30 3.3V O
DATA27 T02 3.3V I/OP02RXCLKRAJ123.3VI/O P06T XE NR AK26 3.3V O P11T XD1 U29 3.3V O
DATA28 T01 3.3V I/O P02RXD0R AE13 3.3V I P07C O LR AK28 3.3V I/O P11T XD2 U28 3.3V O
DAT A29 R02 3.3V I/O P02RXD1R AF13 3.3V I P07C RS R AJ27 3.3V I/O P11T XD3 U27 3.3V O
DAT A30 R01 3.3V I/O P02RXD2R AG13 3.3V I P07RXCLK R AK30 3.3V I/O P11T XEN T 29 3.3V O
DAT A31 P 02 3.3V I/ O P 02RXD3R AH13 3.3V I P07RXD0R AH28 3.3V I P12C O L P30 3.3V I
DAT A32 P 01 3.3V I/ O P02RXDVR AK12 3.3V I P07RXD1R AG 27 3.3V I P12CRS R25 3.3V I
DAT A33 N02 3.3V I/O P02RXERR AH12 3.3V I P07RXD2R AJ30 3.3V I P12RXCLK M30 3.3V I
DAT A34 N01 3.3V I/OP02TXCLKRAG123.3VI/O P07RXD3R AH29 3.3V I P12RXD0 M28 3.3V I
DAT A35 M02 3.3V I/O P 02T XD0R AJ11 3.3V I/O P07RXDVR AJ29 3.3V I P12RXD1 L 30 3.3V I
DAT A36 M01 3.3V I/O P 02T XD1R AH11 3.3V I/O P07RXE RR AF 25 3.3V I P12RXD2 N26 3.3V I
DAT A37 L 02 3.3V I/O P 02T XD2R AG11 3.3V I/OP07TXCLKRAG263.3VI/O P12RXD3 N25 3.3V I
DAT A38 L 01 3.3V I/O P 02T XD3R AK10 3.3V I/O P07T XD0R AJ28 3.3V I/O P12RXDV M29 3.3V I
DAT A39 K 02 3.3V I/ O P02T XENR AK11 3.3V O P07T XD1R AF24 3.3V I/O P 12RXE R N27 3.3V I
DAT A40 K 01 3.3V I/ O P03CO LR AK13 3.3V I/O P07T XD2R AG25 3.3V I/O P12T XC LK N28 3.3V I
DAT A42 J01 3.3V I/OP03RXCLKRAK153.3VI/O P07T XENR AK29 3.3V O P12T XD0 N30 3.3V O

Pin I/O Type

Signal

Name

Pin I/O Type

Signal

Name

Pin I/O Type

Signal

Name

Pin I/O Type

Data Sheet: ACD82124

INTRODUCTORY

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

30

Pin List By Name (With Voltage Rating): Part 2

Signal

Name

P12T XD1 P27 3.3V O P17RXER A24 3.3V I P22RXD1R F 09 3.3V I VDD Y05 3.3V Power
P12T XD2 P28 3.3V O P17T XCLK B24 3.3V I P22RXD2R B05 3.3V I VDD AB26 3.3V Power
P12T XD3 P29 3.3V O P17T XD0 F 22 3.3V O P22RXD3R A04 3.3V I VDD AF 05 3.3V Power

P12T XEN N29 3.3V O P17T XD1 D23 3.3V O P22RXDVR D08 3.3V I VDD AF 12 3.3V Power

P13C OL L 29 3.3V I P17T XD2 C24 3.3V O P22RXERR A05 3.3V I VDD AF 19 3.3V Power

P13C RS M27 3.3V I P17T XD3 A25 3.3V O P22T XCLKR B06 3.3V I/O VDD AF26 3.3V Po wer

P13RXCLK H30 3.3V I P17T XEN E 22 3.3V O P22T XD0R D09 3.3V O VDD E05 3.3V Po wer

P13RXD0 K27 3.3V I P18CO L D21 3.3V I P22T XD1R A06 3.3V O VDD E12 3.3V Power
P13RXD1 L26 3.3V I P18CRS A22 3.3V I P22T XD2R B07 3.3V O VDD E19 3.3V Power
P13RXD2 L25 3.3V I P18RXC LK B 20 3.3V I P22T XD3R A07 3.3V O VDD E26 3.3V P owe r

P13RXD3 J28 3.3V I P18RXD0 D19 3.3V I P22T XENR C08 3.3V O VDD M05 3.3V P owe r
P13RXDV H29 3.3V I P18RXD1 C19 3.3V I P23CO LR D07 3.3V I/OVDDM263.3VPower
P13RXE R J29 3.3V I P18RXD2 F18 3.3V I P23CRS R C06 3.3V I/OVDDW053.3VPower

P13T XCLK K28 3.3V I P18RXD3 E18 3.3V I P 23RXCLKR D05 3.3V I/OVDDW263.3VPower

P13T XD0 J30 3.3V O P18RXDV A20 3.3V I P23RXD0R A01 3.3V I VSS A19 Ground

P13T XD1 K29 3.3V O P18RXER C20 3.3V I P23RXD1R B02 3.3V I VSS AA04 Ground

P13T XD2 K30 3.3V O P18T XCLK D20 3.3V I P23RXD2R C 03 3.3V I VS S AA06 Ground

P13T XD3 L 28 3.3V O P18T XD0 B21 3.3V O P23RXD3R D04 3.3V I VSS AA25 Ground
P13T XEN L27 3.3V O P18T XD1 C 21 3.3V O P 23RXDVR E 06 3.3V I VSS AB06 Ground

P14C OL G29 3.3V I P 18T XD2 E 20 3.3V O P23RXERR F07 3.3V I VSS AB25 Ground
P14C RS G30 3.3V I P 18T XD3 F20 3.3V O P23T XCLKR B03 3.3V I/OVSSAC06 Ground

P14RXCLK J26 3.3V I P 18T XEN A21 3.3V O P23T XD0R D06 3.3V O VS S AC25 Ground

P14RXD0 E 29 3.3V I P19C OL C18 3.3V I P 23T XD1R C05 3.3V O VS S AD06 Ground

P14RXD1 D30 3.3V I P19CRS D18 3.3V I P23T XD2R A03 3.3V O VSS AE 05 Ground

P14RXD2 F28 3.3V I P19RXCLK C16 3.3V I P23T XD3R B 04 3.3V O VS S AE06 Ground

P14RXD3 G27 3.3V I P 19RXD0 A16 3.3V I P23T XE NR E 07 3.3V O VS S AE 08 Ground
P14RXDV J25 3.3V I P19RXD1 A15 3.3V I S T AT 0 B01 3.3V O VS S AE10 Ground
P14RXE R H27 3.3V I P19RXD2 B15 3.3V I S T AT 1 C 01 3.3V O VSS AE12 Ground

P14T XCLK G28 3.3V I P 19RXD3 C 15 3.3V I S T AT 2 C 02 3.3V O VSS AE 14 Ground

P14T XD0 F 29 3.3V O P19RXDV D16 3.3V I ST AT 3 D01 3.3V O VS S AE15 Ground

P14T XD1 H28 3.3V O P 19RXE R B16 3.3V I VDD A02 3.3V Power VS S AE17 Ground

P14T XD2 J27 3.3V O P19T XCLK A17 3.3V I VDD AA03 3.3V Power VS S AE19 Ground

P14T XD3 F 30 3.3V O P19T XD0 C17 3.3V O VDD AA05 3.3V Power VS S AE 21 Ground
P14T XEN E 30 3.3V O P19T XD1 D17 3.3V O VDD AA26 3.3V Power VS S AE23 Ground

P15C OL C30 3.3V I P19T XD2 A18 3.3V O VDD AB03 3.3V Power VS S AE 24 Ground
P15C RS D29 3.3V I P19T XD3 B18 3.3V O VDD AB05 3.3V Po wer VS S AE25 Ground

P15RXCLK E 27 3.3V I P19T XEN B17 3.3V O VDD AC05 3.3V Power VS S AJ03 Ground

P15RXD0 A30 3.3V I P 1COLR AE09 3.3V I/O VDD AC26 3.3V Po wer VS S C 04 Ground

P15RXD1 B29 3.3V I P20COL E 15 3.3V I VDD AD05 3.3V Power VS S F 06 G ro und

P15RXD2 C28 3.3V I P20C RS D15 3.3V I VDD AF08 3.3V Power VS S F08 Ground

P15RXD3 D27 3.3V I P20RXCLK C13 3.3V I VDD AF10 3.3V Po wer VS S F 10 Ground
P15RXDV F 26 3.3V I P20RXD0 A12 3.3V I VDD AF14 3.3V Power VS S F12 Ground
P15RXE R G25 3.3V I P20RXD1 B 12 3.3V I VDD AF15 3.3V Po wer VS S F 14 Ground

P15T XCLK D28 3.3V I P 20RXD2 C12 3.3V I VDD AF17 3.3V Power VS S F16 Ground

P15T XD0 C29 3.3V O P20RXD3 A11 3.3V I VDD AF21 3.3V Po wer VS S F 17 Ground

P15T XD1 G26 3.3V O P20RXDV D13 3.3V I VDD AF23 3.3V Power VS S F19 Ground

P15T XD2 F 27 3.3V O P20RXER B13 3.3V I VDD AH27 3.3V Power VS S F21 Ground

P15T XD3 E 28 3.3V O P20T XCLK A13 3.3V I VDD B19 3.3V Power VS S F 23 Ground
P15T XEN B30 3.3V O P20T XD0 C 14 3.3V O VDD E 08 3.3V Power VS S F25 Ground

P16C OL B28 3.3V I P20T XD1 B14 3.3V O VDD E 10 3.3V Power VS S G06 Ground
P16C RS A29 3.3V I P20T XD2 A14 3.3V O VDD E 14 3.3V Power VS S H06 Ground

P16RXCLK D25 3.3V I P20T XD3 F15 3.3V O VDD E 16 3.3V Power VS S H25 Ground

P16RXD0 C26 3.3V I P20T XEN D14 3.3V O VDD E17 3.3V P ower VS S J06 Ground

P16RXD1 B26 3.3V I P21COL F13 3.3V I VDD E21 3.3V Po wer VS S K06 G ro und

P16RXD2 A26 3.3V I P21CRS E 13 3.3V I VDD E 23 3.3V P owe r VS S K 25 Ground

P16RXD3 D24 3.3V I P21RXCLK C10 3.3V I VDD G05 3.3V P ower VS S L 06 Ground
P16RXDV E 24 3.3V I P21RXD0 A08 3.3V I VDD H05 3.3V Po wer VS S M06 Ground
P16RXE R A27 3.3V I P21RXD1 B 08 3.3V I VDD H26 3.3V Power VS S M25 Ground

P16T XCLK F24 3.3V I P 21RXD2 D10 3.3V I VDD J05 3.3V Power VS S N06 G ro und

P16T XD0 A28 3.3V O P21RXD3 E 11 3.3V I VDD K 05 3.3V Power VS S P04 Gro und

P16T XD1 E 25 3.3V O P21RXDV B 09 3.3V I VDD K 26 3.3V Power VS S P06 Gro und

P16T XD2 D26 3.3V O P21RXER D11 3.3V I VDD L05 3.3V Power VS S P25 G ro und

P16T XD3 C27 3.3V O P21T XC LK A09 3.3V I VDD N03 3.3V Power VS S R06 G ro und
P16T XEN B27 3.3V O P21T XD0 A10 3.3V O VDD N05 3.3V Power VS S T 06 Ground

P17C OL B25 3.3V I P21T XD1 C11 3.3V O VDD P05 3.3V Power VS S T 25 Ground
P17C RS C25 3.3V I P21T XD2 B11 3.3V O VDD P26 3.3V P ower VS S U06 Ground

P17RXCLK C23 3.3V I P 21T XD3 D12 3.3V O VDD R05 3.3V Po wer VS S U25 Ground

P17RXD0 D22 3.3V I P21T XEN B10 3.3V O VDD T 05 3.3V Power VS S V06 Ground

P17RXD1 A23 3.3V I P22C OL R C09 3.3V I/O VDD T 26 3.3V P ower VS S W 06 Gr ound

P17RXD2 C22 3.3V I P22CRS R F11 3.3V I/O VDD U05 3.3V P ower VS S W 25 Gr ound

P17RXD3 B22 3.3V I P22RXC LK R C07 3.3V I/O VDD U 26 3.3V P ower VS S Y 06 Ground
P17RXDV B 23 3.3V I P22RXD0R E 09 3.3V I VDD V05 3.3V Power WCHDOG AH04 O

Pin I/ O Type

Signal

Name

Pin I/ O Type

Signal

Name

Pin I/ O Type

Signal

Name

Pin I/ O Type

Data Sheet: ACD82124

INTRODUCTORY

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

31

9. TIMING DESCRIPTION

MII R eceive T im in g

RXCLK

RXDV

RXD[3:0]

RXER

M II T ra nsmit Timi n g

Data Sheet: ACD82124

t1 t2

T# Description: MIN TYP MAX UNIT

t1 RX_DV, RXD, RX_ER setup time 5 - - ns
t2 RX_DV, RXD, RX_ER hold time 5 - - ns

INTRODUCTORY

TXCLK

TXEN

TXD[3:0]

t2t1

T# Desciption M in Typ Max Unit

t1 TXEN, TXD setup time 10 - - ns
t2 TXEN, TXD hold time 10 - - ns

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

32

Rev e rs e d MII Receive T im ing

RXCLK

RXDV

RXD[3:0]

T# Description: MIN TYP MAX UNIT

t1 RXDV, RXD se tup time 10 - ns

T2 RXDV, RXD hold time 10 ns

Data Sheet: ACD82124

t1 t2

Reversed MII Transmit Timing

TXCLK

TXEN

TXD[3:0]

T# Description: MIN TYP MAX UNIT

t1 RXDV, RXD setup time 5 - ns

T2 RXDV, RXD hold time 5 ns

INTRODUCTORY

t1 t2

33

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Reversed MII Packet Timing (Start of Packet)

RXCLK

RXDV

RXD[3:0]

Data Sheet: ACD82124

t1

T# Desciption Min Typ Max Unit

t1 RXD to RXDV 0 - - ns

Reversed MII Packet Timing (End of Packet)

RXCLK

RXDV

RXD[3:0]

INTRODUCTORY

t1

T# Desciption Min Typ Max Unit

t1 PXD to RXDV delay time 0 - - ns

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

34

PHY Management Read Timing

MDC

MDIO

t1

t2

Data Sheet: ACD82124

T# Description MIN TYP MAX UNIT

t1 MDIO setup time 0 - 300 ns
t2 M DC cycle - 800 - n s

PHY Management Write Timing

MDC

MDIO

t3

t2

t4

t1

T# Description MIN TYP MAX UNIT

t1 MDC High time - 400 - ns
t2 MDC Low time - 400 - ns
t3 MDC period - 800 - ns
t4 MDIO s e t up time 1 0 - - ns
t5 MDIO hold time 10 - - ns

INTRODUCTORY

t5

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

35

ASRA M Read T iming

ADDRESS

__

OE

__

CE

t1

t2 t3

Data Sheet: ACD82124

t4

t6

SRAM R ead Tim ing

DATA

ASRAM Write Timing

ADDRESS

__

CE

___
WE

VALID DATA

t7

t5

T# Description M IN TY P MAX UN IT

t1 Read cycle time - 20 - ns
t2 Address access time - - 12 ns
t3 Output hold time 0 - - ns
t4 O E access time - - 12 ns
t5 CE access tim e - - 12 ns
t6 OE to L o w -Z ou tp u t 0 - - ns
t7 CE to Low-Z output 0 - - ns
t8 OE to High-Z output - - 6 ns
t9 CE to High-Z output - - 6 ns

t8

t9

t1

t2 t3

t4

t5

t6

t8t7

HIGH-ZHIGH-Z

INTRODUCTORY

DATA

VALID DATA

T# Description MIN TYP MAX UNIT

t1 W rite cycle time - 20 - ns
t2 A ddress S etup to Write End time 12 - - ns
t3 Address hold for Write End time 0 - - ns
t4 CE to Write End time 12 - - ns
t5 A ddress S etup time 4 - - ns
t6 WE pulse width 8 - - ns
t7 Data Setu p to W rit e E n d 8 - - ns
t8 D a ta H o ld f or Write E n d 0 - - ns

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

36

CPU C omm and Tim ing

t1

t4

t2

CPUDI

CPUDO

bit

6

ARL Result Timing

bit

7

stop

bit

idle state

start

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

bit

T# Description MIN TYP MAX UNIT

t1 CP U idle time 0 - - us
t2 CPU command bit time 10 - - us
t3 Respo n se t im e 0 - 20 m s
t4 Command time - - 2 0 ms

stop

bit

stop

bit

t3

start

bit

Data Sheet: ACD82124

bit0

INTRODUCTORY

ARLCLK

ARLDO

ARLDI

DA1

DA2

t1

Result1

t2 t3

T# Description MIN TYP MAX UNIT

t1 time between DAs 0 - - ns
t2 tim e f or ARL result 0 - 200 ns
t3 time between res ults 0 - - ns

Result2

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

37

LED Signal Timing

LEDCLK

LEDVLD0

LEDVLD1

nLED0

FDX

FDX

LNK

SPD

LNK

FDX

SPD

LNK

nLED1

nLED2

nLED3

SPD

P22

P23

P21

10. ELECTRICAL SPECIFICATION

Absolute Maximum Ratings

FDX

FDX

FDX

SPD

SPD

SPD

LNK

LNK

LNK

P2P1P0

ERR

COL

RCV

XMT

P23

ERR

COL

RCV

XMT

P22

ERR

COL

RCV

XMT

P21

ERR

ERR

ERR

COL

COL

COL

RCV

RCV

RCV

XMT

XMT

XMT

P2P1P0

Data Sheet: ACD82124

INTRODUCTORY

Operation at absolute maximum ratings is not implied.
Exposure to stresses outside those listed could cause
permanent damage to the device.

DC Supply voltage : VDD -0.3V ~ +5.0V
DC input current: Iin +/-10 mA
DC input voltage: Vin -0.3 ~ V DD + 0.3V
DC output voltage: Vout -0.3 ~ VDD + 0.3V

o

Storage temperature: Tstg -40 to +125

C

Recommended Operation Conditions

Supply voltage: VDD 3.3V, +/-0.3V
Operating temperature: Ta 0

M ax imum power consumption 3.5W

o

C -70 oC

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

38

11. PACKAGING
Top View

Advanced

Comm.

Devices

FLLLLLSMAYYWW

ACD82124

Data Sheet: ACD82124

Pin - A1

Pin - A1

10
12
14

16

18

20
22

24

26
28

30

o.56

1

2

3

4

5

6

7

8

9

11

13

15

17

19

21

23

25
27

29

34.50

40.00+/-0.20

Side View

INTRODUCTORY

0.60+/-0.05

Bottom View

AG

AE

AC

AA

AD

A

K

J

H

G

1.27

R

P

N

M

L

U

T

0.75+/-0.15

F

E

D

C

B

AB

Y

W

V

36.83

AJ

AK

AH

AF

2.33+/-0.13

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

39

Appendix-A1

Address Resolution Logic

(The built-in ARL with 2048 MAC Addresses)

Data Sheet: ACD82124

INTRODUCTORY

40

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

1. SUMMARY

2. FEA TURES

The internal Address Resolution Logic (ARL) of ACD’s
switch controllers automatically builds up an address
table and maps up to 2,048 MAC addresses into their
associated port. It can work by itself without any CPU
intervention in an UN-managed system.

For a managed system, the management CPU can
configure the operation mode of the ARL, learn all the
address in the address table, add new address into
the table, control security or filtering feature of each
address entry etc.

The ARL is designed with such a high performance
that it will never slow down the frame switching opera­tion. It helps the switch controllers to reach wire speed
forwarding rate under any type of traffic load.

The address space can be expanded to 11K entries
by using the external ARL, the ACD80800.

Figure-1. ARL Block Diagram

• Supports up to 2,048 MAC address lookup

• Provides UART type of interface for the manage-

ment CPU

• Wire speed address lookup time.

• Wire speed address learning time.

• Address can be automatically learned from switch

without the CPU intervention

• Address can be manually added by the CPU
through the CPU interface

• Each MAC address can be secured by the CPU
from being changed or aged out

• Each MAC address can be marked by the CPU
from receiving any frame

• Each newly learned MAC address is notified to
the CPU

• Each aged out MAC address is notified to the CPU

• Automatic address aging control, with configurable

aging period

Data Sheet: ACD82124

Address

Learning

Engine

Switch Interface

Address

Aging

Engine

Address

Lookup
Engine

Address Table

(2048 Entries)

CPU Interface

Address

Registers

Data

Registers

CPU Interface Engine

Registers

Command

Control

Registers

INTRODUCTORY

41

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

3. FUNCTIONAL DESCRIPTION

Address Lookup

The ARL provides Address Resolution service for
ACD’s switch controllers.
of the ARL.

Traffic Snooping
All Ethernet frames received by ACD’s switch control-

ler have to be stored into memory buffer. As the frame
data are written into memory, the status of the data
shown on the data bus are displayed by ACD’s switch
controller through a state bus. The ARL’s Switch Con­troller Interface contains the signals of the data bus
and the state bus. By snooping the data bus and the
state bus of ACD’s switch controller , the ARL can de­tect the occurrence of any destination MAC address
and source MAC address embedded inside each frame.

Address Learning
Each source address caught from the data bus, to-

gether with the ID of the ingress port, is passed to the
Address Learning Engine of the ARL. The Address
Learning Engine will first determine whether the frame
is a valid frame. For a valid frame, it will first try to find
the source address from the current address table. If
that address doesn’t exist, or if it does exist but the
port ID associated with the MAC address is not the
ingress port, the address will be learned into the ad­dress table. After an address is learned by the ad­dress learning engine, the CPU will be notified to read
this newly learned address so that it can add it into the
CPU’s address table.

Address Aging
After each source address is learned into the address

table, it has to be refreshed at least once within each
address aging period. Refresh means it is caught again
from the switch interface. If it has not occurred for a
pre-set aging period, the address aging engine will
remove the address from the address table. After an
address is removed by the address aging engine, the
CPU will be notified through interrupt request that it
needs to read this aged out address so that it can
remove this address from the CPU’s address table.

Figure 2

is a block diagram

Each destination address is passed to the Address
Lookup Engine of the ARL. The Address Lookup En­gine checks if the destination address matches with
any existing address in the address table. If it does,
the ARL returns the associated Port ID to ACD’s switch
controller through the output data bus. Otherwise, a
no match result is passed to ACD’s switch controller
through the output data bus.

CPU Interface
The CPU can access the registers of the ARL by send-

ing commands to the UART data input line. Each com­mand is consisted by action (read or write), register
type, register index, and data. Each result of com­mand execution is returned to the CPU through the
UART data output line.

CPU Interface Registers
The ARL provides a bunch of registers for the control

CPU. Through the registers, the CPU can read all ad­dress entries of the address table, delete particular
addresses from the table, add particular addresses
into the table, secure an address from being changed,
set filtering on some addresses, change the hashing
algorithm etc. Through a proper interrupt request sig­nal, the CPU can be notified whenever it needs to
retrieve data for a newly-learned address or an aged­out address so that the CPU can build an exact same
address table learned by the ARL.

CPU Interface Engine
The command sent by the control CPU is executed by

the CPU Interface Engine. For example, the CPU may
send a command to learn the first newly-learned ad­dress. The CPU Interface Engine is responsible to
find the newly-learned address from the address table,
and passes it to CPU. The CPU may request to learn
next newly-learned address. Then, it is again the re­sponsibility of the CPU Interface Engine to search for
next newly-learned address from the address table.

Address T able

Data Sheet: ACD82124

INTRODUCTORY

The address table can hold up to 2,048 MAC ad­dresses, together with the associated port ID, security
flag, filtering flag, new flag, aging information etc. The
address table resides in the embedded SRAM inside
the ARL.

42

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

4. INTERFACE DESCRIPTION

CPU Interface

UARTDO is used to return the result of command ex­ecution to the CPU. The format of the result packet is
shown as follows:

The CPU can communicate with the ARL through the
UART interface of the switch IC. The management CPU
can send command to the ARL by writing into associ­ated registers, and retrieve result from ARL by read­ing corresponding registers. The registers are de­scribed in the section of “Register Description.” The
CPU interface signals are described by

table-1

:

Table-1: CPU Interface

Name I/O Description

UA RTDI I UA RT input data line.
UA RTDO O UART output data line.

UARTDI is used by the control CPU to send command
into the ARL. The baud rate will be automatically de­tected by the ARL. The result will be returned through
the UARTDO line with the detected baud rate. The for­mat of the command packet is shown as follows:

Header Address Data Checksum

Header Address Data Checksum

where:

• Header is further defined as:

b1:b0 - read or write, 01 for read, 1 1
for write
b4:b2 - device number, 000 to 111 (0
to 7)
b7:b5 - device type, 010 for ARL

• Address - 8-bit value for address of the
selected register

• Data - 32-bit value, only the LSB is used
for read operation, all 0 for write opera­tion

• Checksum - 8-bit value of XOR of all bytes

The ARL will always check the CMD header to see if
both the device type and the device number matches
with its setting. If not, it ignores the command and will
not generate any response to this command.

Data Sheet: ACD82124

where:

INTRODUCTORY

• Header is further defined as:

b1:b0 - read or write, 01 for read, 11
for write
b4:b2 - device number, 000 to 111 (0
to 7, same as the host switch con­troller)
b7:b5 - device type, 010 for ARL

• Address - 8-bit value used to select the
register to access

• Data - 32-bit value, only the LSB is used
for write operation, all 0 for read opera­tion

• Checksum - 8-bit value of XOR of all bytes

43

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5. REGISTER DESCRIPTION

ACD80800 provides a bunch of registers for the CPU
to access the address table inside it. Command is sent
to ACD80800 by writing into the associated registers.
Before the CPU can pass a command to ACD80800,
it must check the result register

(register 11)

to see if
the command has been done. When the Result regis­ter indicates the command has been done, the CPU
may need to retrieve the result of previous command
first. After that, the CPU has to write the associated
parameter of the command into the Data registers.
Then, the CPU can write the command type into the
command register. When a new command is written
into the command register, ACD80800 will change the
status of the Result register to 0. The Result register
will indicate the completion of the command at the end
of the execution. Before the completion of the execu­tion, any command written into the command register
is ignored by ACD80800.

The registers accessible to the CPU are described by

table-2

:

Table-2: R egist er Descr iption

Re g. Name De scription

0 DataReg0 Byte 0 of data
1 DataReg1 Byte 1 of data
2 DataReg2 Byte 2 of data
3 DataReg3 Byte 3 of data
4 DataReg4 Byte 4 of data
5 DataReg5 Byte 5 of data
6 DataReg6 Byte 6 of data
7 DataReg7 Byte 7 of data
8 AddrReg0 LSB of address value

9 AddrReg1 MSB of address value
10 CmdReg Command register
11 RsltReg Result register
12 CfgReg Configuration register
13 IntSrcReg Interrupt source register
14 IntMskReg Interrupt mask register

15 nLearnReg0

16 nLearnReg1

17 nLearnReg2
18 AgeTimeReg0 LSB of aging period register

19 AgeTimeReg1

20 P osC fg

Address learning disable
register for port 0 - 7
Address learning disable
register for port 8 - 15
Address learning disable
register for port 16 - 23

MSB of aging period
register
Power On Strobe
configuration register 0

The

DataRegX

are registers used to pass the param­eter of the command to the ACD80800, and the result
of the command to the CPU.

The

AddrRegX

are registers used to specify the ad-

dress associated with the command.
The

CmdReg

the ACD80800. The command types are listed in

3

. The details of each command is described in the

is used to pass the type of command to

table-

chapter of “Command Description.”

Table-3: Command List

Command De scription

0x09

0x0A

0x0B

0x0C

0x0D

0x10 Read the first entry of the address table
0x11 Read next entry of address book
0x20 Read first valid entry
0x21 Read next valid entry
0x30 Read first new page
0x31 Read next new page
0x40 Read first aged page
0x41 Read next aged page
0x50 Read first locked page
0x51 Read next locked page
0x60 Read first filtered page
0x61 Read next filtered page
0x80 Read first page with specified PID
0x81 Read next page with specified PID

Add the specified MAC address into the
address table
Set a lock for the specified MAC
address
Set a filtering flag for the specified MAC
address
Delete the specified MAC address from
the address table
Assign a port ID to the specified MAC
address

0xFF System reset

The

RstReg

is used to indicate the status of command

execution. The result code is listed as follows:

•

01 - command is being executed and is
not done yet

•

10 - command is done with no error

•

1x - command is done, with error indi­cated by x, where x is a 4-bit error code:
0001 for cannot find the entry as speci­fied

Data Sheet: ACD82124

INTRODUCTORY

44

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The

CfgReg

works. The bit definition of CfgReg is described as:

The

IntSrcReg

terrupt request to CPU. The source of interrupt is listed
as:

The

IntMskReg

to generate an interrupt request. The bit definition is
the same as IntSrcReg. A 1 in a bit enables the corre­sponding interrupt source to generate an interrupt re­quest once it is set.

is used to configure the way the ACD80800

•

bit 0 - disable address aging

•

bit 1 - disable address lookup

•

bit 2 - disable DA cache

•

bit 3 - disable SA cache

•

bit 7:4 - hashing algorithm selection, de­fault is 0000

is used to indicate what can cause in-

•

bit 0 - aged address exists

•

bit 1 - new address exists

•

bit 2 - reserved

•

bit 3 - reserved

•

bit 4 - bucket overflowed

•

bit 5 - command is done

•

bit 6 - system initialization is completed

•

bit 7 - self test failure

is used to enable an interrupt source

The

nLearnReg[2:0]

ing activity from a particular port. If the bit correspond­ing to a port is set, ACD80800 will not try to learn new
addresses from that port.

The

AgeTimeReg[1:0]

of address aging control. The aging period can be
from 0 to 65535 units, with each unit counted as 2.684
second.

The

PosCfgReg

fault value is determined by the pull-up or pull-down
status of the associated hardware pin. The bits of
PosCfgReg0 is listed as follows:

•

bit 3 – BISTEN: “0” = self test disabled,
“1” = self test enabled;

•

bit 2 - TESTEN, “0” = normal operation,
“1” = production test enabled;

•

bit 1* - NOCPU*, “0” = presence of con­trol CPU, “1” = no control CPU;

•

bit 0 - CPUGO, “0” = wait for System
Start command from CPU before start­ing self initialization, “1” = CPU ready.
Only effective when bit-1 (NOCPU) is set
to 0;

Note: When
start the initialization process until a System Start com­mand is sent to the command register.

are used to disable address learn-

are used to specify the period

is a configuration register whose de-

NOCPU

is set as 0, ACD80800 will not

Data Sheet: ACD82124

INTRODUCTORY

45

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

6. COMMAND DESCRIPTION

Command 0DH

Command 09H

Description:

address table.

Parameter:

DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. Store
the associated port number into DataReg6.

Result:

dress table if there is space available. The result is
indicated by the Result register.

Command 0AH

Description:

address.

Parameter:

DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.

Result:

matched MAC address, and set the Lock bit of the
entry . The result is indicated by the Result register .

Command 0BH

Description:

address.

Parameter:

DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.

Add the specified MAC address into the

Store the MAC address into DataReg5 -

the MAC address will be stored into the ad-

Set the Lock bit for the specified MAC

Store the MAC address into DataReg5 -

the state machine will seek for an entry with

Set the Filter flag for the specified MAC

Store the MAC address into DataReg5 -

Description:

specified MAC address.

Parameter:

DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. Store
the port number into DataReg6.

Result:

specified MAC address will be changed accordingly.
The result is indicated by the Result register.

Command 10H

Description:
Parameter:
Result:

the command is completed with no error, the content
of the first entry of the address book will be stored into
the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag* bits are stored in DataReg7.The Read Pointer
will be set to point to second entry of the address book.

Note - the Flag bits are defined as:

Assign the associated port number to the

Store the MAC address into DataReg5 -

the port ID field of the entry containing the

Read the first entry of the address table.

None

The result is indicated by the Result register. If

b7 b6 b5 b4 b3 b2 b1 b0

Rsv d Rsv d Filter Lock New Old Age Valid

Data Sheet: ACD82124

INTRODUCTORY

Result:

matched MAC address, and set the Filter bit of the
entry . The result is indicated by the Result register .

Command 0CH

Description:

the address table.

Parameter:

DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.

Result:

address table. The result is indicated by the Result
register.

the state machine will seek for an entry with

Delete the specified MAC address from

Store the MAC address into DataReg5 -

the MAC address will be removed from the

where:

• Filter - 1 indicates the frame heading to
this address should be dropped.

• Lock - 1 indicates the entry should never
be changed or aged out.

• New - 1 indicates the entry is a newly
learned address.

• Old - 1 indicates the address has been
aged out.

• Age - 1 indicates the address has not
been visited for current age cycle.

• V alid - 1 indicates the entry is a valid one.

• Rsvd - Reserved bits.

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46

Command 1 1H

Description:
Parameter:
Result:

the command is completed with no error, the content
of the address book entry pointed by Read Pointer will
be stored into the Data registers. The MAC address
will be stored into DataReg5 - DataReg0, with DataReg5
contains the MSB of the MAC address and DataReg0
contains the LSB. The port number is stored in
DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer will be increased by one.

Command 20H

Description:
Parameter:
Result:

the command is completed with no error, the content
of first valid entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry .

Command 21H

Description:
Parameter:
Result:

the command is completed with no error, the content
of next valid entry from the Read Pointer of the ad­dress book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this en­try .

Command 30H

Description:
Parameter:
Result:

the command is completed with no error, the content

Read next entry of address book.

None

The result is indicated by the Result register. If

Read first valid entry.

None

The result is indicated by the Result register. If

Read next valid entry .

None

The result is indicated by the Result register. If

Read first new page.

None

The result is indicated by the Result register. If

of first new entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry .

Command 31H

Description:
Parameter:
Result:

the command is completed with no error, the content
of next new entry from the Read Pointer of the ad­dress book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this en­try .

Command 40H

Description:
Parameter:
Result:

the command is completed with no error, the content
of first aged entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry .

Command 41H

Description:
Parameter:
Result:

the command is completed with no error, the content
of next aged entry from the Read Pointer of the ad­dress book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this en­try .

Read next new entry .

None

The result is indicated by the Result register. If

Read first aged entry.

None

The result is indicated by the Result register. If

Read next aged entry .

None

The result is indicated by the Result register. If

Data Sheet: ACD82124

INTRODUCTORY

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

47

Command 50H

Description:
Parameter:
Result:

the command is completed with no error, the content
of first locked entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry .

Read first locked entry.

None

The result is indicated by the Result register. If

of next filtered entry from the Read Pointer of the ad­dress book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this en­try .

Command 80H

Description:

ber.

Parameter:

Read first entry with specified port num-

Store port number into DataReg6.

Data Sheet: ACD82124

Command 51H

Description:
Parameter:
Result:

the command is completed with no error, the content
of next locked entry from the Read Pointer of the ad­dress book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this en­try .

Command 60H

Description:
Parameter:
Result:

the command is completed with no error, the content
of first filtered entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry .

Read next locked entry .

None

The result is indicated by the Result register. If

Read first filtered page.

None

The result is indicated by the Result register. If

Result:

the command is completed with no error, the content
of first entry of the address book with the said port
number will be stored into the Data registers. The MAC
address will be stored into DataReg5 - DataReg0, with
DataReg5 contains the MSB of the MAC address and
DataReg0 contains the LSB. The port number is stored
in DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer is set to point to this entry .

Command 81H

Description:
Parameter:
Result:

the command is completed with no error, the content
of next entry from the Read Pointer of the address
book with the said port number will be stored into the
Data registers. The MAC address will be stored into
DataReg5 - DataReg0, with DataReg5 contains the MSB
of the MAC address and DataReg0 contains the LSB.
The port number is stored in DataReg6, and the Flag
bits are stored in DataReg7. The Read Pointer is set to
point to this entry .

Command FFH

Description:
Parameter:

The result is indicated by the Result register. If

Read next valid entry .

Store port number into DataReg6.

The result is indicated by the Result register. If

System reset.

None

INTRODUCTORY

Command 61H

Description:
Parameter:
Result:

the command is completed with no error, the content

Read next valid entry .

None

The result is indicated by the Result register. If

Result:

entries of the address book will be cleared.

This command will reset the ARL system. All

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48