Datasheet ACD80800 Datasheet (ACD)

Download

Page 1

Advanced

Communication

Devices

Data Sheet: ACD80800

Address Resolution Logic

Data Sheet: ACD80800

(8K MAC Addresses)

Rev.1.0.0.E

Last Update: September 19, 2000

Please check ACD’s website for update

information before starting a design

Web site: http://www.acdcorp.com/tech.html

or Contact ACD at:

Email: support@acdcorp.com

Tel: 510-354-6810

Fax: 510-354-6834

ACD Confidential Material

For ACD authorized customer use only . No reproduction or redistribution without ACD’s prior permission.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 2

CONTENT LIST

1. SUMMARY

2. FEA TURES

3. FUNCTIONAL DESCRIPTION

4. PIN DESCRIPTION

5. INTERF ACE DESCRIPTION

6. REGISTER DESCRIPTION

7. COMMAND DESCRIPTION

8. TIMING DESCRIPTION

9. ELECTRICAL SPECIFICATION

Data Sheet: ACD80800

10. PACKAGING

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 3

1. SUMMARY

2. FEA TURES

The ACD80800 serves as an Address Resolution Logic for ACD’s switch controller chips (ACD82124, ACD82012 etc.) through a glueless ARL interface. It automatically builds up an address table and can map up to 8K MAC addresses into their associated ports.

The ACD80800 can work without a CPU in a unmanaged switch system, or with a CPU and an ACD MIB (ACD80900 Management Information Base). A direct input/output interface is integrated to support a management CPU. The CPU can configure the operation mode of the ACD80800, learn all the addresses in the address table, add new addresses into the table, control security or filtering features of each address entry , etc.

The ACD80800 is designed with such a high performance that, it will never slow down the frame switching operation conducted by the ACD’s switch controllers. T ogether with the non-blocking architecture of the ACD’s switch controllers, the chip set (a ACD switch controller plus the ACD80800, plus ACD80900 in a managed switch system) can provide wire speed forwarding rate under any type of traffic load.

• Supports up to 8K MAC address lookup

• Provides Glueless ARL Interface with ACD’s

switch controller chip

• Provides Direct Input/Output type of interface for the management CPU

• Provides UART type of interface for the management CPU

• Wire speed address lookup time.

• Wire speed address learning time.

• Address can be automatically learned from switch

without THE CPU intervention

• Address can be manually added by the CPU through the CPU interface

• Each MAC address can be secured by the CPU from being changed or aged out

• Each MAC address can be marked by the CPU from receiving any frame

• Each newly learned MAC address is notified to the CPU

• Each aged out MAC address is notified to the CPU

• Automatic address aging control, with configurable aging period

• 0.35 micron, 3.3V CMOS technology

• 128-Pin PQFP package

Data Sheet: ACD80800

Figure-1: ACD80800 Used in A Managed n-Port Fast Ethernet Switch System

P(n-1) P(n-2) P(n-3)

ACD82xxx

n-Port Fast Ethernet

Switch Controller

P1 P0

ACD80900

MIB

CPU

ACD80800

ASRAM

Address Resolution

Logic

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 4

3. FUNCTIONAL DESCRIPTION

ACD80800 provides Address Resolution service for ACD’s switch controller chip. ACD80800 provides a glueless interface with ACD’s switch controller, and is used to build an address table and provide address lookup service to ACD’s switch controller.

Figure 2

is a block

diagram of ACD80800. Traffic Snooping

Learning Engine will first determine whether the frame is a valid frame. For a valid frame, it will first try to find the source address from the current address table. If that address doesn’t exist, or if it does exist but the port ID associated with the MAC address is not the ingress port, the address will be learned into the address table. After an address is learned by the address learning engine, the CPU will be notified to read this newly learned address so that it can add it into the CPU’s address table.

Data Sheet: ACD80800

All Ethernet frames received by ACD’s switch controller have to be stored into memory buffer. As the frame data are written into memory, the status of the data shown on the data bus are displayed by ACD’s switch controller through a state bus. ACD80800’s Switch Controller Interface contains the signals of the data bus and the state bus. By snooping the data bus and the state bus of ACD’s switch controller, ACD80800 can detect the occurrence of any destination MAC address and source MAC address embedded inside each frame.

Address Learning Each source address caught from the data bus, to-

gether with the ID of the ingress port, is passed to the Address Learning Engine of ACD80800. The Address

Figure-2. ACD80800 Block Diagram

Switch Interface

Address Aging After each source address is learned into the address

table, it has to be refreshed at least once within each address aging period. Refresh means it is caught again from the switch interface. If it has not occurred for a pre-set aging period, the address aging engine will remove the address from the address table. After an address is removed by the address aging engine, the CPU will be notified through interrupt request that it needs to read this aged out address so that it can remove this address from the CPU’s address table.

Address Lookup Each destination address is passed to the Address

CPU Interface

Address

Learning

Engine

Address

Aging

Engine

Address

Lookup

Engine

Address Table

(8K Entries)

Address

Registers

Data

Registers

CPU Interface Engine

Registers

Command

Control

Registers

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 5

Lookup Engine of ACD80800. The Address Lookup Engine checks if the destination address matches with any existing address in the address table. If it does, ACD80800 returns the associated Port ID to ACD’s switch controller through the output data bus. Otherwise, a no match result is passed to ACD’s switch controller through the output data bus.

CPU Interface ACD80800 provides a direct input/output type of inter-

face for a management CPU to access various kind of registers inside ACD80800. The interface has 8-bit data bus, and 5-bit address bus. The timing of read and write operation is controlled by output enable signal and write enable signal. For details of CPU interface timing information, refer to the section of “Timing Description.”

The CPU can also choose to access the registers of ACD80800 by sending commands to the UART data input line. Each command is consisted by action (read or write), register type, register index, and data. Each result of command execution is returned to the CPU through the UART data output line.

CPU Interface Registers ACD80800 provides a bunch of registers for the control

CPU. Through the registers, the CPU can read all address entries of the address table, delete particular addresses from the table, add particular addresses into the table, secure an address from being changed, set filtering on some addresses, change the hashing algorithm etc. Through a proper interrupt request signal, the CPU can be notified whenever it needs to retrieve data for a newly-learned address or an aged-out address so that the CPU can build an exact same address table learned by ACD80800.

CPU Interface Engine The command sent by the control CPU is executed by

the CPU Interface Engine. For example, the CPU may send a command to learn the first newly-learned address. The CPU Interface Engine is responsible to find the newly-learned address from the address table, and passes it to CPU. The CPU may request to learn next newly-learned address. Then, it is again the responsibility of the CPU Interface Engine to search for next newly-learned address from the address table.

Address T able The address table can hold up to 8K MAC addresses,

together with the associated port ID, security flag, filtering flag, new flag, aging information etc. The address table resides in the embedded SRAM inside ACD80800.

Data Sheet: ACD80800

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 6

4. PIN DESCRIPTIONS

Figure-3: Pin Diagram Of ACD80800 (The ARL Chip)

CPUD7

CPUD6

CPUD5

CPUD4

CPUD3

CPUD2

CPUD1

112

111

110

CPUD0

CPUIRQ

109

108

GND

107

GND SWDI63 SWDI62 SWDI61 SWDI60 SWDI59 SWDI58 SWDI57 SWDI56 SWDI55 SWDI54 SWDI53 SWDI52 SWDI51 SWDI50 SWDI49 SWDI48

VDD

GND SWDI47 SWDI46 SWDI45 SWDI44 SWDI43 SWDI42 SWDI41 SWDI40 SWDI39 SWDI38 SWDI37 SWDI36 SWDI35 SWDI34 SWDI33 SWDI32 SWDI31 SWDI30

VDD

GND

nCPUOE

nCPUCS

nCPUWE

GND

VDD

128

125

126

127

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

39424140434544484746495251505356555457605958616463

124

CPUA3

CPUA4

122

123

CPUA2

121

CPUA0

CPUA1

120

119

118

VDD

117

116

115

114

113

VDD

UARTDO

105

106

UARTDI

GND

104

103

102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

Data Sheet: ACD80800

VDD GND WCHDOG nRESET NC SWDIR1 SWDIR0 SWSTAT3 SWSTAT2 SWSTAT1 SWSTAT0 GND VDD SWEOF SWSYNC SWPID4 SWPID3 SWPID2 SWPID1 SWPID0 SWCLK GND GND

VDD SWDO0 SWDO1 SWDO2 SWDO3 SWDOV GND VDD SWDI0 SWDI1 SWDI2 SWDI3 SWDI4 SWDI5 GND

GND

SWDI29

SWDI26

SWDI28

SWDI27

SWDI24

SWDI25

SWDI23

SWDI20

SWDI22

SWDI21

SWDI19

SWDI18

SWDI17

SWDI14

SWDI16

SWDI15

SWDI13

SWDI12

SWDI11

SWDI8

SWDI9

SWDI10

SWDI6

SWDI7

VDD

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 7

Pin Table

GND Ground. -

SWDI5 Data from switc h controller chip. 3 .3V I

SWDI4 Data from switc h controller chip. 3 .3V I

SWDI3 Data from switc h controller chip. 3 .3V I

SWDI2 Data from switc h controller chip. 3 .3V I

SWDI1 Data from switc h controller chip. 3 .3V I

SWDI0 Data from switc h controller chip. 3 .3V I

VDD 3.3V pow er s upply. -

GND Ground. -

SWDOV Output data valid signal t o switch contro ller c hip. 3.3V O

SWDO 3 Output data to switch controller chip. 3 .3V O

SWDO 2 Output data to switch controller chip. 3 .3V O

SWDO 1 Output data to switch controller chip. 3 .3V O

SWDO 0 Output data to switch controller chip. 3 .3V O

VDD 3.3V powe r supply. 3.3V -

GND Ground. -

S W CL K 50MHz ref er ence cl ock s i gnal fr om s wi tch contr ol ler chip. 3.3V I

SWPID0 Port ID indicat ion sig nal from switch controller chip. 3. 3V I

SWPID1 Port ID indicat ion sig nal from switch controller chip. 3. 3V I

SWPID2 Port ID indicat ion sig nal from switch controller chip. 3.3V I

SWPID3 Port ID indicat ion sig nal from switch controller chip. 3.3V I

SWPID4 Port ID indicat ion sig nal from switch controller chip. 3.3V I

SWSYNC Port 0 indication signal from switch controller chip. 3 .3V I

SWEO F End Of F rame ind icat ion signal from switch c ontroller chip. 3.3V I

VDD 3.3V pow er s upply. -

GND Ground. -

S W S T AT 0 Data S tatu s s i gnal f rom s wi tch control l er chip. 3.3V I

S W S T AT 1 Data S tatu s s i gnal f rom s wi tch control l er chip. 3.3V I

S W S T AT 2 Data S tatu s s i gnal f rom s wi tch control l er chip. 3.3V I

S W S T AT 3 Data S tatu s s i gnal f rom s wi tch control l er chip. 3.3V I

SWDIR0 Data direction in dication signal from switch controller chip. 3 .3V I

SWDIR1 Data direction in dication signal from switch controller chip. 3 .3V I

NC Not connected. -

nRE SET Hardware reset pin. 3.3 V I

WCHDOG Wat ch dog sig nal. 3 .3V O

GND Ground. -

VDD 3.3V pow er s upply. -

GND Ground. -

UART DI UART dat a input line. 3 .3V I

UARTDO UART da ta output line. 3. 3V O

VDD 3.3V pow er s upply. -

GND Ground. -

CPUIRQ Interrupt request. 3.3V O

CPUD0 CPU data b us. 3.3V I/O

CPUD1 CPU data b us. 3.3V I/O

CPUD2 CPU data b us. 3.3V I/O

CPUD3 CPU data b us. 3.3V I/O

CPUD4 CPU data b us. 3.3V I/O

CPUD5 CPU data b us. 3.3V I/O

CPUD6 CPU data b us. 3.3V I/O

CPUD7 CPU data b us. 3.3V I/O

VDD 3.3V pow er s upply. -

GND Ground. -

CPUA0 CPU address bus. 3. 3V I

CPUA1 CPU address bus. 3. 3V I

CPUA2 CPU address bus. 3. 3V I

CPUA3 CPU address bus. 3. 3V I

CPUA4 CPU address bus. 3. 3V I

nCP UOE Output E nable s i gnal from CPU. 3.3V I

nC PUWE Writ e Enable signal from CPU. 3.3V I

nC PUCS C hip Sele ct signal from CPU. 3.3V I

GND Ground. -

VDD 3.3V pow er s upply. -

Pin Name Descr iption I/O Pin Name Descr iption I/O

1GND Ground. - 65 2 SWD I 63 D ata from switch controller chip. 3 .3V I 6 6 3 SWD I 62 D ata from switch controller chip. 3 .3V I 67 4 SWD I 61 D ata from switch controller chip. 3 .3V I 68 5 SWD I 60 D ata from switch controller chip. 3 .3V I 69 6 SWD I 59 D ata from switch controller chip. 3 .3V I 70 7 SWD I 58 D ata from switch controller chip. 3 .3V I 71 8 SWD I 57 D ata from switch controller chip. 3 .3V I 72

9 SWD I 56 D ata from switch controller chip. 3 .3V I 73 1 0 SWD I 55 Data from switc h controller chip. 3.3V I 74 1 1 SWD I 54 Data from switc h controller chip. 3.3V I 75 1 2 SWD I 53 Data from switc h controller chip. 3.3V I 76 1 3 SWD I 52 Data from switc h controller chip. 3.3V I 77 1 4 SWD I 51 Data from switc h controller chip. 3.3V I 78 1 5 SWD I 50 Data from switc h controller chip. 3.3V I 79 1 6 SWD I 49 Data from switc h controller chip. 3.3V I 80 1 7 SWD I 48 Data from switc h controller chip. 3.3V I 81 18 VDD 3.3V power supply. - 82 19 GND Ground. - 83 2 0 SWD I 47 Data from switc h controller chip. 3.3V I 84 2 1 SWD I 46 Data from switc h controller chip. 3.3V I 85 2 2 SWD I 45 Data from switc h controller chip. 3.3V I 86 2 3 SWD I 44 Data from switc h controller chip. 3.3V I 87 2 4 SWD I 43 Data from switc h controller chip. 3.3V I 88 2 5 SWD I 42 Data from switc h controller chip. 3.3V I 89 2 6 SWD I 41 Data from switc h controller chip. 3.3V I 90 2 7 SWD I 40 Data from switc h controller chip. 3.3V I 91 2 8 SWD I 39 Data from switc h controller chip. 3.3V I 92 2 9 SWD I 38 Data from switc h controller chip. 3.3V I 93 3 0 SWD I 37 Data from switc h controller chip. 3.3V I 94 3 1 SWD I 36 Data from switc h controller chip. 3.3V I 95 3 2 SWD I 35 Data from switc h controller chip. 3.3V I 96 3 3 SWD I 34 Data from switc h controller chip. 3.3V I 97 3 4 SWD I 33 Data from switc h controller chip. 3.3V I 98 3 5 SWD I 32 Data from switc h controller chip. 3.3V I 99 3 6 SWD I 31 Data from switc h controller chip. 3.3V I 100 3 7 SWD I 30 Data from switc h controller chip. 3.3V I 101 38 VDD 3.3V power supply. - 102 39 GND Ground. - 103 4 0 SWD I 29 Data from switc h controller chip. 3.3V I 104 4 1 SWD I 28 Data from switc h controller chip. 3.3V I 105 4 2 SWD I 27 Data from switc h controller chip. 3.3V I 106 4 3 SWD I 26 Data from switc h controller chip. 3.3V I 107 4 4 SWD I 25 Data from switc h controller chip. 3.3V I 108 4 5 SWD I 24 Data from switc h controller chip. 3.3V I 109 4 6 SWD I 23 Data from switc h controller chip. 3.3V I 110 4 7 SWD I 22 Data from switc h controller chip. 3.3V I 111 4 8 SWD I 21 Data from switc h controller chip. 3.3V I 112 4 9 SWD I 20 Data from switc h controller chip. 3.3V I 113 5 0 SWD I 19 Data from switc h controller chip. 3.3V I 114 5 1 SWD I 18 Data from switc h controller chip. 3.3V I 115 5 2 SWD I 17 Data from switc h controller chip. 3.3V I 116 5 3 SWD I 16 Data from switc h controller chip. 3.3V I 117 5 4 SWD I 15 Data from switc h controller chip. 3.3V I 118 5 5 SWD I 14 Data from switc h controller chip. 3.3V I 119 5 6 SWD I 13 Data from switc h controller chip. 3.3V I 120 5 7 SWD I 12 Data from switc h controller chip. 3.3V I 121 5 8 SWD I 11 Data from switc h controller chip. 3.3V I 122 5 9 SWD I 10 Data from switc h controller chip. 3.3V I 123 6 0 SWD I 9 D at a from switch controller chip. 3 .3V I 124 6 1 SWD I 8 D at a from switch controller chip. 3 .3V I 125 6 2 SWD I 7 D at a from switch controller chip. 3 .3V I 126 6 3 SWD I 6 D at a from switch controller chip. 3 .3V I 127 64 VDD 3.3V power supply. - 128

Data Sheet: ACD80800

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 8

5. INTERFACE DESCRIPTION

Switch Interface Switch interface provides a communication channel

between ACD’s switch controller chip and ACD80800. As a frame is being received by ACD’s switch controller chip , the destination address and source address of the frame are snooped from the SWDIx lines of ACD80800, with respect to the SWCLK signal. ACD80800 carries a lookup process for each destination address, and a learning process for each source address. The result of the lookup is returned to the switch controller chip through the SWDOx lines.

T able 1

shows

the associated signals in the Switch Interface.

• 0000 - Third to Last word

• 0001 - First word

• 0010 - Second word

• 001 1 - Reserved

• 0100 - Reserved

• 0101 - Drop event

• 0110 - Jabber

• 0111 - False carrier

• 1000 - Alignment error

• 1001 - Flow control/collision

• 1010 - Short event/excessive collision

• 101 1 - Runt/Late collision

• 1100 - Symbol error

• 1101 - FCS error

• 1 1 10 - Long event

• 1111 - Reserved

Data Sheet: ACD80800

Table-1: Sw itch Interface

Name Type De scription

SWDI0 ~

SWDI63

SWSTAT0 ~

SWSTAT3

SWEOF I End of frame indication signal

SWDIR0 ~

SWDIR1

SWSYN C I Port synchronization signal

SWPID0 ~

SWPID4 SWCLK I Reference clock

SWDOV O Output data valid signal

SWDO0 ~

SWDO3

Input data, which can be 48-

I Input data state

I Port-ID indication signal

bit or 64-bit wide

Data direction indication

signal

Output data which can be 2-

bit or 4-bit wide

The SWDIx signal comes from the SRAM Data bus of ACD’s switch controller chip . Since all data of the received frames have to be written into the shared memory through the Data bus, the bus can be monitored for occurrence of DA and SA values, indicated by the associated state bits. The signals in SWDIx bus can be a 48-bit or 64-bit wide data bus. For a 48-bit wide bus, the first word will be the DA and the second word will be the SA. For a 64-bit wide bus, DA is the first 48-bit of first word, SA is the last 16-bit of first word plus first 32bit of second word.

SWDIR is a 2-bit signal to indicate the direction of the data displayed on the SWDI bus, 01 for receiving, 10 for transmitting, 00 or 11 for other states. ACD80800 only deals with the received data.

SWST AT bus is a 4-bit signal, used to indicate the meaning (status) of the data. The 4-bit status is defined as:

Note: error type depends on SWDIR is 01 or

10.

SWSYNC is used to indicate port 0 is driving the Data bus. It is used when the bus is evenly allocated in a time division multiplexing manner, such that a monitoring device can implement a counter to indicate the ID of the port which is driving the SWDI bus, and use SWSYNC signal to reset the counter. When SWSYNC is in use, SWPID is ignored.

SWPID is used to indicate the ID of the port which is driving the Data bus. When SWPID is in use, SWSYNC is ignored.

SWEOF is used to indicate the start and end of a frame. It is always asserted when the corresponding port is idling. The start of a frame is indicated by a high-to-low transition of SWEOF signal. The end of a frame is indicated by a low to high transition of SWEOF signal.

SWCLK is used to provide timing reference of input data snooping and output data latching. The signal is also used as the system clock of the chip.

SWDOV is used to indicate the start of a lookup result package.

SWDOx is used to return the result of lookup to ACD’s switch controller chip. Data is latched onto SWDOx bus with respect to the rising edge of SWCLK signal. Each result package is consisted by 5-bit source port ID, 2bit result, and 5-bit destination port ID. The 2-bit result field is defined as 01 for match, with the port ID shown by the 5-bit destination port ID field; 10 for no match; 11 for forced disregard (filtering).

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 9

CPU Interface The CPU interface provides a communication channel

between the CPU and the ACD80800. Basically, the CPU sends command to the ACD80800 by writing into associated registers, and retrieve result from ACD80800 by reading corresponding registers. The registers are described in the section of “Register Description.” The CPU interface signals are described by

table 2

Table-2: C PU Interface

Name I/O De scription

CPU A0 ~

CPU A4

CPU D 0 ~

CPU D7

nCPUOE I Read enable signal, low active.

nCPUWE I Write enable signal, low active.

nCPUCS I Chip Select signal, low active.

CPUIRQ O Interrupt request signal.

I/O 8 data lines.

5 address lines for register

selection.

UARTDI I UART i nput data line.

UARTDO O UART output data line.

CPUAx is the address bus used to select the registers of the ACD80800.

CPUDx is the data bus used to pass data between the CPU and the registers of the ACD80800.

nCPUOE is used to control the timing of the read operation.

where:

• Header is further defined as: ∗ b1:b0 - read or write, 01 for read,

11 for write

∗ b4:b2 - device number , 000 to 1 11

(0 to 7)

∗ b7:b5 - device type, 010 for ARL

• Address - 8-bit value used to select the reg-

ister to access

• Data - 32-bit value, only the LSB is used

for write operation, all 0 for read operation

• Checksum - 8-bit value of XOR of all bytes

UARTDO is used to return the result of command execution to the CPU. The format of the result packet is shown as follows:

Header Addres s Data Checksum

where:

• Header is further defined as: ∗ b1:b0 - read or write, 01 for read,

11 for write

∗ b4:b2 - device number , 000 to 1 11

(0 to 7)

∗ b7:b5 - device type, 010 for ARL

• Address - 8-bit value for address of the

selected register

• Data - 32-bit value, only the LSB is used

for read operation, all 0 for write operation

• Checksum - 8-bit value of XOR of all bytes

Data Sheet: ACD80800

nCPUWE is used to control the timing of the write operation.

nCPUCS is used to make the ACD80800 active to the nCPUOE or nCPUWE signals.

CPUIRQ is used to generate an interrupt request to the CPU. For each source of the interrupt, refer to the description of the interrupt source register.

UARTDI is used by the control CPU to send command into the ACD80800. The baud rate will be automatically detected by the ACD80800. The result will be returned through the UARTDO line with the detected baud rate. The format of the command packet is shown as follows:

Header Addres s Data Checksum

The ACD80800 will always check the CMD header to see if both the device type and the device number matches with its setting. If not, it ignores the command and will not generate any response to this command.

Other Interface

(table 3)

Table-3: O ther Int erface

Name I/O Description

WCHDOG O

nRESET I Hard wa re reset signal, low active.

VDD - 3.3V power supply.

Alive signal from ACD80800 to indicate

it is working properly.

GND - Ground.

WCHDOG signal is used to prevent the system from hitting dead-lock by any abnormal event. Under normal condition, the output signal from the WCHDOG pin will not stay at low for longer than 10ms. If the state of

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 10

WCHDOG remains at low state, the chip is not working properly and needs to be reset.

nRESET pin is used to do a hardware reset to the ACD80800. Please note that after a hardware reset, all learned address is cleared, and the address table has to be built again.

Configuration Interface The following table shows the Power-On-Strobed con-

figuration setting:

Power-On-Strobed Setting

Name Description

BI ST Enable IC Test Enable DIO Enable

Port ID Select

NO CPU

Bus Width Selection

UART ID

Note: High=1=Enable

Boot-Internal-Self-Test for optional internal RAM test IC Manufacturer test use only: always pull low

1 = Data I/O 76 0 = UART Mode 1 = for 82124 or 82012 75 0 = reserve d

11 = No CPU, 80800 will self initiate 00 = With CPU, 80800 will wait for CPU to initia te

00 = 32 bit ( reserved ) 110/109

01 = 48 bit ( 82124 or 82012) 10 = reserved 11 = 64 bit ( reserved ) 000 = ID for the only or the first 80800 on the system 001 = ID for the second 80800 on the system with two 80800s

Shared

Pin#

74/111

114/113/112

6. REGISTER DESCRIPTION

into the command register. When a new command is written into the command register, ACD80800 will change the status of the Result register to 0. The Result register will indicate the completion of the command at the end of the execution. Before the completion of the execution, any command written into the command register is ignored by ACD80800.

The registers accessible to the CPU are described by

table 4

Table-4: R egist er Description

Re g. Name De scription

0 DataReg0 Byte 0 of data 1 DataReg1 Byte 1 of data 2 DataReg2 Byte 2 of data 3 DataReg3 Byte 3 of data 4 DataReg4 Byte 4 of data 5 DataReg5 Byte 5 of data 6 DataReg6 Byte 6 of data 7 DataReg7 Byte 7 of data 8 AddrReg0 LSB of address value

9 AddrReg1 MSB of address value 10 CmdReg Command register 11 RsltReg Result register 12 CfgReg Configuration register 13 IntSrcReg Interrupt source register 14 IntMskReg Interrupt mask register

15 nLearnReg0

16 nLearnReg1

17 nLearnReg2 18 AgeTimeReg0 LSB of aging period register

AgeTimeReg

20 PosCfg0

21 PosCfg1

Address learning disable

MSB of aging period

Power On Strobe

configur ation register 0

Power On Strobe

configur ation register 1

Data Sheet: ACD80800

ACD80800 provides a bunch of registers for the CPU to access the address table inside it. Command is sent to ACD80800 by writing into the associated registers. Before the CPU can pass a command to ACD80800, it must check the result register

11)

to see if the command has been done. When the

(register

Result register indicates the command has been done, the CPU may need to retrieve the result of previous command first. After that, the CPU has to write the associated parameter of the command into the Data registers. Then, the CPU can write the command type

The

DataRegX

are registers used to pass the parameter of the command to the ACD80800, and the result of the command to the CPU.

The

AddrRegX

are registers used to specify the address associated with the command.

The

CmdReg

the ACD80800. The command types are listed in

. The details of each command is described in the

is used to pass the type of command to

table

chapter of “Command Description.”

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 11

Table-5: Co mmand List

Command Description

0x09 0x0A Set a lock for the specified MAC address 0x0B

0x0C

0x0D

0x10 Read the first entry of the address table 0x11 Read next entry of address book 0x20 Read first valid entry 0x21 Read next valid entry 0x30 Read first new page 0x31 Read next new page 0x40 Read first aged page 0x41 Read next aged page 0x50 Read first locked page 0x51 Read next locked page 0x60 Read first filtered page 0x61 Read next filtered page 0x80 Read first page with specified PID 0x81 Read next page with specified PID

Add the specified MAC address into the

address table

Set a filtering flag for the specified MAC

address

Delete the specified MAC address from

the address table

Assign a port I D to the specified M AC

address

0xFF System reset

• bit 0 - aged address exists

• bit 1 - new address exists

• bit 2 - reserved

• bit 3 - reserved

• bit 4 - bucket overflowed

• bit 5 - command is done

• bit 6 - system initialization is completed

• bit 7 - self test failure

The

IntMskReg

is used to enable an interrupt source to generate an interrupt request. The bit definition is the same as IntSrcReg. A 1 in a bit enables the corresponding interrupt source to generate an interrupt request once it is set.

The

nLearnReg[2:0]

are used to disable address learning activity from a particular port. If the bit corresponding to a port is set, ACD80800 will not try to learn new addresses from that port.

The

AgeTimeReg[1:0]

are used to specify the period of address aging control. The aging period can be from 0 to 65535 units, with each unit counted as 2.684 second.

The

PosCfgReg0

is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin. The bits of PosCfgReg0 is listed as follows:

Data Sheet: ACD80800

The

RstReg

is used to indicate the status of command

execution. The result code is listed as follows:

• 01 - command is being executed and is not done yet

• 10 - command is done with no error

• 1x - command is done, with error indi-

cated by x, where x is a 4-bit error code: 0001 for cannot find the entry as specified

The

CfgReg

is used to configure the way the ACD80800 works. The bit definition of CfgReg is described as:

• bit 0 - disable address aging

• bit 1 - disable address lookup

• bit 2 - disable DA cache

• bit 3 - disable SA cache

• bit 7:4 - hashing algorithm selection,

default is 0000

The

IntSrcReg

is used to indicate what can cause interrupt request to CPU. The source of interrupt is listed as:

• bit 0 - BISTEN, shared with ARLDO0, 0 for no self test, 1 for enable self test

• bit 1 - TESTEN, shared with ARLDO1, 0 for normal operation, 1 for production test.

• bit 2 - DIOEN, shared with ARLDO2, 0 for using UART, 1 for using DIO.

• bit 3 - SYNCEN, shared with ARLDO3, 0 for using SWPID, 1 for using SWSYNC.

• bit 4 - NOCPU*, 0 for have a control CPU, 1 for do not have a control CPU.

Note: When

NOCPU

is set as 0, ACD80800 will not start the initialization process until a System Start command is sent to the command register.

The

PosCfgReg1

is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin. The bits of PosCfgReg1 is listed as follows:

• bit 1:0 - BUSMODE, shared with CPUD1:CPUD0, bus width selection, 01 for 48-bit, 10 for 64 bit.

• bit 2 - CPUGO, shared with CPUD2, only effective when NOCPU bit of PosCfgReg0 is set to 1. Setting CPUGO to 0 means

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 12

wait for the CPU to send the System Start command before the initialization process can be started.

• bit 5:3 - UARTID, shared with CPUD5:CPUD3, 3-bit ID for UART communication.

Parameter:

DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB.

Result:

address table. The result is indicated by the Result register.

Command 0DH

Store the MAC address into DataReg5 -

the MAC address will be removed from the

Data Sheet: ACD80800

7. COMMAND DESCRIPTION

Command 09H

Description:

address table.

Parameter:

DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the associated port number into DataReg6.

Result:

address table if there is space available. The result is indicated by the Result register.

Command 0AH

Description:

address.

Parameter:

DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB.

Result:

matched MAC address, and set the Lock bit of the entry . The result is indicated by the Result register .

Add the specified MAC address into the

Store the MAC address into DataReg5 -

the MAC address will be stored into the

Set the Lock bit for the specified MAC

Store the MAC address into DataReg5 -

the state machine will seek for an entry with

Description:

specified MAC address.

Parameter:

DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the port number into DataReg6.

Result:

specified MAC address will be changed accordingly . The result is indicated by the Result register.

Command 10H

Description: Parameter: Result:

the command is completed with no error, the content of the first entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag* bits are stored in DataReg7.The Read Pointer will be set to point to second entry of the address book.

Assign the associated port number to the

Store the MAC address into DataReg5 -

the port ID field of the entry containing the

Read the first entry of the address table.

None

The result is indicated by the Result register. If

Command 0BH

Description:

address.

Parameter:

DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB.

Result:

matched MAC address, and set the Filter bit of the entry . The result is indicated by the Result register .

Command 0CH

Description:

the address table.

Set the Filter flag for the specified MAC

Store the MAC address into DataReg5 -

the state machine will seek for an entry with

Delete the specified MAC address from

Note - the Flag bits are defined as:

b7 b6 b5 b4 b3 b2 b1 b0

Rsv d R sv d Filter Lock New O ld Age Valid

where:

• Filter - 1 indicates the frame heading to this address should be dropped.

• Lock - 1 indicates the entry should never be changed or aged out.

• New - 1 indicates the entry is a newly learned address.

• Old - 1 indicates the address has been aged out.

• Age - 1 indicates the address has not

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.

Page 13

been visited for current age cycle.

• V alid - 1 indicates the entry is a valid one.

• Rsvd - Reserved bits.

Command 1 1H

Description: Parameter: Result:

the command is completed with no error, the content of the address book entry pointed by Read Pointer will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer will be increased by one.

Command 20H

Description: Parameter: Result:

the command is completed with no error, the content of first valid entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry .

Command 21H

Description: Parameter: Result:

the command is completed with no error, the content of next valid entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry .

Command 30H

Description:

Datasheet ACD80800 Datasheet (ACD)

Specifications and Main Features

Frequently Asked Questions

User Manual