Datasheet AB28F200BR-T80, AB28F200BR-B80 Datasheet (Intel Corporation)

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ADVANCE INFORMATION

April 1997 Order Number: 290542-003

Intel SmartVoltage Technology



5V or 12V Program/Erase



5V Read Operation

Very High Performance Read



80 ns Max. Access Time,



40 ns Max. Output Enable Time

Low Power Consumption



Maximum 65 mA Read Current at 5V

x8/x16-Selectable Input/Output Bus



High Performance 16- or 32-bit CPUs

Optimized Array Blocking Architecture



One 16-KB Protected Boot Block



Two 8-KB Parameter Blocks



One 96-KB Main Block



One 128-KB Main Block



Top or Bottom Boot Locations

Hardware-Protection for Boot Block

Software EEPROM Emulation with Parameter Blocks

Automotive Temperature Operation



-40°C to +125°C

Extended Cycling Capability



30,000 Block Erase Cycles for Parameter Blocks



1,000 Block Erase Cycles for Main Blocks

Automated Word/Byte Program and Block Erase



Industry-Standard Command User Interface



Status Registers



Erase Suspend Capability

SRAM-Compatible Write Interface

Automatic Power Savings Feature



1 mA Typical ICC Active Current in Static Operation

Reset/Deep Power-Down Input



0.2 µA ICCTypical



Provides Reset for Boot Operations

Hardware Data Protection Feature



Program/Erase Lockout during Power Transitions

Industry-Standard Surface Mount Packaging



44-Lead PSOP: JEDEC ROM Compatible

ETOX™ IV Flash Technology

A28F200BR-T/B

2-MBIT (128K X 16, 256K X 8)

SmartVoltage BOOT BLOCK

FLASH MEMORY FAMILY

Automotive

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provi ded in Intel ’s Terms and Condi tions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. The A28F200BR-T/B may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available upon request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s website at http:\\www.intel.com

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CONTENTS

PAGE PAGE

1.0 PRODUCT FAMILY OVERVIEW.....................5

1.1 New Features in the

SmartVoltage Products ...............................5

1.2 Main Features..............................................5

1.3 Applications..................................................6

1.4 Pinouts.........................................................6

1.5 Pin Descriptions...........................................8

2.0 PRODUCT DESCRIPTON...............................9

2.1 Memory Organization...................................9

2.1.1 Boot Block.............................................9

2.1.2 Parameter Blocks................................10

2.1.3 Main Blocks.........................................10

3.0 PRODUCT FAMILY PRINCIPLES OF

OPERATION ................................................10

3.1 Bus Operations ..........................................12

3.2 Read Operations........................................12

3.2.1 Read Array..........................................12

3.2.2 Intelligent Identifiers ............................12

3.3 Write Operations........................................12

3.3.1 Command User Interface.....................12

3.3.2 Status Register....................................15

3.3.3 Program Mode.....................................16

3.3.4 Erase Mode.........................................17

3.4 Boot Block Locking ....................................20

3.4.1 V

= VIL for Complete Protection .......20

3.4.2 WP# = V

for Boot Block Locking .......21

3.4.3 RP# = V

or WP# = VIH for

Boot Block Unlocking .........................21

3.5 Power Consumption...................................21

3.5.1 Active Power .......................................21

3.5.2 Automatic Power Savings....................21

3.5.3 Standby Power....................................21

3.5.4 Deep Power-Down Mode.....................21

3.6 Power-Up Operation...................................22

3.6.1 RP# Connected to System Reset ........22

3.7 Power Supply Decoupling ..........................22

3.7.1 V

Trace on Printed Circuit Boards....22

3.7.2 V

, VPP and RP# Transitions.............22

4.0 ABSOLUTE MAXIMUM RATINGS................23

5.0 OPERATING CONDITIONS ..........................24

5.1 V

Voltage................................................24

5.2 DC Characteristics .....................................25

5.3 AC Characteristics......................................29

APPENDIX A: Ordering Information .................36

APPENDIX B: Additional Information...............37

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REVISION HISTORY

Number Description

-001 Original Version

-002 Changed RP# AC Characteristics Changed V

LKO

to 3.5V

-003 Parameter Block Cycling Specification Increased to 30,000 I

CCD

Specification Increased to 105 µA

CCR

Specification Increased to 65 mA

WHAX

Specification changed from 10 ns to 0 ns

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1.0 PRODUCT FAMILY OVERVIEW

This datasheet contains the specifications for the automotive version of the 28F200BR family of boot block flash memory devices.

This device continues to offer the same functionality as earl ier “BX” devices but adds the

capability of performing program and erase operations with a 5V or 12V V

. The A28F200BR automatically senses which voltage is applied to the V

pin and adjusts its operation accordingly.

1.1 New Features in the

SmartVoltage Products

The new SmartVoltage boot block flash memory family offers identical operation as the current BX/BL 12V program products, except for the differences listed below. All other functions are equivalent to current products, including signatures, write commands, and pinouts.

• WP# pin has replaced a DU pin. See Table 1

for details.

• 5V program/erase operation has been added

that uses proven program and erase techniques with 5V ± 10% applied to V

If you are designing with exi st ing BX 12V VPP boot block products today, you should provide the capability in your board design to upgrade to these new SmartVoltage products.

Follow these guidelines to ensure compatibilty:

1. Connect WP# (DU on existing product s) to a

control signal, V

or GND.

2. If adding a switch on V

for write protection,

switch to GND for complete write protection.

3. Allow for connecting 5V t o V

instead of 12V,

if desired.

1.2 Main Features

Intel’s SmartVolt age technology prov ides the mos t flexible voltage solution in the industry. SmartVoltage provides t wo disc rete v olt age supply pins, V

for read operation, and VPP for program and erase operation. Discrete supply pins allow system designers to use the optimal volt age level s for their design. For program and erase

operations, 5V V

operation eliminates the need

for in system voltage converters, while 12V V

operation provides faster program and erase for situations where 12V is available, such as manufacturing or designs where 12V is already available.

The 28F200 boot block flash memory family is a very high-performance, 2-Mbit (2,097, 152 bit ) flas h memory family organized as either 256 Kwords (131,072 words) of 16 bits each or 512 Kbytes (262,144 bytes) of 8 bits each.

Separately erasable blocks, including a hardwarelockable boot block (16,384 by tes), two param eter blocks (8,192 Bytes each) and main blocks (one block of 98,304 bytes and one block of 131,072 bytes) define the boot block flash family architecture. See Figure 3 for memory maps. Eac h parameter block can be independently erased and programmed 10,000 times. Eac h main block can be erased 1,000 times.

The boot block is located at either the top (denoted by -T suffix) or the bottom (-B suf fix) of the address map in order to accommodate different microprocessor protocols for boot code location. The hardware-lockable boot block provides complete code security for the kernel code required for system initialization. Locking and unlocking of the boot block is controlled by WP# and/or RP# (see Section 3.4 for details).

The Command User Interface (CUI) s erves as the interface between the microprocessor or microcontroller and the internal operation of the boot block flash memory products. The internal Write State Machine (WSM) automatically executes the algorithms and ti mings necess ary f or program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller of these tasks. The Status Register (SR) indicates the status of the WSM and whether it successfully completed the desired program or erase operation.

Program and erase automation allows program and erase operations to be executed using an industry-standard two-write c ommand sequenc e to the CUI. Data writes are perf ormed in word or by te increments. Each byte or word in the flash memory can be programmed independently of other memory locations, unlike erases, which erase all locations within a block simultaneously.

The 4-Mbit SmartVoltage boot block f lash memory family is also designed with an A utomatic Power

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Savings (APS) feature which minimizes system battery current drain, allowing for v ery low power designs. To provide even greater power savings, the boot block family includes a deep power-down mode which minimizes power consumption by

turning most of the flash memory’s circuitry off. This mode is controlled by the RP# pin and its usage is discussed in Section 3.5, along with other power consumption issues.

Additionally, the RP# pin provides protection against unwanted command writes due to invalid system bus conditions that may occur during system reset and power-up/down sequences. Also, when the flash memory powers-up, it automatically default s to the read array mode, but during a warm system reset, where power continues uniterrupted to the system components, the flash memory could remain in a non-read mode, such as erase. Consequently, the system Reset pin should be tied to RP# to reset the memory to normal read mode upon activation of the Reset pin.

The byte-wide or word-wide input/output is controlled by the BYTE# pin. See Table 1 for a detailed description of BYTE# operations, especially the usage of the DQ

15/A-1

pin.

The 28F200 products are available in a ROM/EPROM-compatible pinout and housed in the 44-lead PSOP (Plastic Small Outline) package.

Refer to the DC Characteristics Table, Sect ion 5.2 for complete current and voltage specifications. Refer to the AC Characteristics Table, Section

5.3, for read, program and erase performance specifications.

1.3 Applications

The 2-Mbit boot block flash memory family combines high-density, low-power, highperformance, cost-effective flash memories with blocking and hardware protection capabilities. Their flexibility and versatility reduce costs throughout the product lif e cycle. Flash memory is ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component handling during the production phase.

When the product is in the end-user’s hands, and updates or feature enhancements become necessary or mandatory, f lash memory el iminates the need to replace an assembl y. The update can be performed as part of routine maintenance operation by relatively unsophisticated technicians.

The reliability of such a field upgrade is enhanced by a hardware-protected 16-Kbyte boot block. If the protection methods are implemented in the circuit design, the boot block will be unchangeable. Locating the boot-st rap code i n t his area assures a fail-safe rec overy from an update operation that failed to complete correctly.

The two 8-Kbyte parameter blocks allow modification of control algorithms to reflect changes in the process or device being c ontrolled. A variety of software algorithms allow these two blocks to behave like a standard EEPROM.

Intel’s boot block architecture provides a flexible voltage solution for the di fferent design needs of various applications. The asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. The boot block provides a s ecure boot PROM ; t he parameter blocks can emulate EEPROM functionality for parameter store with proper software techniques; and t he main blocks provide code and data storage with access times fast enough to execute code in plac e, decreas ing RAM requirements.

1.4 Pinouts

Intel’s SmartVoltage boot block architecture provides upgrade paths in every pac kage pinout to the 8-Mbit density. The 28F200 44-lead PSOP pinout follows the indust ry standard ROM/EPROM pinout as shown in Figure 2.

Pinouts for the corresponding 4-Mbit and 8-Mbit components are also provided for convenient reference. 2-Mbit pinouts are given on the chip illustration in the center, with 2-Mbit and 8-Mbit pinouts going outward from the center.

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A[1:17]

CS#

RD#

WR#

D[0:15]

A[0:16]

CE#

OE#

WE#

DQ[0:15]

Intel386™ EX

Microprocessor

GPIO

RESET#

PWRGOOD

PLD

Intel

28F200-T

RP#

GPIO

RESET#

WP#

BYTE#

PLD

Transceiver

0542-01

Figure 1. 28F200BX Interface to Intel386™ Microprocessor

AB28F200

44-Lead PSOP

0.525" x 1.110"

TOP VIEW

GND

WE#

RP#

BYTE#

32 31 30 29 28 27 26 25 24 23

CE#

WP#

GND

OE#

17 18

1 2 3 4 5 6 7 8 9

10 11

12 13 14

CE#

WP#

GND OE#

GND

WE#

RP#

BYTE#

28F400 28F400

15 -1

/A DQ

15 -1

CE#

GND

OE#

28F800

GND

WE#

RP#

BYTE#

28F800

15 -1

0542_02

NOTE:

Pin 2 is DU for BX 12V V

Versions.

Figure 2. 44-Lead PSOP Lead Configuration for x8/x16 28F200 Is Compatible with 4 and 8 Mbit.

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1.5 Pin Descriptions

Table 1. 28F200 Pin Descriptions

Symbol Type Name and Function

A0 - A

INPUT ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a write cycle.

INPUT ADDRESS INPUT: When A9 is at VHH the signature mode is accessed.

During this mode, A

decodes between the manufacturer and device IDs. When BYTE# is at a logic low, only the lower byte of the signatures are read. DQ

15/A-1

is a don’t care in the signature mode when BYTE# is low.

DQ0-DQ7INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and

WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched during the Write cycle. Outputs array, Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled.

DQ8-DQ15INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and

WE# cycle during a Program command. Data is internally latched during the Write cycle. Outputs array data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide mode DQ

15/A-1

becomes the lowest

order address for data output on DQ

-DQ7.

CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers,

decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP# input stages.

OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers

during a read cycle. OE# is active low.

WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array

blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse.

RP# INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and

) to control two different functions: reset/deep power-down mode and

boot block unlocking. It is backwards-compatible with the 28F200BX/BL.

When RP# is at logic low, the device is in reset/deep power-down mode, which puts the outputs at High-Z, resets the Write State Machine,

and draws minimum current. When RP# is at logic high, the device is in standard operation. When

RP# transitions from logic-low to logic-high, the device defaults to the read array mode.

When RP# is at V

, the boot block is unlocked and can be

programmed or erased. This overides any control from the WP# input.

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Table 1. 28F200 Pin Descriptions

(Continued)

Symbol Type Name and Function

WP# INPUT WRITE PROTECT: Provides a method for unlocking the boot block in a

system without a 12V supply. When WP# is at logic low, the boot block is locked, preventing

program and erase operations to the boot block. If a program or erase operation is attempted on the boot block when WP# is low, the corresponding status bit (bit 4 for program, bit 5 for erase) will be set in the Status Register to indicate the operation failed.

When WP# is at logic high, the boot block is unlocked and can be programmed or erased.

NOTE: This feature is overridden and the boot block unlocked when RP# is at V

. See Section 3.4 for details on write protection.

BYTE# INPUT BYTE# ENABLE: Controls whether the device operates in the byte-wide

(x8) mode or the word (x16) mode. The BYTE# input must be controlled at CMOS levels to meet the CMOS current specification in the standby mode.

When BYTE# is at logic low, the byte-wide mode is enabled. A 19-bit address is applied on A

-1

to A17, and 8 bits of data is read and written on

-DQ7.

When BYTE# is at logic high, the word-wide mode is enable. An 18-bit address is applied on A

to A17 and 16 bits of data is read and written on

- DQ15.

DEVICE POWER SUPPLY: 5.0V ± 10%

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must be applied to this pin. When V

< V

PPL

all blocks are locked

and protected against Program and Erase commands.

GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating.

2.0 PRODUCT DESCRIPTON

2.1 Memory Blocking Organization

This product family features an asymmetricallyblocked architecture enhancing system memory integration. Each block can be erased independently of the others up to 10, 000 t imes . The block sizes have been chosen to optimize their functionality for common appli cations of nonvolatile storage. For the address locations of the blocks, see the memory maps in Figure 3.

2.1.1 ONE 16-KB BOOT BLOCK

The boot block is intended to repl ace a dedicated boot PROM in a microprocess or or microcontrollerbased system. The 16-Kbyte (16,384 bytes) boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address m ap to accommodate different microproces sor protocols for boot code location. This boot block features hardware controllable write-protection to protec t the crucial microprocessor boot code from accidental erasure. The protection of the boot block is controlled using a combinati on of the V

, RP#, and

WP# pins, as is detailed in Table 8.

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2.1.2 TWO 8-KB PARAMETER BLOCKS

The boot block architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally require an EEPROM. By using software techniques, the by terewrite functionality of EEPROMs can be emulated.

These techniques are detailed in Intel’s AP-604, “Using Intel’s Boot B lock Flash Memory Parameter Blocks to Replace EEPROM.” Each boot block component contains two paramet er blocks of eight Kbytes (8,192 bytes) each. The parameter blocks are not write-protectable.

2.1.3 ONE 96-KB + THREE 128-KB MAIN BLOCKS

After the allocation of address space to the boot and parameter blocks, the remainder is divided into main blocks for data or code storage. Each 2-Mbit device contains one 96-Kbyte (98,304 byte) block and one 128-Kbyte (131,072 byte) block. See the memory maps for each device for more information.

3.0 PRODUCT FAMILY PRINCIPLES

OF OPERATION

Flash memory augments EPROM funct ionality with in-circuit electrical program and erase. The boot block flash family utilizes a Command User

Interface (CUI and automated algori thms to simpli fy program and erase operations. The CUI allows for 100% TTL-level control inputs, f ixed power s upplies during erasure and programming, and maximum EPROM compatibility.

When V

< V

PPLK

, the device will only successfully execute the following commands: Read Array, Read Status Register, Clear Status Register and intelligent identifier mode. The device provides standard EPROM read, standby and output disable operations. Manufacturer identification and device Identification data c an be accessed through the CUI or through the standard EPROM A

high voltage

access (V

) for PROM programming equipment.

The same EPROM read, standby and output disable functions are avai lable when 5V or 12V is applied to the V

pin. In addition, 5V or 12V on

allows program and erase of the device. All functions associ ated wit h alt ering mem ory c ontent s: Program and Erase, Intelligent Identifier Read, and Read Status are accessed via the CUI.

The purpose of the Write State Machine (WS M) is to completely automate the programming and erasure of the device. The WSM will begin operation upon receipt of a signal from the CUI and will report status back through a Status Register. The CUI will handle the WE# interface to the data and address latches, as well as system software requests for status while the WSM is in operation.

28F200-B

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

00000H

0FFFFH

10000H

1BFFFH

1C000H

1CFFFH

1D000H

1DFFFH

1E000H

1FFFFH

28F200-T

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

1FFFFH

10000H

0FFFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

0542-03

Figure 3. 28F200-T/B Memory Maps

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Table 2. Bus Operations for Word-Wide Mode (BYTE# = VIH)

Mode Notes RP# CE# OE# WE# A

A0V

0-15

Read 1,2,3 V

XXX D

OUT

Output Disable V

X X X High Z

Standby V

X X X X X High Z

Deep Power-Down 9 V

X X X X X X High Z

Intelligent Identifier (Mfr) 4 V

X 0089 H

Intelligent Identifier (Device)

4,5 V

X See Table 4

Write 6,7,8 V

XXX D

Table 3. Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE# OE# WE# A

A-1V

0-7

8-14

Read 1,2,3 V

XXXXD

OUT

High Z

Output Disable V

X X X X High Z High Z

Standby V

X X X X X X High Z High Z

Deep PowerDown

9VILX X X X X X X High Z High Z

Intelligent Identifier (Mfr)

4VIHV

X X 89H High Z

Intelligent Identifier (Device)

4,5 V

X X See

Table 4

High Z

Write 6,7,8 V

XXXXDINHigh Z

NOTES:

1. Refer to DC Characteristics.

2. X can be V

, VIH for control pins and addresses, V

PPLK

or V

PPH

for VPP.

3. See DC Characteristics for V

PPLK

, V

PPH

1, V

PPH

2, VHH, V

voltages.

4. Manufacturer and Device codes may also be accessed via a CUI write sequence, A

1-A17

= X, A1-A18 = X.

5. See Table 4 of Device IDs.

6. Refer to Table 5 for valid D

during a write operation.

7. Command writes for Block Erase or Word/ByteProgram are only executed when V

= V

PPH

1 or V

PPH

8. To program or erase the boot block, hold RP# at V

or WP# at VIH.

9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.

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3.1 Bus Operations

Flash memory reads, erases and programs insystem via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized in Tables 2 and 3.

3.2 Read Operations

The boot block flash device has three user read modes: array, intelligent identifier, and status register. Status register read mode will be discussed, in detail, in Section 3.3.2.

3.2.1 READ ARRAY

When RP# transitions from V

(reset) to VIH, the device will be in the read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any commands being written to the CUI.

When the device is in the read array mode, five control signals must be cont rolled to obtain data at the outputs.

• WE# must be logic high (V

)

• CE# must be logic low (V

)

• OE must be logic low (V

)

• RP# must be logic high (V

)

• BYTE# must be logic high or logic low. In addition, the address of the desired l ocat ion mus t

be applied to the address pins. Ref er to Figures 10 and 11 for the exact sequence and ti ming of these signals.

If the device is not i n read array mode, as would be the case after a program or erase operation, the Read Mode command (FFH) must be written to t he CUI before reads can take place.

3.2.1.1 Output Control

With OE# at logic-high level (V

), the output from the device is disabled and data Input/Output pins (DQ[0:15] or DQ[0:7]) are tri-stated.

3.2.1.2 Input Control

With WE# at logic-high level (V

), input to the

device is disabled.

3.2.2 INTELLIGENT IDENTIFIERS

The intelligent identifiers of the SmartVoltage boot block components are identical to the boot block products that operate only at 12V V

. The manufacturer and device codes are read via the CUI or by taking the A

pin to VID. Writing 90H to the CUI places the devic e into intelligent identifier read mode. In this mode, A

= 0 outputs the

manufacturer’s identification code and A

= 1 outputs the device code. When BYTE # is at a logic low, only the lower byte of the abov e signatures is read and DQ

15/A-1

is a “don’t care” during intelligent identifier mode. See the table below for product signatures. A Read Array c ommand m ust be writt en to the memory to return to the read array mode.

Table 4. Intelligent Identifier Table

Product Mfr. ID Device ID

-T

(Top Boot)-B(Bottom Boot)

28F200 0089 H 2274 H 2275 H

3.3 Write Operations

3.3.1 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) s erves as the interface between the microprocessor and the internal chip controller. Commands are written to the CUI using standard microprocessor write timings. The available c ommands are Read Array, Read Intelligent Identifier, Read Status Register, Clear Status Register, Program and Erase (summarized in Tables 5 and 6). For Read commands, the CUI points the read path at either the array, the intelligent identifier, or the Status Register depending on the command receiv ed. For Program or Erase commands, t he CUI informs the Write State Machine (WSM) that a program or erase has been requested. During the execution of a Program command, the WSM will control the programming sequences and the CUI will only respond to status reads. Duri ng an erase cycle, the

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CUI will respond to status reads and erase suspend. After the WSM has completed its task , it will set the WSM Status bit to a “1,” which will also

allow the CUI to respond to it s full command set. Note that after the WSM has returned control to the CUI, the CUI will stay in the current command stat e until it receives another command.

3.3.1.1 Command Function Description

Device operations are selected by writing specific commands into the CUI. Table 5 defines the available commands.

Table 5. Command Set Codes and

Corresponding Device Mode

Command Codes Device Mode

00 Invalid Reserved 10 Alternate Program Set-

Up 20 Erase Set-Up 40 Program Set-Up 50 Clear Status Register 70 Read Status Register 90 Intelligent Identifier B0 Erase Suspend

D0 Erase Resume/Erase

Confirm

FF Read Array

Invalid/Reserved

These are unassigned commands and should not be used. Intel reserves the right to redefi ne these codes for future functions.

Read Array (FFH)

This single write cycle command points the read path at the array. If the host CPU performs a CE#/OE#-controlled Read immediately following a two-write sequence that st arted the WSM, then the device will output Status Register contents. If the

Read Array command is given after the Erase Setup command, the device will res et to read the array. A two Read Array c ommand sequenc e (FFH) is required to reset to Read Array after t he Program Setup command.

Intelligent Identifier (90H)

After this command is exec uted, the CUI points the output path to the intelligent identifier circuits . Only intelligent identifier values at addresses 0 and 1 can be read (only address A

is used in this mode, all

other address inputs are ignored).

Read Status Register (70H)

This is one of the two comm ands that i s ex ecutable while the WSM is operating. After t his command is written, a read of the device will output the c ontents of the Status Register, regardless of the address presented to the device.

The device automatically enters this mode after program or erase has completed.

Clear Status Register (50H)

The WSM can only set the Program Status and Erase Status bits in the Status Register to “1,” it cannot clear them to “0.”

Two reasons exist for operating the Status Register in this fashion. The first is synchronization. Since the WSM does not know when the hos t CPU has read the Status Register, it would not k now when to clear the status bits. Secondly, if the CPU is programming a string of bytes, it may be more efficient to query the Status Register after programming the string. Thus, if any errors exist while programming the string, the Status Register will return the accumulated error status.

Program Setup (40H or 10H)

This command simply sets the CUI into a state such that the next write will load the Address and Data registers. After this c ommand is ex ecuted, the outputs default to the Status Register. A two Read Array command sequence (FFH) is required to reset to Read Array after the Program Setup command.

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Table 6. Command Bus Definitions

Notes First Bus Cycle Second Bus Cycle

Command 8 Oper Addr Data Oper Addr Data

Read Array 1 Write X FFH Intelligent Identifier 2,4 Write X 90H Read IA IID Read Status Register 3 Write X 70H Read X SRD Clear Status Register Write X 50H Word/Byte Program 6,7 Write PA 40H Write PA PD Alternate Word/Byte

Program

6,7 Write PA 10H Write PA PD

Block Erase/Confirm 5 Write BA 20H Write BA D0H Erase Suspend/Resume Write X B0H Write X D0H

ADDRESS DATA

BA= Block Address SRD= Status Register Data IA= Identifier Address IID= Identifier Data PA= Program Address PD= Program Data

X= Don’t Care

NOTES:

1. Bus operations are defined in Tables 2 and 3.

2. IA = Identifier Address: A

=0 for manufacturer code, A0=1 for device code.

3. SRD - Data read from Status Register.

4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two Read operations access manufacturer and device codes.

5. BA = Address within the block being erased.

6. PA = Address to be programmed. PD = Data to be programmed at location WD.

7. Either 40H or 10H commands is valid.

8. When writing commands to the device, the upper data bus [DQ

-DQ15] = X (28F200 only) which is either VCC or VSS, to

minimize current draw.

Program

The second write after the Program Setup command, will latch addresses and data. A lso, the CUI initiates the WSM to begin execution of the program algorithm. The device outputs Status Register data when OE# is enabled. A Read Array command is required after programming, to read array data.

Erase Setup (20H)

Prepares the CUI for the Eras e Confirm comm and. No other action is taken. I f t he next com mand is not an Erase Confirm command, then the CUI will set both the Program Status and Eras e Status bits of the Status Register t o a “1,” place the device into the Read Status Register s tate, and wait for another command.

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Erase Confirm (D0H)

If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at the same time closing the address and data latches, and respond only to t he Read Status Register and Erase Suspend commands . While the WSM is executing, the device will output Status Register data when OE# is toggled low. Status Register data can only be updated by toggling either OE# or CE# low.

Erase Suspend (B0H)

This command is only valid while the WSM is executing an erase operation, and therefore will only be responded to during an erase operation. After this command has been executed, the CUI will set an output that directs the WSM to suspend erase operations, and then respond only to Read Status Register or to the Erase Resume commands. Once the WSM has reached the Suspend state, it will set an output into the CUI which allows the CUI to respond to the Read Array, Read Status Register, and Erase Resume commands. In this mode, the CUI will not respond to any other commands. The WSM will als o set the WSM Status bit to a “1. ” The WSM will continue to

run, idling in the SUSPEND s tate, regardles s of the state of all input control pins except RP #, which will immediately shut down the WSM and the rem ainder of the chip, if it is made activ e. During a suspend operation, the data and address latc hes will remain closed, but the address pads are able to drive the address into the read path.

Erase Resume (D0H)

This command will cause the CUI to clear the Suspend state and clear the WSM Status Bi t to a “0,” but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect under any other conditions.

3.3.2 STATUS REGISTER

The device contains a Status Register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The Status Register may be read at any time by writing the Read Status

command to the CUI. Aft er writing this command, all subsequent read operations output data from t he Status Register until another command is written to the CUI. A Read Array command must be written t o the CUI to return to the read array mode.

The Status Register bits are output on DQ[0:7], whether the device is in the by te-wide (x8) or wordwide (x16) mode. In the word-wide mode t he upper byte, DQ[8:15], is set to 00H during a Read Stat us command. In the byte-wide mode, DQ[ 8:14] are tristated and DQ

15/A-1

retains the low order address

function.

Important: The contents of the Status Register are latched on the falling edge of OE# or CE#, whichever occurs last in the read cycle. This

prevents possible bus errors which might occur if the contents of the Status Register change while reading the Status Register. CE# or OE# must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident from the Status Register.

When the WSM is active, this regist er will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was suc cessful in performing the desired operation.

3.3.2.1 Clearing the Status Register

The WSM sets status bits “3” through “7” t o “1,” and clears bits “6” and “7” to “0,” but cannot clear status bits “3” through “5” to “0.” Bits 3 through 5 can only be cleared by the controlling CPU through the use of the Clear Status Regist er command. These bits can indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (s uch as cumulatively programmi ng several bytes or erasing multiple blocks in sequence). The Status Register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. To clear the Status Register, the Clear Status Register command is written to the CUI. Then, any other command may be issued to the CUI. Note, again, that before a read cycle can be initiated, a Read Array command must be written to the CUI to specif y whether the read data is to come from the M em ory Array, Status Register, or Intelligent Identifier.

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3.3.3 PROGRAM MODE

Programing is executed using a two-write sequence. The Program Setup command is writ ten to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to:

1. Program the desired bits of the addressed memory word or byte.

2. Verify that the desired bits are sufficiently programmed.

Programming of the memory resul ts in spec ific bits within a byte or word being changed to a “0.”

If the user attempts to program “1”s, there will be no change of the memory cell content and no error occurs.

Similar to erasure, the Status Register indicates whether programming is complete. While the program sequence is executing, bit 7 of the Stat us Register is a “0.” The Status Regis ter c an be polled by toggling either CE# or OE# to determine when the program sequence is complet e. Only the Read Status Register command is valid while programming is active.

Table 7. Status Register Bit Definition

WSMS ESS ES DWS VPPS R R R

76543210

NOTES:

SR.7 =WRITE STATE MACHINE STATUS (WSMS)

1 = Ready 0 = Busy

Write State Machine bit must first be checked to determine Byte/Word program or Block Erase completion, before the Program or Erase Status bits are checked for success.

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended 0 = Erase In Progress/Completed

When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an Erase Resume command is issued.

SR.5 = ERASE STATUS

1 = Error In Block Erasure 0 = Successful Block Erase

When this bit is set to “1,” WSM has applied the maximum number of erase pulses to the block and is still unable to successfully verify block erasure.

SR.4 = PROGRAM STATUS

1 = Error in Byte/Word Program 0 = Successful Byte/Word Program

When this bit is set to “1,” WSM has attempted but failed to program a byte or word.

SR.3 = VPP STATUS

1 = V

Low Detect, Operation Abort

0 = V

The V

Status bit, unlike an A/D converter, does

not provide continuous indication of V

level. The

WSM interrogates V

level only after the Byte Program or Erase command sequences have been entered, and informs the system if V

has not

been switched on. The V

Status bit is not guaranteed to report accurate feedback between V

PPLK

and V

PPH

SR.2–SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS

These bits are reserved for future use and should be masked out when polling the Status Register.

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When programming is complete, the status bits, which indicate whether the program operation was successful, s hould be checked. If bit 3 is set to a

“1,” then V

was not within accept able limits, and the WSM did not execute the programming sequence. If the program operation fails, Bit 4 of the Status Register will be set within 3.3 ms as determined by the timeout of the WSM.

The Status Register should be cleared before attempting the next operati on. Any CUI instruction can follow after programming is completed; however, reads from the Memory Array, Status Register, or Intelligent Identifier cannot be accomplished until the CUI is given t he Read Array command.

3.3.4 ERASE MODE

Erasure of a single block i s initiated by writi ng the Erase Setup and Erase Confirm c ommands to the CUI, along with the addresses identif ying the block to be erased. These addresses are latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.”

The WSM will execute a sequence of internally timed events to:

1. Program all bits within the block to “0.”

2. Verify that all bits within the block are

sufficiently programmed to “0.”

3. Erase all bits within the block.

4. Verify that all bits within the block are

sufficiently erased.

While the erase sequence is executing, bit 7 of the Status Register is a “0.”

When the Status Register indi cates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. If the erase operation was unsuccessful , bit 5 of the Status Register will be set to a “1,” indicating an Erase Failure. If V

was not within

acceptable limits af ter the E rase Confirm command is issued, the WSM will not execute an erase sequence; instead, bit 5 of the Status Register is set to a “1” to indicate an Eras e Failure, and bi t 3 is set to a “1” to identify that V

supply voltage was

not within acceptable limits. The Status Register should be cleared before

attempting the next operati on. Any CUI instruction can follow after erasure is completed; however, reads from the Memory Array, Status Register, or Intelligent Identifier cannot be accomplished until the CUI is given the Read Array command.

3.3.4.1 Suspending and Resuming Erase

Since an erase operation requires on the order of seconds to complete, an Erase Suspend c ommand is provided to allow erase-s equence interruption in order to read data from another block of the memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM paus e the erase sequence at a pre-determined point in the erase algorithm. The Status Register must then be read to determine if the erase operation has been suspended.

At this point, a Read Array com mand c an be writ ten to the CUI in order to read data from blocks other than that which is being suspended. The only other valid command at this time is the Erase Resume command or Read Status Register command.

During erase suspend mode, the chip c an go into a pseudo-standby mode by taki ng CE# to V

, which

reduces active current draw. To resume the erase operation, the chip must be

enabled by taking CE# to V

, then issuing the Erase Resume command. When the E rase Resume command is given, the WSM will continue with the erase sequence and complete erasing the block. As with the end of a standard erase operation, the Status Register must be read, c leared, and t he next instruction issued in order to continue.

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SR.7 = 1

YES

Start

Write 40H,

Word/Byte Address

Write Word/Byte

Data/Address

Full Status

Check if Desired

Word/Byte Program

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Read

Status Register

VPP Range Error

Bus

Operation

Standby

Check SR.3 1 = V

Low Detect

SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register command, in cases where multiple bytes are programmed before full status is checked.

If error is detected, clear the Status Register before attempt ing retry or other error recovery.

Bus

Operation

Command Comments

Write

Setup

Program

Data = Data to Program Addr = Location to Program

Read

Data = 40H Addr = Word/Byte to Program

Check SR.7 1 = WSM Ready 0 = WSM Busy

Repeat for subsequent word/byte program operations. SR Full Status Check can be done after each word/byte program, or after a sequence of word/byte programs. Write FFH after the last program operation to reset device to read array mode.

Standby

SR.3=

SR.4 =

Word/Byte Program

Error

Word/Byte Program

Successful

Check SR.4 1 = Word/Byte Program Error

Program

Status Register Data Toggle CE# or OE# to Update SRD.

Command Comments

0542_04

Figure 4. Automated Word/Byte Programming Flowchart

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SR.7 =

Start

Write 20H,

Block Address

Write D0H and

Block Address

Full Status

Check if Desired

Block Erase

Complete

FULL STATUS CHECK PR OCE DURE

Read Status Register

Data (See Above)

Read Status

VPP Range Error

Suspend

Erase

Suspend Erase

Loop

YES

Command Sequence

Error

SR.3 =

SR.5 =

SR.4,5 =

Block Erase

Error

Bus

Operation

Command Comments

Standby

Check SR.4,5 Both 1 = Command Sequence Error

Standby

Check SR.3 1 = V Low Detect

SR.3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machi ne.

SR.5 is only cleared by the Clear Stat us Regi ster Command, in cases where multiple blocks are erase before full status i s checked.

If error is detected, clear the S tat us R egister before attempting retry or other error recovery.

Check SR.5 1 = Block Erase Error

Standby

Bus

Operation

Command Comments

Write

Erase Setup

Read

Data = 20H Addr = Within Block to be Erased

Check SR.7 1 = WSM Ready 0 = WSM Busy

Repeat for subsequent block erasur es. Full Status Check can be done after each block erase, or after a sequence of block erasures. Write FFH after the last operation to reset device to read array mode.

Status Register Data Toggle CE# or OE# to Update Status Register

Standby

Erase

Confirm

Data = D0H Addr = Within Block to be Erased

Block Erase

Successful

0542_05

Figure 5. Automated Block Erase Flowchart

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SR.7 =

Start

Write B0H

Read

Status Register

Write D0H

Erase Resumed

Bus

Operation

Command Comments

Write

Erase

Suspend

Read

Data = B0H Addr = X

Check SR.7 1 = WSM Ready 0 = WSM Busy

Status Register Data Toggle CE# or OE# to update SRD. Addr = X

Standby

CSR.6 =

Write FFH

Read Array Data

Done

Reading

Erase Completed

Write FFH

Read Array Data

YES

Check SR.6 1 = Erase Suspended 0 = Erase Completed

Standby

Data = FFH Addr = X

Write

Read array data from block other than the one being erased.

Read

Data = D0H Addr = X

Write

Read Array

Erase Resume

0542_06

Figure 6. Erase Suspend/Resume Flowchart

3.4 Boot Block Locking

The boot block family architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blocks are programmed and erased independently as necessary. Only the boot block can be locked independently from the other blocks.

3.4.1 V

= VIL FOR COMPLETE

PROTECTION

For complete write protection of all blocks in the flash device, the V

programming voltage can be

held low. When V

is below V

PPLK

, any program or erase operation will result in a error in the Status Register.

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3.4.2 WP# = VIL FOR BOOT BLOCK LOCKING

When WP# = V

, the boot block is loc ked and any program or erase operation will result in an error in the Status Register. All other blocks remain unlocked in this condition and can be programmed or erased normally. Note that this feature is overridden and the boot block unlocked when RP# = V

3.4.3 RP# = V

OR WP# = VIH FOR BOOT

BLOCK UNLOCKING

Two methods can be used to unlock the boot block:

1. WP# = V

2. RP# = V

If both or either of these t wo condit ions are met , the boot block will be unlocked and can be programmed or erased. The Truth Table, Table 8, clearly defines the write protection methods.

Table 8. Write Protection Truth Table for

SmartVoltage Boot Block Family

RP# WP# Write Protection

Provided

X X All Blocks Locked

≥ V

PPLKVIL

X All Blocks Locked

(Reset)

≥ V

PPLKVHH

X All Blocks Unlocked

≥ V

PPLKVIH

VILBoot Block Locked

≥ V

PPLKVIH

VIHAll Blocks Unlocked

3.5 Power Consumption

3.5.1 ACTIVE POWER

With CE# at a logic-low level and RP# at a logichigh level, the device is placed in the active mode. Refer to the DC Characterist ics t able for I

current

values.

3.5.2 AUTOMATIC POWER SAVINGS (APS)

Automatic Power Savings (APS) is a low-power feature during active mode of operation. The boot block flash memory family incorporates Power

Reduction Control (PRC) circuitry which allows the device to put itself int o a low current st ate when i t is not being accessed. After data is read from the

memory array, PRC logic controls the device’s power consumption by entering the APS mode where typical I

current is less than 1 mA. The device stays in this static state with outputs valid until a new location is read.

3.5.3 STANDBY POWER

With CE# at logic-high level (V

), and the CUI in read mode, the memory is plac ed in st andby m ode. The standby operation disables much of the device’s circuitry and substantially reduces device power consumption. The outputs (DQ[0:15] or DQ[0:7]) are placed in a high-impedance state independent of the status of the OE# si gnal. When CE# is at logic-high level during erase or program functions, the devices will c ontinue to perform the erase or program function and consume erase or program active power until erase or program is completed.

3.5.4 DEEP POWER-DOWN MODE

The SmartVoltage boot block family s upports a low typical I

in deep power-down mode. The device has a RP# pin which places the device in the deep power-down mode. When RP# is at a logic-low (GND ± 0.2V), all circuits are turned off in order t o save power. (Note: BYTE# pi n must be at CMOS levels to achieve the most deep power-down current savings.)

During read modes, the RP# pin going low deselects the memory and pl aces the out put driv ers in a high impedance state. Recovery from the deep power-down state, requires a mi nimum access ti me of t

PHQV

. (See the AC Characteristics table for

specification numbers.) During erase or program modes, RP# low will abort

either erase or program operation. The contents of the memory are no longer valid as the data has been corrupted by the RP# functi on. As in the read mode above, all internal circuitry is turned off to achieve the power savings.

RP# transitions to V

, or turning power off to the

device will clear the Status Register.

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3.6 Power-Up Operation

The device is designed to offer protection against accidental block erasure or programming during power transitions. Upon power-up, the device is indifferent as to which power supply, V

or VCC, powers-up first. Power supply sequencing is not required.

A system designer must guard against spurious programming for V

voltages above V

LKO

when

is active. Since both WE# and CE# must be

low for a command write, drivi ng ei ther si gnal to V

will inhibit writes to the device. The CUI arc hitec ture provides an added level of protection since alteration of memory contents c an only occur after successful completion of the two-step command sequences. Finally the dev ice is disabled unti l RP# is brought to V

, regardless of the state of its control inputs. By hol ding the device in reset (RP # connected to system PowerGood) during power up/down, invalid bus condit ions that may oc cur can be masked. This feature provides yet another level of memory protection.

3.6.1 RP# CONNECTED TO SYSTEM

RESET

The use of RP# during system reset is important with automated program/erase devices. When the system comes out of reset it expects to read from the flash memory. Automated flash memories provide status information when accessed during program/erase modes. If a CPU reset oc curs with no flash memory reset, proper CPU initialization would not occur because the flash memory would be providing the status inf ormation instead of array

data. Intel’s Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application RP# is controlled by the same RESET# signal that resets the system CPU.

3.7 Power Supply Decoupling

Flash memory’s power switching characteristics require careful device decoupling methods. System designers should consider three supply current issues:

1. Standby current levels (I

CCS

)

2. Active current levels (I

CCR

)

3. Transient peaks produced by falling and rising edges of CE#.

Transient current magnitudes depend on t he devi ce outputs’ capacitiv e and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between eac h V

and GND,

and between its V

and GND. These high frequency, inherently low inductance capacitors should be placed as close as possible to the package leads.

3.7.1 V

TRACE ON PRINTED CIRCUIT

BOARDS

Writing to flash memories while they res ide in the target system, requires special consideration of the V

power supply trace by the printed c ircuit board

designer. The V

pin supplies the flash memory cells current for programming and erasing. One should use similar trace widths and layout considerations given to t he V

power supply trace.

Adequate V

supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.

3.7.2 V

, VPP AND RP# TRANSITIONS

The CUI latches commands as issued by system software and is not altered by V

or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode, or after V

transitions above V

LKO

(Lockout

voltage), is read array mode. After any word/byte program or block erase

operation is complete and even after V

transitions

down to V

PPLK

, the CUI must be reset to read array mode via the Read Array command when accesses to the flash memory are desired.

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4.0 ABSOLUTE MAXIMUM RATINGS*

Operating Temperature

During Read........................... -40°C to +125°C

During Block Erase

and Word/Byte Program......... -40°C to +125°C

Temperature Under Bias ........ -40°C to +125°C

Storage Temperature.................... -65°C to +125°C

Voltage on Any Pin

(except V

, VPP, A9 and RP#)

with Respect to GND..............-2.0V to +7.0V

(1)

Voltage on Pin RP# or Pin A

with Respect to GND..........-2.0V to +13.5V

(1,2)

VPP Program Voltage with Respect

to GND during Block Erase and

Word/Byte Program...........-2.0V to +14.0V

(1,2)

VCC Supply Voltage

with Respect to GND..............-2.0V to +7.0V

(1)

Output Short Circuit Current....................100 mA

(3)

NOTICE: This datasheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design

* WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability.

NOTES:

1. Minimum DC voltage is -0.5V on input/output pins.

During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum DC voltage on input/output pins is V

+ 0.5V which, during transitions, may overshoot to

+ 2.0V for periods <20 ns.

2. Maximum DC voltage on V

may overshoot to +14.0V

for periods <20ns. Maximum DC voltage on RP# or A

may overshoot to 13.5V for periods <20 ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

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5.0 OPERATING CONDITIONS

Table 9. Temperature and VCC Operating Conditions

Symbol Parameter Notes Min Max Units

Operating Temperature -40 +125 °C

VCC Supply Voltage (10%) 4.50 5.50 Volts

5.1 Applying VCC Voltages

If the VCC ramp rate is greater than 0.01 V/µs, a delay of 2 µs is required before any device operation can be initiated. This includes array or status read, command writ es and program or erase operations. The 2 µs are measure beginning f rom the time V

reaches V

CCMIN

(4.5V). This delay is

not tied to the operation of the reset input. It is recommended that the device be held in reset (RP# = GND) while V

is less than V

CCMIN

If the V

ramp rate is less than 0.01 V /µs, no delay

is required once V

has reached V

CCMIN

VCC Ramp Rate Required Timing

≤ 1V/100 µs No delay required. > 1V/100 µs A delay time of 2 µs is required before any device operation is initiated, including read

operations, command writes, program operations, and erase operations. This delay

measured beginning from the time V

reaches V

CCMIN

(4.5V for 5V operation).

NOTES:

1. These requirements must be strictly followed to guarantee all other read and write specifications.

2. Any time the V

supply drops below V

CCMIN

, the chip may be reset, aborting any operations pending or in progress.

3. These guidelines must be followed for any V

transition from GND.

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5.2 DC Characteristics

Table 10. DC Characteristics: Automotive Temperature Operation

Symbol Parameter Notes Min Typ Max Unit Test Conditions

Input Load Current 1 ± 5.0 µA

= VCCMax

= VCC or GND

Output Leakage Current 1 ± 10 µA

= V

Max

= VCC or GND

CCS

VCC Standby Current 1,3 0.8 2.5 mA

= V

Max CE# = RP# = BYTE# = V

70 250 µA

= V

Max CE# = RP# = WP# = V

± 0.2V

CCD

VCC Deep Power-Down Current 1 0.2 105 µA

= V

Max V

= VCC or GND

RP# = GND ± 0.2V

CCR

VCC Read Current for Word or Byte

1,5,6 50 65 mA

CMOS

= V

Max CE = V

f = 10 MHz (5V) 5 MHz (3.3V) I

OUT

= 0 mA Inputs = GND ± 0.2V or V

± 0.2V

55 70 mA

TTL

= V

Max

CE# = V

f = 10 MHz I

OUT

= 0 mA Inputs = V

or V

CCW

VCC Program Current for Word or Byte

1,4 25 50 mA Program in Progress

= V

PPH

1 (at 5V)

20 45 mA Program in Progress

= V

PPH

2 (at 12V)

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Table 10. DC Characteristics: Automotive Temperature Operation (Continued)

Symbol Parameter Notes Min Typ Max Unit Test Conditions

CCE

VCC Erase Current 1,4 22 45 mA

Block Erase in Progress V

= V

PPH

1 (at 5V)

18 40 mA

Block Erase in Progress V

= V

PPH

2 (at 12V)

CCES

VCC Erase Suspend Current 1,2 5 12.0 mA

CE# = V

Block Erase Suspend V

= V

PPH

1 (at 5V)

PPS

VPP Standby Current 1 ± 5 ± 15 µA V

≤ V

PPD

VPP Deep Power-Down Current 1 0.2 10 µA RP# = GND ± 0.2V

PPR

VPP Read Current 1 50 200 µA VPP >V

PPW

VPP Program Current for Word or Byte

11330mA

= V

PPH

Program in Progress V

= V

PPH

1 (at 5V)

825mA

= V

PPH

Program in Progress V

= V

PPH

2 (at 12V)

PPE

VPP Erase Current 1 15 25 mA

= V

PPH

Block Erase in Progress V

= V

PPH

1 (at 5V)

10 20 mA

= V

PPH

Block Erase in Progress V

PP=VPPH

2 (at 12V)

PPES

VPP Erase Suspend Current 1 50 200 µA

= V

PPH

Block Erase Suspend in Progress

RP#

RP# Boot Block Unlock Current 1,4 500 µA

RP# = V

= 12V

A9 Intelligent Identifier Current 1,4 500 µA A9 = V

A9 Intelligent Identifier Voltage 11.4 12.6 V

Input Low Voltage -0.5 0.8 V

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Table 10. DC Characteristics: Automotive Temperature Operation (Continued)

Symbol Parameter Notes Min Typ Max Unit Test Conditions

Input High Voltage 2.0

0.5V

Output Low Voltage (TTL) 0.45 V

= V

Min

= 5.8 mA

=12V

VOH1 Output High Voltage (TTL) 2.4 V

= V

Min

= -1.5 mA

VOH2 Output High Voltage (CMOS)

.4V

VCC = V

Min

= -100 µA

PPLK

VPP Lock-Out Voltage 3 0.0 1.5 V Complete Write

Protection

PPH

(Program/ Erase

Operations)

4.5 5.5 V V

at 5V

PPH

(Program/ Erase

Operations)

11.4 12.6 V V

at 12V

LKO

VCC Program/Erase Lock Voltage

2.0 V V

= 12V

RP# Unlock Voltage 11.4 12.6 V

Boot Block Program/Erase V

= 12V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

= 5.0V, T = 25°C. These currents are valid for all

product versions (packages and speeds).

2. I

CCES

is specified with the device de-selected. If the devices is read while in erase suspend mode, current draw is the sum

of I

CCES

and I

CCR

3. Block erases and word/byte program operations are inhibited when V

= V

PPLK

, and not guaranteed in the range between

PPH

1 and V

PPLK

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I

CCR

to less than 1 mA typical, in static operation.

6. CMOS Inputs are either V

± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

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Table 11. Capacitance (TA -25°C, f = 1 MHz)

Symbol Parameter Note Typ Max Unit Conditions

Input Capacitance 4 6 8 pF VIN = 0V

OUT

Output Capacitance 4 10 12 pF V

OUT

= 0V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

= 5.0V, T = +25°C. These currents are valid for all

product versions (packages and speeds).

2. I

CCES

is specified with the device de-selected. If the devices is read while in erase suspend mode, current draw is the sum

of I

CCES

and I

CCR

3. Block erases and word/byte program operations are inhibited when V

= V

PPLK

, and not guaranteed in the range between

PPH

1 and V

PPLK

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I

CCR

to less than 1 mA typical, in static operation.

6. CMOS Inputs are either V

± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

TEST POINTS

INPUT OUTPUT

2.0

0.8 0.8

2.0

2.4

0.45

0542-08

Figure 7. 5V Inputs and Measurement Points

585

Ω

394

Ω

DEVICE UNDER

TEST

0538-09

NOTE:

CL = 100 pF, includes Jig Capacitance

Figure 8. 5V Standard Test Configuration

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5.3 AC Characteristics

Table 12. AC Characteristics: Read Only Operations

(1)

(Automotive Temperature)

Symbol Parameter Note Min Max Unit

AVAV

Read Cycle Time 80 ns

AVQV

Address to Output Delay 80 ns

ELQV

CE# to Output Delay 2 80 ns

PHQV

RP# to Output Delay 550 ns

GLQV

OE# to Output Delay 2 40 ns

ELQX

CE# to Output in Low Z 3 0 ns

EHQZ

CE# to Output in High Z 3 20 ns

GLQX

OE# to Output in Low Z 3 0 ns

GHQZ

OE# to Output in High Z 3 20 ns

Output Hold from Address CE#, or OE# Change Whichever Occurs First

300ns

t t

ELFH

CE# Low to BYTE High or Low 3 5 ns

AVFL

Address to BYTE# High or Low 3 5 ns

t t

FHQV

BYTE# to Output Delay 3,4 80 ns

FLQZ

BYTE# Low to Output in High Z

330ns

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t

- tOE after the falling edge of CE# without impact on tCE.

3. Sampled, but not 100% tested.

4. t

FLQV

, BYTE# switching low to valid output delay will be equal to t

AVQV

, measured from the time DQ15/A-1 becomes valid.

5. See 5V Standard Test Configuration. (Figure 9)

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Address Stable

Device and

Address Sel e ction

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP#(P)

PHQV

High Z

Valid Output

Data

Valid Standby

AVAV

EHQZ

GHQZ

GLQV

GLQX

ELQV

ELQX

AVQV

High Z

0542_10

Figure 9. AC Waveforms for Read Operations

Address Stable

Device

Address Selection

ADDRESSES (A)

CE#

OE#

BYTE#

DATA (D/Q)

(DQ0-DQ7)

High Z

Data Output

on DQ0-DQ7

Data

Valid

Standby

AVAV

EHQZ

GHQZ

AVQV

High Z

GLQV

ELQV

AVQV

Data Output

on DQ0-DQ7

DATA (D/Q)

(DQ8-DQ14)

High Z

Data Output

on DQ8-DQ14

High Z

(DQ15-A1)

High Z

Data Output

on DQ15

Address Input

FLQZ

ELQX

ELFL

AVFL

GLQX

0542_11

Figure 10. BYTE# Timing Diagram for Both Read and Write Operations with VCC at 5V

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Table 13. AC Characteristics: WE#–Controlled Write Operations

(1)

(AutomotiveTemperature)

Symbol Parameter Notes Min Max Unit

AVAV

Write Cycle Time 80 ns

PHWL

RP# High Recovery to WE# Going Low 450 ns

ELWL

CE# Setup to WE# Going Low 0 ns

PHHWH

Boot Block Lock Setup to WE# Going High 6,8 100 ns

VPWH

VPP Setup to WE# Going High 5,8 100 ns

AVWH

Address Setup to WE# Going High 3 60 ns

DVWH

Data Setup to WE# Going High 4 60 ns

WLWH

WE# Pulse Width 60 ns

WHDX

Data Hold Time from WE# High 4 0 ns

WHAX

Address Hold Time from WE# High 3 0 ns

WHEH

CE# Hold Time from WE# High 10 ns

WHWL

WE# Pulse Width High 20 ns

WHQV1

Duration of Word/Byte Program Operation 2,5 7 µs

WHQV2

Duration of Erase Operation (Boot) 2,5,6 0.4 s

WHQV3

Duration of Erase Operation (Parameter) 2,5 0.4 s

WHQV4

Duration of Erase Operation (Main) 2,5 0.7 s

QWL

Hold from Valid SRD 5,8 0 ns

QVPH

RP# VHH Hold from Valid SRD 6,8 0 ns

PHBR

Boot-Block Relock Delay 7,8 100 ns

NOTES:

1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC Characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; Program/Erase algorithms are now controlled internally which includes verify and margining operations.

3. Refer to command definition table for valid A

4. Refer to command definition table for valid D

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)

6. For boot block program/erase, RP# should be held at V

or WP# should be held at V

until operation completes

successfully.

7. Time t

PHBR

is required for successful relocking of the boot block.

8. Sampled, but not 100% tested.

9. V

at 5V.

10. V

at 12V.

11. See 5V Standard Test Configuration.

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ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

6.5V

WHEH

WHWL

Valid SRD

WHQV1,2,3,4

PHHWH

PHWL

High Z

WHDX

V (V)

12 3 4 65

PPH

PPLK

PPH

WP#

AVAV

AVWH

WHAX

DVWH

WLWH

QVPH

QVVL

VPWH

ELWL

0542_12

Figure 11. AC Waveforms for Write Operations (WE#-Controlled Writes)

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Table 14. AC Characteristics: CE#–Controlled Write Operations

(1,12)

Symbol Parameter Notes Min Max Unit

AVAV

Write Cycle Time 80 ns

PHEL

RP# High Recovery to CE# Going Low 450 ns

WLEL

WE# Setup to CE# Going Low 0 ns

PHHEH

Boot Block Lock Setup to CE# Going High 6,8 100 ns

VPEH

VPP Setup to CE# Going High 5,8 100 ns

AVEH

Address Setup to CE# Going High 60 ns

DVEH

Data Setup to CE# Going High 3 60 ns

ELEH

CE# Pulse Width 4 60 ns

EHDX

Data Hold Time from CE# High 0 ns

EHAX

Address Hold Time from CE# High 4 10 ns

EHWH

WE# Hold Time from CE# High 3 10 ns

EHEL

CE# Pulse Width High 20 ns

EHQV1

Duration of Word/Byte Program Operation 2,5 7 µs

EHQV2

Duration of Erase Operation (Boot) 2,5,6 0.4 s

EHQV3

Duration of Erase Operation (Parameter) 2,5 0.4 s

EHQV4

Duration of Erase Operation (Main) 2,5 0.7 s

QWL

VPP Hold from Valid SRD 5,8 0 ns

QVPH

RP# V

Hold from Valid SRD 6,8 0 ns

PHBR

Boot-Block Relock Delay 7,8, 100 ns

NOTES:

See WE# Controlled Write Operations for notes 1 through 11.

12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE#

defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative to the CE# waveform.

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ADDRESSES (A)

WE# (E)

OE# (G)

CE# (W)

DATA (D/Q)

RP# (P)

6.5V

AVAV

Valid SRD

QVPH

PHHEH

High Z

EHDX

V (V)

12 3 4 65

EHAX

EHQV1,2,3,4

EHEL

EHWH

ELEH

DVEH

VPEH

QVVL

PHWL

WLEL

AVEH

PPLK

PPH

WP#

0542_13

Figure 12. Alternate AC Waveforms for Program and Erase Operations (CE#-Controlled Writes)

Table 15. Extended Temperature Operations - Erase and Program Timings

Parameter V

= 5V ±10% V

= 12V ±5% Unit

Typ Max Typ Max

Boot/Parameter Block Erase Time 0.8 7.8 0.34 4.0 s Main Block Erase Time 1.9 15.4 1.1 7.1 s Main Block Write Time (Byte Mode) 1.4 16.8 1.2 6.8 s Main Block Write Time (Word Mode) 0.9 8.4 0.6 3.4 s

All numbers are sampled, not 100% tested.

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APPENDIX A

ORDERING INFORMATION

= Bottom Boot

= Top Boot

Product line designator

for all Intel Flash products

Density / Organization

X00 = x8/x16 Selectable(X = 2, 4, 8)

Access Speed

(ns)

Architecture B

= Boot Block

Operating Temperature

A = Automotive Temp

Package

B = PSOP

Voltage Options

)

R = (5 or 12)

AB 28F2

BR-T

0542_14

VALID COMBINATIONS: AB28F200BR-T80 AB28F200BR-B80

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APPENDIX B

ADDITIONAL INFORMATION

(1,2)

Order

Number

Document

292130

AB-57 Boot Block Architecture for Safe Firmware Updates

292098

AP-363 Extended Flash BIOS Concepts for Portable Computers

290448

28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet

290449

28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet

290450

28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet

290451

28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet

290531

2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

NOTE:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.