The AAT3532 PowerManager™ product is a member of AATI’s Total Power Management ICs™
(TPMIC™) product family. It is a fully integrated
device for monitoring microprocessor activity,
external reset, and power supply conditions. The
device holds the microprocessor in a reset condition for a minimum of 250ms while VCCis established to ensure correct system start-up. A manual
reset can be initiated via a de-bounced input pin.
As an additional level of protection, the AAT3532
includes a watchdog timer which requires a periodic strobe input from the microprocessor to ensure
correct operation. The AAT3532 has a programmable watchdog timer and voltage tolerance level.
The quiescent supply current is extremely low, typically 23µA.
The AAT3532 is available in an 8-pin SOP package
specified over -40° to 85°C temperature range.
PowerManager
Features
•Adjustable 4.5V or 4.75V Voltage Monitor
•250ms (min) Reset Pulse Width
•Low quiescent current: typically 23µA
•Adjustable Watchdog Timer (150ms, 600ms,
or 1200ms)
•De-bounced Manual Reset Input
•Operates down to 20ns strobe input pulse
width
•No external components
•Temp range -40° to 85°C
•Standard 8 pin SOP package
•Pin compatible with MAX1232
Applications
•Computers
•Controllers
•Telecom Equipment
•Embedded Systems
•Intelligent Instrumentation
•Automotive
™
Preliminary Information
Typical Application
PBRST
TD
TOL
DD
V
CC
AAT3532
GND
RST
RST
RESET
INPUT
I/OST
V
DD
µ
P
3532.2001.11.0.91
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AAT3532
MicroPower™ Microprocessor Reset Circuit
Pin Descriptions
Pin #SymbolFunction
1PBRSTPushbutton reset input. A de-bounced active low input for manual reset. Guaranteed
to recognize inputs 20ms or greater.
2TDWatchdog time delay set input. See Table 1 for watchdog timeout selections.
3TOLTolerance set. Input selects 5% or 10% threshold detection
4GNDIC ground connection
5RSTReset Output (active high). Activated when either:
V
falls below the reset voltage threshold, or PBRST is forced low, or ST not strobed
CC
within the minimum timeout period, or during power-up.
6RSTReset Output (active low, open drain). Inverse of RST.
7STStrobe input to watchdog timer. A pulse is required within watchdog timeout period to
prevent RST and RST entering active state
8Vcc5V Supply
Pin Programming Selections
TD Pin
MinTypMax
GND62.5ms150ms250ms
Float250ms600ms1000ms
V
CC
500ms1200ms2000ms
Table 1: TD Pin Programming for Watchdog Timeout Selections
TOL PinTolerance
V
CC
GND5%
Table 2: Reset Voltage Threshold Programming Selections
Time-Out
10%
Pin Configuration
SOP-8
(Top View)
PBRST
TD
TOL
GND
1
2
3
4
8
7
6
5
Vcc
ST
RST
RST
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AAT3532
MicroPower™ Microprocessor Reset Circuit
Absolute Maximum Ratings (T
=25°C unless otherwise noted)
A
SymbolDescriptionValueUnits
V
CC
V
I/O
T
A
T
S
T
LEAD
V
ESD
Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time.
Note 1: Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
VCCto GND-0.5 to 6V
Voltage on I/O pins relative to GND-0.5 to (VCC+0.5)V
Operating Temperature Range-40 to 85°C
Storage Temperature Range-65 to 150°C
Maximum Soldering Temperature (at Leads) for 10s300°C
ESD Rating1—HBM2000V
Thermal Characteristics
SymbolDescriptionValueUnits
Θ
JA
P
D
Note 2: Mounted on an FR4 board.
Maximum Thermal Resistance
Maximum Power Dissipation
2
2
100°C/W
1.25W
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AAT3532
MicroPower™ Microprocessor Reset Circuit
DC Electrical Characteristics (V
= 4.5V to 5.5V, TA= -40 to 85°C unless otherwise noted.
4.254.374.49V
Input Leakage ST, TOL-1.01.0µA
Output Current RST
2
VOH= 2.4V-8.0mA
Current RST2, RSTVOL= 0.4V10.0mA
ST and PBRST Input High2.0VCC+0.3V
ST and PBRST Input Low-0.30.8V
RST Output LeakageVOH= V
CC
= 4.5V to 5.5V, TA= -40 to 85°C unless otherwise noted.
IN
1.0µA
Typical values are at TA=25°C)
SymbolDescriptionConditionsMinTypMaxUnits
C
IN
C
OUT
t
PB
t
PBD
t
RST
t
ST
t
TD
t
f
t
r
t
RPD
t
RPU
Notes:
1. Measured with outputs open and ST toggling at 100kHz, 50% duty cycle
2. RST is an open drain output
3. Guaranteed by design and not subject to production testing.
4. PBRST must remain low for greater than 20ms to guarantee a reset
Input Capacitance ST, TOL
Output Capacitance RST, RST
PBRST
4
PBRST DelayFig 21420ms
Reset Active Time2506101000ms
ST Pulse WidthFig 320ns
ST Time-out PeriodTD Pin = Open2506001000ms
VCCFall Time
VCCRise Time
3
3
VCCDetect to RST High and RST LowVCCFalling50µs
VCCDetect to RST Low and RST OpenVCCRising2506101000ms
3
3
TA= 25ºC5pF
TA= 25ºC7pF
Fig 220ms
TD Pin = 0V62.5150250ms
TD Pin = V
CC
50012002000ms
4.75V to 4.25V10µs
4.25V to 4.75V05µs
µA
43532.2001.11.0.9
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Functional Block Diagram
V
CC
TOL
AAT3532
MicroPower™ Microprocessor Reset Circuit
V
CC
Tolerance
Select
Reset
Generator
V
REF
RST
RST
PBRST
ST
TD
De-Bounce
Circuit
Applications Information
Power Monitor
The reset function monitors the VCCsupply to ensure
a microprocessor is correctly reset and is powered
up into a known condition following a power supply
failure. RST and RST will remain valid for Vcc voltages down to 1.4V.
The RST and RST pins are asserted whenever V
drops below the reset threshold voltage. This volt-
V
CC
CC
+4.75V (5% Trip Point)
+4.50V (10% Trip Point)
Watchdog
Timer
Detector
GND
+5V
Watchdog
Timer
age can be set by programming the TOL pin.
Connecting TOL to V
sets the 10% tolerance of
CC
the VCCsupply (typically 4.37V for VCC= 5V).
Connecting TOL to GND sets the 5% tolerance of
the VCCsupply (typically 4.62V for VCC= 5V). The
reset pin is guaranteed to remain asserted for a
minimum period of 250ms after VCChas risen
above the reset threshold voltage.
RST output is an open drain output. For correct
operation, a pull-up resistor of 10kΩ should be con-
nected between this output and VCC.
0V
RESET output delay (V
Rising)
CC
RST
RST
t
RPU
RESET output delay (V
t
RPD
Falling)
CC
Figure 1. Reset Output Delay
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AAT3532
MicroPower™ Microprocessor Reset Circuit
Applications Information
Manual Reset
The PBRST pin makes it possible to manually
reset the system by either directly connecting a
mechanical push-button between the PBRST pin
t
PBD
PBRST
RESET
RESET
and GND or connecting to a logic low output.
Internal de-bounce circuitry is provided to reduce
the effect of noise glitches at the input. The signal
should remain low for a minimum of 20ms for correct operation. Once the PBRST signal is released
(or goes to a logic high), RESET (RESET) remains
asserted for a minimum of 250ms.
t
PB
t
RST
Figure 2 Push-button Reset
Watchdog Timer
The watchdog timer monitors the microprocessor
to ensure that the system is functioning correctly.
The ST pin of the AAT3532 can be derived from the
microprocessor data signals, address signals,
and/or I/O signals. The watchdog timer function
forces the RST and RST signals into the active
state when the ST input is not toggled by a predetermined time. This time period is set by the logic
state of the TD pin as shown in Table 1. The timer
t
ST
ST
t
TD
starts once the RST signals become inactive. If the
watchdog timer does not receive a high-to-low transition within the specified timeout period, then the
RST signals are activated for a minimum 250ms. In
normal operation the timer should receive a transition from the microprocessor within the timeout
period, in which case the timer is reset and normal
operation continues.
The AAT3532 will accept and recognize ST pulses
down to a minimum of 20ns wide.