Page 1
AAT3215
150mA CMOS High Performance LDO
General Description
The AAT3215 MicroPower™ Low Dropout Linear
Regulator is ideally suited for portable applications
where low noise, extended battery life and small
size are critical. The AAT3215 has been specifically designed for very low output noise performance, fast transient response and high power supply rejection ratio (PSRR), making it ideal for powering sensitive RF circuits.
Other features include low quiescent current, typically 95µA, and low dropout voltage which is typically less than 140mV at full output current. The
device is output short circuit protected and has a
thermal shutdown circuit for additional protection
under extreme conditions.
The AAT3215 also features a low-power shutdown
mode for extended battery life. A reference bypass
pin has been provided to improve PSRR performance and output noise, by connecting an external
capacitor from the AAT3215's reference output to
ground.
The AAT3215 is available in a space saving 5-pin
SOT-23 or 8-pin SC70-JW package in 8 factory
programmed voltages of 2.5V, 2.7V, 2.8V, 2.85V,
2.9V, 3.0V, 3.3V, or 3.5V.
PowerLinear
Features
• Low Dropout - 140mV at 150mA
• Guaranteed 150mA Output
• High accuracy ±1.5%
• 95µA Quiescent Current
• High Power Supply Ripple Rejection
• 70 dB at 1kHz
• 50 dB at 10kHz
• Very low self noise 45µVrms/rtHz
• Fast line and load transient response
• Short circuit protection
• Over-Temperature protection
• Uses Low ESR ceramic capacitors
• Noise reduction bypass capacitor
• Shutdown mode for longer battery life
• Low temperature coefficient
• 8 Factory programmed output voltages
• SOT-23 5-pin or SC70-JW 8-pin package
Applications
• Cellular Phones
• Notebook Computers
• Portable Communication Devices
• Personal Portable Electronics
• Digital Cameras
™
Preliminary Information
Typical Application
V
IN
IN
OUT
AAT3215
ON/OFF
1µF
GND GND
3215.2002.03.0.91 1
EN
GND
BYP
10nF
2.2µF
V
OUT
Page 2
Pin Descriptions
AAT3215
150mA CMOS High Performance LDO
Pin #
SOT23-5 SC70JW-8
1 5, 6 IN Input voltage pin - should be decoupled with 1µF or greater
2 8 GND Ground connection pin
3 7 EN Enable pin - this pin is internally pulled high. When pulled low
4 1 BYP Bypass capacitor connection - to improve AC ripple rejection,
5 2, 3, 4 OUT Output pin - should be decoupled with 2.2µF capacitor.
Symbol Function
capacitor.
the PMOS pass transistor turns off and all internal circuitry
enters low-power mode, consuming less than 1µA.
connect a 10nF capacitor to GND. This will also provide a soft
start function.
Pin Configuration
SOT-23-5 SC70JW-8
(Top View) (Top View)
IN
GND
EN
1
OUT
5
2
3BYP
4
BYP
OUT
OUT
OUT
1 2
1
2
3
4
8
7
6
5
GND
EN
IN
IN
2 3215.2002.03.0.91
Page 3
AAT3215
150mA CMOS High Performance LDO
Absolute Maximum Ratings (T
=25°C unless otherwise noted)
A
Symbol Description Value Units
V
IN
I
OUT
T
J
T
LEAD
Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time.
Input Voltage 6 V
DC Output Current PD/(VIN-VO)mA
Operating Junction Temperature Range -40 to 150 °C
Maximum Soldering Temperature (at leads, 10 sec) 300 °C
Thermal Information
Symbol Description Rating Units
Θ
JA
P
D
Note 1: Mounted on a demo board.
Maximum Thermal Resistance1(SOT23-5, SC70JW-8) 190 °C/W
Maximum Power Dissipation1(SOT23-5, SC70JW-8) 526 mW
Recommended Operating Conditions
Symbol Description Rating Units
V
IN
T Ambient Temperature Range -40 to +85 °C
Electrical Characteristics (V
-40 to 85°C unless otherwise noted. Typical values are TA=25°C)
Input Voltage (V
IN=VOUT(NOM)
+1V, I
=1mA, C
OUT
=2.2µF, CIN=1µf, C
OUT
+0.3) to 5.5 V
OUT
BYP
=10nF, TA=
Symbol Description Conditions Min Typ Max Units
T
=25°C -1.5 1.5 %
A
TA=-40 to 85°C -2.5 2.5 %
95 150 µA
+2V, I
IN
=150mA, 1 mV
OUT
1 kHz 70
1MHz 47
∆V
OUT/VOUT
∆V
V
OUT
I
OUT
V
DO
I
SC
I
Q
I
SD
(line) Dynamic Line Regulation VIN=V
OUT
Output Voltage Tolerance I
Output Current V
Dropout Voltage
1
Short Circuit Current V
= 1mA to 150mA
OUT
> 1.2V 150 mA
OUT
I
= 150mA 140 250 mV
OUT
< 0.4V 600 mA
OUT
Ground Current VIN= 5V, No load, EN = V
Shutdown Current VIN= 5V, EN = 0V 1 µA
*∆V
IN
Line Regulation VIN= V
+ 1 to 5.5V 0.07 %/V
OUT
+1V to V
OUT
OUT
TR/TF=2µs
∆V
(load) Dynamic Load Regulation I
OUT
V
V
EN(L)
EN(H)
I
EN
Enable Threshold Low 0.6 V
Enable Threshold High 1.5 V
Leakage Current on Enable Pin VEN= 5V 1 µA
PSRR Power Supply Rejection Ratio I
T
SD
T
HYS
e
N
Over Temp Shutdown Threshold 150 °C
Over Temp Shutdown Hysteresis 10 °C
Output Noise Noise Power BW = 300Hz-50kHz 45 µVrms/rtHz
= 1mA to 150mA, TR<5µs 30 mV
OUT
=10mA, C
OUT
=10nF 10kHz 50 dB
BYP
TC Output Voltage Temp. Coeff. 22 ppm/°C
Note 1: VDOis defined as VIN- V
OUT
when V
is 98% of nominal.
OUT
3215.2002.03.0.91 3
Page 4
Typical Characteristics
(Unless otherwise noted, VIN= 5V, TA= 25°C)
AAT3215
150mA CMOS High Performance LDO
Dropout Voltage vs. Temperature
200
180
160
140
120
100
80
60
40
Dropout Voltage (mV)
20
0
-40 -20 0 20 40 60 80 100 120
IL=150mA
IL=100mA
IL=50mA
Temperature (°C)
Dropout Voltage vs. Output Current
200
180
160
140
120
100
80
60
40
Dropout Voltage (mV)
20
0
0 50 100 150
Output Current (mA)
Dropout Characteristics
3.1
3.0
2.9
2.8
2.7
I
=10mA
OUT
I
=0mA
OUT
I
=150mA
OUT
I
=100mA
OUT
I
=50mA
OUT
2.9 3.0 3.1 3.2 3.3
Vin
Ground Current vs. Input Voltage
120
V
=3.0V
OUT
100
(µA)
GND
I
80
60
40
20
0
I
=0
OUT
23 45
I
OUT
I
OUT
=5mA
V
=150mA
IN
Ground Current vs. Temperature
V
=3.0V
OUT
105
100
95
(µA)
GND
I
90
85
80
-50 0 50 100 150
Temperature (°C)
3.014
3.013
3.012
3.011
3.009
Output Voltage
3.008
3.007
Output Voltage vs. Temperature
3.01
-50 0 50 100 150
Temperature (°C)
4 3215.2002.03.0.91
Page 5
Typical Characteristics
(Unless otherwise noted, VIN= 5V, TA= 25°C)
AAT3215
150mA CMOS High Performance LDO
V
OUT
3.04
3.03
3.02
3.01
3.00
2.99
2.98
On/Off Transient Response
No C
10mA
BYP
V
150mA
Capacitor
EN (2V/div)
(1V/div)
OUT
100µs/div
Line Transient Response
5µs/div
On/Off Transient Response
C
=10nF
BYP
EN (2V/div)
V
(1V/div)
10mA
OUT
150mA
5ms/div
Load Transient Response
6
5
4
IN
3
V
2
1
0
V
OUT
3.10
3.05
3.00
2.95
2.90
2.85
2.80
100 µs/div
500
400
300
200
100
0
-100
(mA)
OUT
I
Short Circuit Current
Power Supply Rejection Ratio vs.
Frequency
1.2
1
0.8
0.6
Isc(A)
0.4
0.2
0
10ms/div
3215.2002.03.0.91 5
90
80
70
60
50
40
30
PSRR (dB)
20
10
0
10 100 1k 10k 100k 1m 10m
I
OUT
=150mA
C
OUT
=10µf
Frequency (Hz)
4.7µf
2.2µf
1.0µf
Page 6
Typical Characteristics
(Unless otherwise noted, VIN= 5V, TA= 25°C)
Output Self Noise
500
(50nVrms/√Hz per DIV)
0
Noise Amplitude in nVrms/√Hz
10
100 1k 10k 100k 1m 10m
Frequency (Hz)
AAT3215
150mA CMOS High Performance LDO
6 3215.2002.03.0.91
Page 7
Functional Block Diagram
AAT3215
150mA CMOS High Performance LDO
IN
EN
BYP
OUT
Over-Current
Protection
Over-Temperature
Protection
Error
Amplifier
Voltage
Reference
GND
Functional Description
The AAT3215 is intended for LDO regulator applications where output current load requirements
range from no load to 150mA.
The advanced circuit design of the AAT3215 provides excellent input to output isolation, which
allows for good power supply ripple rejection characteristics. To optimize for very low output self
noise performance, a bypass capacitor pin has
been provided to decrease noise generated by the
internal voltage reference. This bypass capacitor
will also enhance PSRR behavior. The two combined characteristics of low noise and high PSRR
make the AAT3215 a truly high performance LDO
regulator especially well suited for circuit applications which are sensitive to their power source.
3215.2002.03.0.91 7
The LDO regulator output has been specifically
optimized to function with low cost, low ESR ceramic capacitors. However, the design will allow for
operation over a wide range of capacitor types.
The device enable circuit is provided to shutdown the
LDO regulator for power conservation in portable
products. The enable circuit has an additional output
capacitor discharge circuit to assure sharp application circuit turn off upon device shutdown.
This LDO regulator has complete short circuit and
thermal protection. The integral combination of
these two internal protection circuits give the
AAT3215 a comprehensive safety system during
extreme adverse operating conditions. Device
power dissipation is limited to the package type
and thermal dissipation properties. Refer to the
thermal considerations discussion in the section for
details on device operation at maximum output current loads.
Page 8
AAT3215
150mA CMOS High Performance LDO
Applications Information
To assure the maximum possible performance is
obtained from the AAT3215, please refer to the following application recommendations.
Input Capacitor
Typically a 1µF or larger capacitor is recommended for CINin most applications. A CINcapacitor is
not required for basic LDO regulator operation.
However, if the AAT3215 is physically located more
than 3 centimeters from an input power source, a
CINcapacitor will be needed for stable operation.
CINshould be located as close to the device VINpin
as practically possible. CINvalues greater than
1µF will offer superior input line transient response
and will assist in maximizing the highest possible
power supply ripple rejection.
Ceramic, tantalum or aluminum electrolytic capacitors may be selected for CIN. There is no specific
capacitor ESR requirement for CIN. However, for
150mA LDO regulator output operation, ceramic
capacitors are recommended for CINdue to their
inherent capability over tantalum capacitors to withstand input current surges from low impedance
sources such as batteries in portable devices.
Output Capacitor
For proper load voltage regulation and operational
stability, a capacitor is required between pins V
and GND. The C
the LDO regulator ground pin should be made as
direct as practically possible for maximum device
performance.
The AAT3215 has been specifically designed to
function with very low ESR ceramic capacitors.
Although the device is intended to operate with
these low ESR capacitors, it is stable over a very
wide range of capacitor ESR, thus it will also work
with higher ESR tantalum or aluminum electrolytic
capacitors. However, for best performance,
ceramic capacitors are recommended.
Typical output capacitor values for maximum output
current conditions range from 1µF to 10µF.
Applications utilizing the exceptionally low output
noise and optimum power supply ripple rejection
characteristics of the AAT3215 should use 2.2µF or
greater for C
without limit.
. If desired, C
OUT
capacitor connection to
OUT
may be increased
OUT
OUT
In low output current applications where output
load is less then 10mA, the minimum value for
C
can be as low as 0.47µF.
OUT
Bypass Capacitor and Low Noise
Applications
A bypass capacitor pin is provided to enhance the
very low noise characteristics of the AAT3215 LDO
regulator. The bypass capacitor is not necessary
for operation of the AAT3215. However, for best
device performance, a small ceramic capacitor
should be placed between the Bypass pin (BYP)
and the device ground pin (GND). The value of
C
may range from 470pF to 10nF. For lowest
BYP
noise and best possible power supply ripple rejection performance a 10nF capacitor should be used.
To practically realize the highest power supply ripple rejection and lowest output noise performance,
it is critical that the capacitor connection between
the BYP pin and GND pin be direct and PCB traces
should be as short as possible. Refer to the PCB
Layout Recommendations section of this document for examples.
There is a relationship between the bypass capacitor value and the LDO regulator turn on time. In
applications where fast device turn on time is
desired, the value of C
In applications where low noise performance and/
or ripple rejection are less of a concern, the bypass
capacitor may be omitted. The fastest device turn
on time will be realized when no bypass capacitor
is used.
DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. For this reason, the use of a low leakage,
high quality ceramic (NPO or COG type) or film
capacitor is highly recommended.
should be reduced.
BYP
Capacitor Characteristics
Ceramic composition capacitors are highly recommended over all other types of capacitors for use
with the AAT3215. Ceramic capacitors offer many
advantages over their tantalum and aluminum electrolytic counterparts. A ceramic capacitor typically
has very low ESR, is lower cost, has a smaller PCB
footprint and is non-polarized. Line and load transient response of the LDO regulator is improved by
using low ESR ceramic capacitors. Since ceramic
capacitors are non-polarized, they are not prone to
incorrect connection damage.
8 3215.2002.03.0.91
Page 9
AAT3215
150mA CMOS High Performance LDO
Applications Information
Equivalent Series Resistance (ESR): ESR is a very
important characteristic to consider when selecting a
capacitor. ESR is the internal series resistance associated with a capacitor, which includes lead resistance, internal connections, size and area, material
composition and ambient temperature. Typically
capacitor ESR is measured in milliohms for ceramic
capacitors and can range to more than several ohms
for tantalum or aluminum electrolytic capacitors.
Ceramic Capacitor Materials: Ceramic capacitors
less than 0.1µF are typically made from NPO or
COG materials. NPO and COG materials are typically tight tolerance very stable over temperature.
Larger capacitor values are typically composed of
X7R, X5R, Z5U and Y5V dielectric materials. Large
ceramic capacitors, typically greater then 2.2µF are
often available in the low cost Y5V and Z5U
dielectrics. These two material types are not recommended for use with LDO regulators since the
capacitor tolerance can vary more than ±50% over
the operating temperature range of the device. A
2.2µF Y5V capacitor could be reduced to 1µF over
temperature, this could cause problems for circuit
operation. X7R and X5R dielectrics are much more
desirable. The temperature tolerance of X7R
dielectric is better than ±15%.
Capacitor area is another contributor to ESR.
Capacitors which are physically large in size will have
a lower ESR when compared to a smaller sized
capacitor of an equivalent material and capacitance
value. These larger devices can improve circuit transient response when compared to an equal value
capacitor in a smaller package size.
Consult capacitor vendor data sheets carefully
when selecting capacitors for LDO regulators.
Enable Function
The AAT3215 features an LDO regulator enable/
disable function. This pin (EN) is active high and is
compatible with CMOS logic. To assure the LDO
regulator will switch on, the EN turn on control level
must be greater than 2.0 volts. The LDO regulator
will go into the disable shutdown mode when the
voltage on the EN pin falls below 0.6 volts. If the
enable function is not needed in a specific application, it may be tied to VINto keep the LDO regulator in a continuously on state.
When the LDO regulator is in the shutdown mode,
an internal 1.5kΩ resistor is connected between
and GND. This is intended to discharge C
V
OUT
when the LDO regulator is disabled. The internal
1.5kΩ has no adverse effect on device turn on time.
OUT
Short Circuit Protection
The AAT3215 contains an internal short circuit protection circuit that will trigger when the output load
current exceeds the internal threshold limit. Under
short circuit conditions the output of the LDO regulator will be current limited until the short circuit
condition is removed from the output or LDO regulator package power dissipation exceeds the
device thermal limit.
Thermal Protection
The AAT3215 has an internal thermal protection circuit which will turn on when the device die temperature exceeds 150°C. The internal thermal protection circuit will actively turn off the LDO regulator
output pass device to prevent the possibility of over
temperature damage. The LDO regulator output
will remain in a shutdown state until the internal die
temperature falls back below the 150°C trip point.
The combination and interaction between the short
circuit and thermal protection systems allow the
LDO regulator to withstand indefinite short circuit
conditions without sustaining permanent damage.
No-Load Stability
The AAT3215 is designed to maintain output voltage regulation and stability under operational noload conditions. This is an important characteristic
for applications where the output current may drop
to zero.
Reverse Output to Input Voltage
Conditions and Protection
Under normal operating conditions a parasitic
diode exists between the output and input of the
LDO regulator. The input voltage should always
remain greater then the output load voltage maintaining a reverse bias on the internal parasitic
diode. Conditions where V
should be avoided since this would forward bias
the internal parasitic diode and allow excessive
current flow into the V
the LDO regulator.
OUT
might exceed V
OUT
pin possibly damaging
IN
3215.2002.03.0.91 9
Page 10
AAT3215
150mA CMOS High Performance LDO
Applications Information
In applications where there is a possibility of V
exceeding VINfor brief amounts of time during normal operation, the use of a larger value CINcapacitor is highly recommended. A larger value of C
with respect to C
will effect a slower CINdecay
OUT
rate during shutdown, thus preventing V
exceeding VIN. In applications where there is a
greater danger of V
exceeding VINfor extended
OUT
periods of time, it is recommended to place a schottky diode across VINto V
ode to VINand anode to V
(connecting the cath-
OUT
). The Schottky diode
OUT
forward voltage should be less than 0.45 volts.
Thermal Considerations and High
Output Current Applications
The AAT3215 is designed to deliver a continuous
output load current of 150mA under normal operating conditions.
The limiting characteristic for the maximum output
load current safe operating area is essentially
package power dissipation and the internal preset
thermal limit of the device. In order to obtain high
operating currents, careful device layout and circuit
operating conditions need to be taken into account.
The following discussions will assume the LDO regulator is mounted on a printed circuit board utilizing
the minimum recommended footprint as stated in
the layout considerations section of the document.
At any given ambient temperature (TA) the maximum package power dissipation can be determined by the following equation:
P
Constants for the AAT3215 are T
mum junction temperature for the device which is
125°C and ΘJA= 190°C/W, the package thermal
resistance. Typically, maximum conditions are calculated at the maximum operating temperature
where TA= 85°C, under normal ambient conditions
TA= 25°C. Given TA= 85°, the maximum package
power dissipation is 211mW. At TA= 25°C°, the
maximum package power dissipation is 526mW.
The maximum continuous output current for the
AAT3215 is a function of the package power dissi-
D(MAX)
= [T
J(MAX)
- TA] / Θ
J(MAX)
JA
, the maxi-
OUT
OUT
IN
from
pation and the input to output voltage drop across
the LDO regulator. Refer to the following simple
equation:
I
OUT(MAX)
For example, if VIN= 5V, V
I
OUT(MAX)
< 264mA. If the output load current were to
< P
D(MAX)
/ (VIN- V
OUT
OUT
= 3V and TA= 25°,
)
exceed 264mA or if the ambient temperature were to
increase, the internal die temperature will increase.
If the condition remained constant, the LDO regulator thermal protection circuit will activate.
To figure what the maximum input voltage would be
for a given load current refer to the following equation. This calculation accounts for the total power
dissipation of the LDO Regulator, including that
caused by ground current.
P
D(MAX)
= (VIN- V
OUT)IOUT
+ (VINx I
GND
)
This formula can be solved for VINto determine the
maximum input voltage.
V
IN(MAX)
= (P
D(MAX)
+ (V
OUT
x I
OUT
)) / (I
OUT
+ I
GND
)
The following is an example for an AAT3215 set for
a 2.5 volt output:
From the discussion above, P
D(MAX)
was deter-
mined to equal 526mW at TA= 25°C.
V
= 2.5 volts
OUT
I
= 150mA
OUT
I
= 150µA
GND
V
V
=(526mW+(2.5Vx150mA))/(150mA +150µA)
IN(MAX)
= 6.00V
IN(MAX)
Thus, the AAT3215 can sustain a constant 2.5V
output at a 150mA load current as long as V
IN
is ≤
6.00V at an ambient temperature of 25°C. 6.0V is
the absolute maximum voltage where an AAT3215
would never be operated, thus at 25°C, the device
would not have any thermal concerns or operational V
IN(MAX)
limits.
This situation can be different at 85°C. The following is an example for an AAT3215 set for a 2.5 volt
output at 85°C:
From the discussion above, P
D(MAX)
was deter-
mined to equal 211mW at TA= 85°C.
10 3215.2002.03.0.91
Page 11
Applications Information
Voltage Drop (V)
V
= 2.5 volts
OUT
I
= 150mA
OUT
I
= 150uA
GND
V
V
Higher input to output voltage differentials can be
obtained with the AAT3215, while maintaining
device functions within the thermal safe operating
area. To accomplish this, the device thermal
resistance must be reduced by increasing the heat
sink area or by operating the LDO regulator in a
duty cycled mode.
=(211mW+(2.5Vx150mA))/(150mA +150uA)
IN(MAX)
IN(MAX)
= 3.90V
AAT3215
150mA CMOS High Performance LDO
Device Duty Cycle vs. V
V
= 2.5V @ 25 C
OUT
3.5
3
2.5
2
1.5
1
0.5
0
0 10203040 50607080 90100
Duty Cycle (%)
DROP
200mA
For example, an application requires VIN= 4.2V
while V
= 2.5V at a 150mA load and TA= 85°C.
OUT
VINis greater than 3.90V, which is the maximum
safe continuous input level for V
OUT
= 2.5V at
150mA for TA= 85°C. To maintain this high input
voltage and output current level, the LDO regulator
must be operated in a duty cycled mode. Refer to
the following calculation for duty cycle operation:
P
I
GND
I
OUT
is assumed to be 211mW
D(MAX)
= 150µA
= 150mA
VIN= 4.2 volts
V
= 2.5 volt
OUT
%DC=100(P
D(MAX)
/((VIN-V
OUT)IOUT
+(VINxI
GND
))
%DC=100(211mW/((4.2V-2.5V)150mA+(4.2Vx150µA))
%DC = 85.54%
For a 150mA output current and a 2.7volt drop
across the AAT3215 at an ambient temperature of
85°C, the maximum on time duty cycle for the
device would be 85.54%.
The following family of curves show the safe operating area for duty cycled operation from ambient
room temperature to the maximum operating level.
Device Duty Cycle vs. V
V
= 2.5V @ 50 C
OUT
3.5
3
2.5
2
1.5
1
0.5
Voltage Drop (V)
0
0 10203040 50607080 90100
Duty Cycle (%)
Device Duty Cycle vs. V
V
= 2.5V @ 85 C
OUT
3.5
3
2.5
2
1.5
1
0.5
Voltage Drop (V)
0
0 10203040 50607080 90100
200mA
150mA
Duty Cycle (%)
DROP
200mA
150mA
DROP
100mA
3215.2002.03.0.91 11
Page 12
AAT3215
150mA CMOS High Performance LDO
Applications Information
High Peak Output Current Applications
Some applications require the LDO regulator to
operate at continuous nominal level with short
duration high current peaks. The duty cycles for
both output current levels must be taken into
account. To do so, one would first need to calculate the power dissipation at the nominal continuous level, then factor in the additional power dissipation due to the short duration high current peaks.
For example, a 2.5V system using a AAT3215IGV-
2.5-T1 operates at a continuous 100mA load current level and has short 150mA current peaks. The
current peak occurs for 378µs out of a 4.61ms period. It will be assumed the input voltage is 4.2V.
First the current duty cycle in percent must be calculated:
% Peak Duty Cycle: X/100 = 378µs/4.61ms
% Peak Duty Cycle = 8.2%
The LDO Regulator will be under the 100mA load
for 91.8% of the 4.61ms period and have 150mA
peaks occurring for 8.2% of the time. Next, the
continuous nominal power dissipation for the
100mA load should be determined then multiplied
by the duty cycle to conclude the actual power dissipation over time.
P
P
P
P
P
P
= (VIN- V
D(MAX)
D(100mA)
D(100mA)
D(91.8%D/C)
D(91.8%D/C)
D(91.8%D/C)
= (4.2V - 2.5V)100mA + (4.2V x 150µA)
OUT)IOUT
= 170.6mW
= %DC x P
= 0.918 x 170.6mW
= 156.6mW
The power dissipation for 100mA load occurring for
91.8% of the duty cycle will be 156.6mW. Now the
power dissipation for the remaining 8.2% of the
duty cycle at the 150mA load can be calculated:
P
P
P
P
P
P
= (VIN- V
D(MAX)
D(150mA)
D(150mA)
D(8.2%D/C)
D(8.2%D/C)
D(8.2%D/C)
= (4.2V - 2.5V)150mA + (4.2V x 150mA)
OUT)IOUT
= 255.6mW
= %DC x P
= 0.082 x 255.6mW
= 21mW
The power dissipation for 150mA load occurring for
8.2% of the duty cycle will be 21mW. Finally, the
+ (VINx I
D(100mA)
+ (VINx I
D(150mA)
GND
GND
)
)
two power dissipation levels can summed to determine the total true power dissipation under the varied load.
P
D(total)
P
D(total)
P
D(total)
= P
D(100mA)
= 156.6mW + 21mW
= 177.6mW
+ P
D(150mA)
The maximum power dissipation for the AAT3215
operating at an ambient temperature of 85°C is
211mW. The device in this example will have a total
power dissipation of 177.6mW. This is well within
the thermal limits for safe operation of the device.
Printed Circuit Board Layout
Recommendations
In order to obtain the maximum performance from
the AAT3215 LDO regulator, very careful attention
must be considered in regard to the printed circuit
board (PCB) layout. If grounding connections are
not properly made, power supply ripple rejection,
low output self noise and transient response can
be compromised.
Figure 1 shows a common LDO regulator layout
scheme. The LDO Regulator, external capacitors
(CIN, C
nected to a common ground plane. This type of layout will work in simple applications where good
power supply ripple rejection and low self noise are
not a design concern. For high performance applications, this method is not recommended.
The problem with the layout in Figure 1 is the bypass
capacitor and output capacitor share the same
ground path to the LDO regulator ground pin along
with the high current return path from the load back
to the power supply. The bypass capacitor node is
connected directly to the LDO regulator internal reference, making this node very sensitive to noise or
ripple. The internal reference output is fed into the
error amplifier, thus any noise or ripple from the
bypass capacitor will be subsequently amplified by
the gain of the error amplifier. This effect can
increase noise seen on the LDO regulator output as
well as reduce the maximum possible power supply
ripple rejection. There is PCB trace impedance
between the bypass capacitor connection to ground
and the LDO regulator ground connection. When
the high load current returns through this path, a
small ripple voltage is created, feeding into the C
loop.
OUT
and C
) and the load circuit are all con-
BYP
BYP
12 3215.2002.03.0.91
Page 13
Applications Information
I
V
IN
DC INPUT
IN
C
IN
I
RIPPLE
V
IN
Regulator
EN
I
GND
LDO
GND
AAT3215
150mA CMOS High Performance LDO
I
LOAD
V
OUT
BYP
I
BYP
+ noise
C
GND
LOOP
BYP
C
BYP
C
OUT
R
LOAD
GND
R
TRACE
I
return + noise and ripple
LOAD
Figure 1: Common LDO Regulator Layout with C
Figure 2 shows the preferred method for the bypass
and output capacitor connections. For low output
noise and highest possible power supply ripple
rejection performance, it is critical to connect the
I
V
IN
DC INPUT
GND
IN
C
IN
V
IN
LDO
Regulator
EN
GND
I
GND
I
RIPPLE
R
TRACE
I
return + noise and ripple
LOAD
I
Figure 2: Recommended LDO Regulator Layout
Evaluation Board Layout
The AAT3215 evaluation layout follows the recommend printed circuit board layout procedures and
R
TRACE
Ripple feedback loop
BYP
bypass and output capacitor directly to the LDO regulator ground pin. This method will eliminate any
load noise or ripple current feedback through the
LDO regulator.
I
LOAD
V
OUT
BYP
C
BYP
only
BYP
R
TRACE
can be used as an example for good application
layouts.
Note: Board layout shown is not to scale.
R
TRACE
R
TRACE
R
C
TRACE
R
OUT
TRACE
R
LOAD
Figure 3: Evaluation board Figure 4: Evaluation board Figure 5: Evaluation board
component side layout solder side layout top side silk screen layout /
assembly drawing
3215.2002.03.0.91 13
Page 14
Ordering Information
AAT3215
150mA CMOS High Performance LDO
Output Voltage Package Marking
2.5V SOT-23-5 N/A AAT3215IGV-2.5-T1
2.7V SOT-23-5 N/A AAT3215IGV-2.7-T1
2.8V SOT-23-5 N/A AAT3215IGV-2.8-T1
2.85V SOT-23-5 N/A AAT3215IGV-2.85-T1
2.9V SOT-23-5 N/A AAT3215IGV-2.9-T1
3.0V SOT-23-5 N/A AAT3215IGV-3.0-T1
3.3V SOT-23-5 N/A AAT3215IGV-3.3-T1
3.5V SOT-23-5 N/A AAT3215IGV-3.5-T1
2.5V SC70JW-8 N/A AAT3215IJS-2.5-T1
2.7V SC70JW-8 N/A AAT3215IJS-2.7-T1
2.8V SC70JW-8 N/A AAT3215IJS-2.8-T1
2.85V SC70JW-8 N/A AAT3215IJS-2.85-T1
2.9V SC70JW-8 N/A AAT3215IJS-2.9-T1
3.0V SC70JW-8 N/A AAT3215IJS-3.0-T1
3.3V SC70JW-8 N/A AAT3215IJS-3.3-T1
Bulk Tape and Reel
Part Number
3.5V SC70JW-8 N/A AAT3215IJS-3.5-T1
14 3215.2002.03.0.91
Page 15
Package Information
SOT-23-5
e
S1
H
E
D
A2
S
A
A1
b
AAT3215
150mA CMOS High Performance LDO
Dim
A 1.00 1.30 0.039 0.051
A1 0.00 0.10 0.000 0.004
A2 0.70 0.90 0.028 0.035
b 0.35 0.50 0.014 0.020
c 0.10 0.25 0.004 0.010
D 2.70 3.10 0.106 0.122
E 1.40 1.80 0.055 0.071
e 1.90 0.075
H 2.60 3.00 0.102 0.118
L 0.37 0.015
S 0.45 0.55 0.018 0.022
c
L
S1 0.85 1.05 0.033 0.041
Θ 1° 9° 1° 9°
Millimeters Inches
Min Max Min Max
SC70JW-8
eee
Dim
Millimeters Inches
Min Max Min Max
E 2.10 BSC 0.083 BSC
E1 1.75 2.00 0.069 0.079
E
L 0.23 0.40 0.009 0.016
A 1.10 0.043
A1 0 0.10 0.004
A2 0.70 1.00 0.028 0.039
D 2.00 BSC 0.079 BSC
b
D
c
A2
A
Θ1
L
E1
0.048REF
Θ
A1
e 0.50 BSC 0.020 BSC
b 0.15 0.30 0.006 0.012
c 0.10 0.20 0.004 0.008
Θ 08º08º
Θ 1 4º 10º 4º 10º
3215.2002.03.0.91 15
Page 16
AAT3215
150mA CMOS High Performance LDO
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Advanced Analogic Technologies, Inc.
1250 Oakmead Parkway, Suite 310, Sunnyvale, CA 94086
Phone (408) 524-9684
Fax (408) 524-9689
16 3215.2001.11.0.9
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