Datasheet A8032L-40, A8032L-24, A8032L, A8032-40, A8032-24 Datasheet (AMICC)

A8032 Series

Preliminary 8 Bit Microcontroller

Document Title

8 Bit Microcontroller

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue November 27, 1998

PRELIMINARY (November, 1998, Version 0.0) AMIC Technology, Inc.

A8032 Series

Preliminary 8 Bit Microcontroller

Features

n 8-bit CMOS microcontroller
n Fully static design with power saving idle mode and

power down mode

n Low standby current at full supply voltage
n Versions for 12/24/40MHZ operating frequency
n On chip 256B RAM
n Four 8-bit bidirectional ports
n 64K bytes external data memory space

General Description

The AMIC A8032 is a high-performance 8-bit
microcontroller. It is compatible with the industry
standard 80C52 microcontroller series.

Pin Configurations

n P-DIP n PLCC

VCC

T2,P1.0

T2EX,P1.1

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RST

RXD,P3.0

TXD,P3.1
INT0,P3.2
INT1,P3.3

T0,P3.4
T1,P3.5

WR,P3.6

RD,P3.7

XTAL2
XTAL1

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33

A8032

32
31
30
29
28
27
26
25
24
23
22
21

P0.0,AD0
P0.1,AD1
P0.2,AD2
P0.3,AD3
P0.4,AD4
P0.5,AD5
P0.6,AD6
P0.7,AD7
EA
ALE
PSEN
P2.7,A15
P2.6,A14
P2.5,A13
P2.4,A12
P2.3,A11
P2.2,A10
P2.1,A9
P2.0,A8

n Three 16-bit Timers/Counters (Timer 2 with up/down

counter feature)

n One full duplex serial port
n Boolean processor
n Six interrupt sources, two priority levels
n Available in 40-pin P-DIP and 44-pin PLCC packages

The A8032 contains a 256B RAM, four 8-bit bidirectional
parallel ports, three 16-bit timer/counters, a serial port
and six interrupt sources with two priority levels.
The A8032 has supports 64KB external data memory.

P1.4

P1.3

P1.2

P1.1,T2EX

P1.0,T2

GND

VCC

P0.0,AD0

P0.1,AD1

P0.2,AD2

P0.3,AD3

1

2

3

4

5
P1.5
P1.6

P1.7

RST

RXD,P3.0

NC

TXD,P3.1

INT0, P3.2

INT1,P3.3

T0,P3.4
T1,P3.5

6

7
8

9
10

11
12
13
14
15
16
17

A8032L

20

19

18

22

21

4443424140

25

24

23

39
38
37
36
35
34
33
32
31
30
29

28

27

26

P0.4,AD4
P0.5,AD5
P0.6,AD6
P0.7,AD7

EA
NC
ALE

PSEN
P2.7,A15
P2.6,A14
P2.5,A13

NC

GND

XTAL1

RD,P3.7

WR,P3.6

XTAL2

P2.0,A8

P2.1,A9

P2.3,A11

P2.2,A10

P2.4,A12

PRELIMINARY (November, 1998, Version 0.0) 1 AMIC Technology, Inc.

Block Diagram

A8032 Series

CPU CORE

SFR

256B
RAM

PSEN ALE EA RST

TIMING AND

CONTROL

PORT 1

P1.0-P1.7

XTAL1 XTAL2

OSCILLATOR

TIMER 2 INTERRUPT

P0.0-P0.7

PORT 0

(AD0-AD7)

ADDRESS

SERIAL PORT TIMER 0.1

PORT 3

P3.0-P3.7

P2.0-P2.7

PORT 2

A8-A15

ADDRESS

PRELIMINARY (November, 1998, Version 0.0) 2 AMIC Technology, Inc.

Pin Description

RXD

TXD

INT1

WR

RD

EA

Pin No. Symbol I/O Description

A8032 Series

1 - 8 P1.0 - P1.7

9 RST I Reset input, active high. It must be kept high for at least two

10 - 17 P3.0 - P3.7 I/O Port3. Port3 is a bidirectional I/O port with internal pull-ups. Port3

18 XTAL2 O Crystal2. This is the output of crystal oscillator. It is the inversion

I/O Port1. Port1 is a bidirectional I/O port with internal pull-ups. Pin

P1.0 and P1.1 also provide alternate functions as follows:

I/O P1.0 T2 Timer/Counter2 external input/clock out

I P1.1 T2EX Timer/Counter2 capture/reload input

machine cycles to be recognized by the processor

pins also serve alternate functions as follows:

I P3.0

O P3.1

I P3.2
I P3.3
I P3.4 T0 Timer/Counter 0 input

I P3.5 T1 Timer/Counter 1 input

O P3.6
O P3.7

of XTAL1

INT0

Serial receive port
Serial transmit port
External interrupt 0
External interrupt 1

External data memory write strobe
External data memory read strobe

19 XTAL1 I Crystal1. This is the input of crystal oscillator. It can be driven by

an external clock

20 GND I Ground

21 - 28 P2.0 - P2.7 I/O Port2. Port2 is a bidirectional I/O port with internal pull-ups. Port2

is also the multiplexed upper-order address bus during accesses
to external data memory

29

30 ALE O Address latch enable, active high. ALE is used to enable the

31

32 - 39 P0.7 - P0.0 I/O Port0. Port0 is an open drain, bidirectional I/O port. Port0 is also

40 VCC I Power supply

PSEN

O Program Store Enable, active low. The read strobe to external

program memory.
when fetching external program memory

address latch that separates the data on Port 0

I External Access enable, active low. It is held low to enable the

device to fetch code from external program memory

the multiplexed low-order address bus during accesses to external
data memory

is activated in each machine cycle

PSEN

PRELIMINARY (November, 1998, Version 0.0) 3 AMIC Technology, Inc.

A8032 Series

Functional Description

The A8032 is a high speed 8-bit microcontroller. The architecture consists of a core controller, four general purposes I/O
ports, 256 bytes RAM internal register and a serial port.
This microcontroller supports 111 opcodes and executes instructions in a 6-clock bus cycle. It can reference both a 64K
program address space and a 64K data storage space.

Timer/Counter 0, 1 and 2

Timer 0,1 and 2 each consist of two 8-bit data registers.
These are called TL0 and TH0 for Timer 0. TL1 and TH1
for Timer 1, and TL2 and TH2 for Timer 2. The TMOD
and TCON registers support control function for Timer 0
and Timer 1. The T2CON register provides control
function for Timer 2. When operating reload/capture
mode, RCAP2H and RCAP2L will be used.

Interrupt

The A8032 provides 6 interrupt modes. These consist of
2 external interrupts, 3 internal interrupts and a serial
port interrupt.
The enable/disable interrupt is controlled by IE register in
SFR.
The priority of interrupts is controlled by IP register in
SFR.

Serial Port Transfer

The A8032 provides a full duplex serial transfer function.
This function is controlled by SCON register in SFR.
And the data is storaged in SBUF register during
transmitting and receiving.

Oscillator Characteristics

N/C

EXTERNAL

OSCILLATOR

SIGNAL

XTAL 2

XTAL 1

V

SS

Figure 2. External Clock Drive configuration

RESET

The external reset signal must be held high for at least
two machine cycles during the oscillator running.
After reset, the ports are held high, SP register to 07H,
all of the other SFR registers except SBUF to 00H, and
SBUF is not reset.

The oscillator connections are shown as Figure 1. And
Figure 2. When quartz crystal is used, C1 and C2 are
30pF shown in Figure 1. When external clock is used,
the internal clock will be gotten through a divide-by-two
flip-flop. When starting up, the input loading for XTAL1
pin is 100pF. This is due to interaction between the
amplifier and its feedback capacitance interaction. After
the external signal meets the VIL and VIH specification
the capacitance will not exceed 20pF.

C2

XTAL 2

C1

XTAL 1
V

SS

C1,C2 = 30pF ± 10pF for Crystals

Figure 1. Oscillator Connections

PRELIMINARY (November, 1998, Version 0.0) 4 AMIC Technology, Inc.

Recommended DC Operating Conditions (TA = -25°C to + 85°C)

PSEN

PSEN

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V

GND Ground 0 0 0 V

VIH* Input High Voltage 2.4 - VCC+0.2 V

VIL Input Low Voltage 0 - 0.8 V

* XTAL1 is a CMOS input. RESET is a Schmit trigger input.

The min. of VIH is 3.5 Volts for these two pins.

A8032 Series

Absolute Maximum Ratings*

VCC to GND . . . . . . . . . . . . . . . . . . . . . –0.3V to +7.0V

IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V

Operating Temperature, Topr . . . . . . . -25°C to + 85°C

Storage Temperature, Tstg . . . . . . . . . -55°C to + 125°C

Power Dissipation1*, Pr . . . . . . . . . . . . . . . . . . . . . . 1W

Soldering Temperature & Time . . . . . . . . . 260°C, 10sec

1* : Operating frequency is 40MHZ

*Comments

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 5V ± 10%)

Symbol Parameter Min. Max. Unit Conditions

1

ILI 
ILO 

ICC Operating Current - 50 mA

VOL1

VOL2

VOH1

VOH2

C1 Input Pin Capacitance - 10 pF

Input Leakage Current - 10
Output Leakage Current - 10

Output Low Voltage
(PORT1, PORT2 and PORT3)

Output Low Voltage
(ALE,

Output High Voltage
(PORT1, PORT2 and PORT3)

Output High Voltage
(ALE,

and PORT0)

and PORT0)

- 0.45 V IOL = 2mA

- 0.45 V IOL = 4mA

2.4 - V

2.4 - V

µA
µA

VIN = GND to VCC
VI/O = GND to VCC

foper = 40MHZ
External oscillator is on

XTAL1 pin
No load

IOH = -100µA

IOH = -400µA

1MHZ , 25°C

1. For RESET pin, the ILI  max. is 300 µA, since it has an internal pull-low of approx. 30KΩ resistor.

PRELIMINARY (November, 1998, Version 0.0) 5 AMIC Technology, Inc.

A8032 Series

RD

RD

WR

WR

WR

WR

AC Characteristics (TA = -25°C to + 85°C, VCC = 5V ± 10%)

Symbol Parameter Min. Max. Unit

Program Memory Cycle

tAP ALE Pulse Width 2tck – 20
tALS Address Valid to ALE Low 1tck - ns
tALH Address Hold from ALE Low 1tck - ns

top

tAO

tOI

tIDO

tIFO

Pulse Width

PSEN

ALE Low to

2

Low to Valid Instruction in

PSEN

Input Instruction Hold after
Input Instruction Float after

PSEN

Low

PSEN

PSEN

High

High

3tck - 20

External Clock

fOPER Clock Frequency 0 40 MHZ

3

tCK

tCKH

tCKL

4

4

Clock Period 25 - ns
Clock High Time 10 - ns
Clock Low Time 10 - ns

1

1

- ns

- ns

1tck - ns

- 2tck ns

- 1tck ns

- 1tck ns

Data Memory Cycle

tPR

tPD
tDHR
tDFR

tAR

tWP

tDS

tDHW

tAW

Pulse Width

Low to Valid Data in
Data Hold from RD High
Data Float from RD High
ALE Low to RD Low

Pulse Width
Valid Data to
Data Hold from
ALE Low to

Low

High

Low

6tck - 20

6tck - 20

1

- ns

- 4tck ns
0 2tck ns
0 2tck ns

3tck 3tck + 20

1

1

- ns
1tck - ns
1tck - ns
3tck 3tck + 20

1

Serial Port Cycle

tSCK Serial Port Clock 12tck - ns

tKI Clock Rising Edge to Valid Input Data - 11tck ns

tIKH Input Data to Serial Clock Rising Clock Hold Time 0 - ns
tOKS Output Data to Serial Clock Rising Edge Setup Time 11tck - ns
tOKH Output Data to Serial Clock Rising Edge Hold Time 1tck - ns

ns

ns

1. This 20 ns is due to buffer driving delay and wire loading.

2. Instruction cycle time is 12 tck.

3. tck = 1/ foper

4. There are no duty cycle requirements on the XTAL1 input.

PRELIMINARY (November, 1998, Version 0.0) 6 AMIC Technology, Inc.

Timing Waveforms

Program Memory Cycle

S1 S2 S3 S4 S5 S6 S1

A8032 Series

XTAL 1

ALE

PSEN

PORT 2

PORT 0

Clock Input Waveform

t

AP

t

AO

t

OP

t

ALS

A8 - A15 A8 - A15

t

t

ALH

t

OI

t

IHO

IFO

A0 - A7 A0 - A7

INSTRUCTION IN INSTRUCTION IN

t

XTAL 1

CKH

t

CKL

t

CK

PRELIMINARY (November, 1998, Version 0.0) 7 AMIC Technology, Inc.

Timing Waveforms (continued)

S4

Data Memory Read Cycle

A8032 Series

S4 S5 S6 S1 S2 S3

XTAL 1

ALE

PSEN

PORT 2
PORT 0

RD

Data Memory Write Cycle

S4 S5 S6 S1 S2 S3

XTAL 1

ALE

PSEN

PORT 2

A0-A7

S4

S5 S6

A8-A15

t

AR

t

RD

t

RP

DATA IN
t

DHR

t

DFR

A0-A7

S5 S6

A8-A15

PORT 0

A0-A7

t

DS

DATA OUT

t

DHW

WR

t

t

AW

WP

Serial Port Timing – Shift Register Mode

INSTRUCTION

0 1 2 3

4

ALE

t

SCK

CLOCK

t

VALID

OKH

t

KI

t

IKH

VALID VALID VALID VALID VALID VALID VALID

OUTPUT DATA

INPUT DATA

t

OKS

0 1 2 3 4 5 6 7

PRELIMINARY (November, 1998, Version 0.0) 8 AMIC Technology, Inc.

5 6

7 8

SET TI

SET RI

A8032 Series

Ordering Information

Part No. RAM FREQ (MHZ) Package

A8032-12 256 Byte 12 40L P-DIP

A8032L-12 256 Byte 12 44L PLCC

A8032-24 256 Byte 24 40L P-DIP

A8032L-24 256 Byte 24 44L PLCC

A8032-40 256 Byte 40 40L P-DIP

A8032L-40 256 Byte 40 44L PLCC

PRELIMINARY (November, 1998, Version 0.0) 9 AMIC Technology, Inc.

A8032 Series

Package Information

P-DIP 40L Outline Dimensions unit: inches/mm

D

40

E1

21

1

AL

A2

B

B

1

Symbol

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

20

A1

Base Plane

Seating Plane

e

1

θ 0

º/15º

E

C

e

A

A - - 0.210 - - 5.344
A1 0.015 - - 0.381 - ­A2 0.150 0.155 0.160 3.810 3.937 4.064

B 0.018 TYP 0.457 TYP
B1

0.050 TYP 1.270 TYP

C - 0.010 - - 0.254 ­D 2.049 2.054 2.059 52.045 52.172 52.299

E 0.590 0.600 0.610 14.986 15.240 15.494
E1 0.542 0.547 0.552 13.767 13.894 14.021

e1 0.100 TYP 2.540 TYP

L 0.120 0.130 0.140 3.048 3.302 3.556
eA 0.622 0.642 0.662 15.799 16.307 16.815

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E1 does not include resin fins.

PRELIMINARY (November, 1998, Version 0.0) 10 AMIC Technology, Inc.

A8032 Series

Package Information

PLCC 44L Outline Dimension unit: inches/mm

H

D

D

16

44 40

7

17

L

18

Seating Plane

39

E

HE

29

28

A2

A

0.150 REF0.020 MIN

e

0.050 REF

G

0.630/0.590

D

b

0.022/0.016
b

1

0.032/0.026

A1

0.004

y

D

Dimensions in inches Dimensions in mm

Symbol

Min Nom Max Min Nom Max

A - - 0.185 - - 4.70

D 0.648 0.653 0.658 16.46 16.59 16.71

E 0.648 0.653 0.658 16.46 16.59 16.71
HD 0.680 0.690 0.700 17.27 17.53 17.78
HE 0.680 0.690 0.700 17.27 17.53 17.78

L 0.090 0.100 0.110 2.29 2.54 2.79

θ 0° - 10° 0° - 10°

GE

0.630/0.590

0.014/0.0008
C

Notes:

1. Dimensions D and E do not include resin fins.

2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.

PRELIMINARY (November, 1998, Version 0.0) 11 AMIC Technology, Inc.