Page 1
6B273
Data Sheet
26180.122
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
LOGIC
V
DD
LATCHES
20
SUPPLY
19
IN
8
IN
18
7
OUT
17
8
16
OUT
7
OUT
15
6
14
OUT
5
13
IN
6
12
IN
5
11
STROBE
Dwg. PP-015-2
OUT
OUT
OUT
OUT
1
2
IN
1
3
IN
2
4
1
5
2
6
3
7
4
8
IN
3
9
IN
4
10
LATCHES
CLEAR
GROUND
Note that the A6B273KA (DIP) and the A6B273KLW
(SOIC) are electrically identical and share a common
terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at T
= 25°C
A
Output Voltage, VO............................... 50 V
Output Drain Current,
Continuous, IO.......................... 150 mA*
Peak, IOM................................... 500 mA†
Single-Pulse Avalanche Energy,
EAS................................................. 30 mJ
Logic Supply Voltage, VDD.................. 7.0 V
Input Voltage Range,
VI................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD........................................... See Graph
Operating Temperature Range,
TA................................. -40°C to +125°C
Storage Temperature Range,
TS................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
8-BIT LATCHED
DMOS POWER DRIVER
The A6B273KA and A6B273KLW combine eight (positive-edgetriggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power
loads. The CMOS inputs and latches allow direct interfacing with
microprocessor-based systems. Use with TTL may require appropriate
pull-up resistors to ensure an input logic high.
The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs
are capable of sinking up to 500 mA. Similar devices with reduced
r
are available as the A6273KA/KLW.
DS(on)
The A6B273KA is furnished in a 20-pin dual in-line plastic
package. The A6B273KLW is furnished in a 20-lead wide-body,
small-outline plastic package (SOIC) with gull-wing leads for surfacemount applications. Copper lead frames, reduced supply current
requirements, and low on-state resistance allow both devices to sink
150 mA from all outputs continuously, to ambient temperatures over
85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 150 mA Output Current (all outputs simultaneously)
■ 5 Ω Typical
■ Low Power Consumption
■ Replacements for TPIC6B273N and TPIC6B273DW
Always order by complete part number:
Part Number Package R
A6B273KA 20-pin DIP 55°C/W 25°C/W
A6B273KLW 20-lead SOIC 70°C/W 17°C/W
r
DS(on)
θJA
R
θJC
Page 2
6B273
8-BIT LATCHED
DMOS POWER DRIVER
2.5
2.0
SUFFIX 'A', R = 55
1.5
1.0
0.5
0
25
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
SUFFIX 'LW
50 75 100 125 150
AMBIENT TEMPERATURE IN °C
IN
θ
J
A
', R = 70
θ
J
A
°C/W
°C/W
V
Dwg. GS-004A
DD
LOGIC SYMBOL
1
11
2
3
18
R
C1
1D 4
1D
1D8
1D9
1D12
1D13
1D
1D19
5
6
7
14
15
16
17
Dwg. FP-046-1
OUT
Dwg. EP-010-16
DMOS POWER DRIVER OUTPUTLOGIC INPUTS
FUNCTION TABLE
Inputs
CLEAR STROBE IN
X
LXXH
HHL
HLH
HLXR
L = Low Logic Level
H = High Logic Level
X = Irrelevant
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
W
Copyright © 2000, Allegro MicroSystems, Inc.
OUT
X
Dwg. EP-063
Page 3
FUNCTIONAL BLOCK DIAGRAM
6B273
8-BIT LATCHED
DMOS POWER DRIVER
IN
STROBE
IN
LOGIC
SUPPLY
IN
IN
IN
1
2
V
DD
3
4
5
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
OUT
OUT
OUT
OUT
OUT
1
2
3
4
5
www.allegromicro.com
IN
IN
IN
CLEAR
(ACTIVE LOW)
6
7
8
D
C1
CLR
D
C1
CLR
D
C1
CLR
OUT
6
OUT
7
OUT
8
GROUND
Dwg. FP-016-2
Page 4
6B273
8-BIT LATCHED
DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD............... 4.5 V to 5.5 V
High-Level Input Voltage, V
Low-level input voltage, V
............................ ≥ 0.85V
IH
................................. ≤0.15V
IL
DD
DD
ELECTRICAL CHARACTERISTICS at T
= +25°C, V
A
= 5 V, tir = t
DD
≤ 10 ns (unless otherwise
if
specified).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Logic Supply Voltage V
Output Breakdown V
(BR)DSXIO
Voltage
Off-State Output I
Current
Static Drain-Source r
On-State Resistance
Nominal Output I
Current
Logic Input Current I
Prop. Delay Time t
DD
DSX
DS(on)
ON
IH
I
IL
PLH
Operating 4.5 5.0 5.5 V
= 1 mA 50 — — V
VO = 40 V, V
VO = 40 V, VDD = 5.5 V, T
IO = 100 mA, V
IO = 100 mA, VDD = 4.5 V, T
IO = 350 mA, V
V
= 0.5 V, T
DS(on)
VI = V
= 5.5 V — — 1.0 µA
DD
VI = 0, V
= 5.5 V — 0.1 5.0 µA
DD
= 125°C — 0.15 8.0 µA
A
= 4.5 V — 4.2 5.7 Ω
DD
= 125°C— 6.8 9.5 Ω
A
= 4.5 V (see note) — 5.5 8.0 Ω
DD
= 85°C—90—mA
A
= 5.5 V — — -1.0 µA
DD
IO = 100 mA, CL = 30 pF — 150 — ns
t
Output Rise Time t
Output Fall Time t
Supply Current I
DD(OFF)
I
DD(ON)
PHL
r
f
IO = 100 mA, CL = 30 pF — 90 — ns
IO = 100 mA, CL = 30 pF — 200 — ns
IO = 100 mA, CL = 30 pF — 200 — ns
V
= 5.5 V, Outputs off — 20 100 µA
DD
V
= 5.5 V, Outputs on — 150 300 µA
DD
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Page 5
TIMING REQUIREMENTS
6B273
8-BIT LATCHED
DMOS POWER DRIVER
INx
STROBE
OUTPUTx
t
t
PHL
50%
su(D)
t
su(D)
50%
t
50%
t
PLH
h(D)
10%
t
r
Input Active Time Before Strobe
(Data Set-Up Time), t
.............................................. 20 ns
su(D)
Input Active Time After Strobe
(Data Hold Time), t
Input Pulse Width, t
................................................... 20 ns
h(D)
....................................................... 40 ns
w(D)
Input Logic High, VIH................................................ ≥ 0.85V
Input Logic Low, VIL................................................. ≤ 0.15V
CC
CC
t
h(D)
90%
t
f
Dwg. WP-036-1
www.allegromicro.com
Page 6
6B273
8-BIT LATCHED
DMOS POWER DRIVER
TEST CIRCUITS
INPUT
I
O
V
O
t
av
IAS = 500 mA
V
(BR)DSX
V
O(ON)
EAS = IAS x V
(BR)DSX
DUT
x tAV/2
+15 V
OUT
Dwg. EP-066
Single-Pulse Avalanche Energy Test Circuit
and Waveforms
10.5 Ω
200 mH
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Page 7
TYPICAL CHARACTERISTICS
6B273
8-BIT LATCHED
DMOS POWER DRIVER
www.allegromicro.com
Page 8
6B273
8-BIT LATCHED
DMOS POWER DRIVER
TYPICAL CHARACTERISTICS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Page 9
TERMINAL DESCRIPTIONS
Terminal No. Terminal Name Function
6B273
8-BIT LATCHED
DMOS POWER DRIVER
1 CLEAR
2 IN
1
When (active) LOW, all latches are reset and all outputs go HIGH (turn OFF).
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN1 = HIGH, OUT1 = LOW).
3
IN
2
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN2 = HIGH, OUT2 = LOW).
4 OUT
5 OUT
6 OUT
7 OUT
8
IN
1
2
3
4
3
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN3 = HIGH, OUT3 = LOW).
9
IN
4
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN4 = HIGH, OUT4 = LOW).
10 GROUND Reference terminal for all voltage measurements.
11 STROBE A CMOS dynamic input to all latches. Data on each INx terminal is loaded
into its associated latch on a low-to-high STROBE transition.
12
IN
5
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN5 = HIGH, OUT5 = LOW).
13
IN
6
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN6 = HIGH, OUT6 = LOW).
14 OUT
15 OUT
16 OUT
17 OUT
18
IN
5
6
7
8
7
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN7 = HIGH, OUT7 = LOW).
19
IN
8
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN8 = HIGH, OUT8 = LOW).
20 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).
www.allegromicro.com
Page 10
6B273
8-BIT LATCHED
DMOS POWER DRIVER
20
0.280
0.240
A6B273KA
Dimensions in Inches
(controlling dimensions)
11
0.014
0.008
0.300
BSC
0.430
MAX
0.210
MAX
7.11
6.10
0.015
MIN
1
0.070
0.045
0.022
0.014
1.060
0.980
0.100
BSC
10
0.005
MIN
0.150
0.115
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
0.355
20
1
1.77
1.15
26.92
24.89
2.54
BSC
11
10
0.13
MIN
0.204
7.62
BSC
10.92
MAX
5.33
MAX
0.39
MIN
0.558
0.356
3.81
2.93
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Dwg. MA-001-20 mm
Page 11
A6B273KLW
Dimensions in Inches
(for reference only)
6B273
8-BIT LATCHED
DMOS POWER DRIVER
20 11
0.2992
0.2914
0.020
1 2
0.013
0.0926
0.1043
0.0040
3
MIN.
20
0.050
0.5118
0.4961
BSC
Dimensions in Millimeters
(controlling dimensions)
11
0.419
0.394
0° TO 8°
0.0125
0.0091
0.050
0.016
Dwg. MA-008-20 in
0.32
0.23
7.60
7.40
0.51
0.33
2.65
2.35
1
0.10
2
MIN.
3
13.00
12.60
1.27
BSC
10.65
10.00
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
0° TO 8°
Dwg. MA-008-20 mm
1.27
0.40
Page 12
6B273
8-BIT LATCHED
DMOS POWER DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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