Datasheet A6818SEP, A6818EEP, A6818EA Datasheet (Allegro)

6818

DABiC-IV, 32-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVER

26182.128A

Data Sheet

A6818xA

LOAD

1

V

SUPPLY

SERIAL

DATA OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BLANKING

GROUND

BB

2

338

32

4

31

5

30

6

29

7

28

8

27

9

26

10

25

11

24

12

23

13

22

14

21

15

20

16

19

17

18

18

17

19

20

LATCHES

BLNK

REGISTER

LATCHES

REGISTER

ABSOLUTE MAXIMUM RATINGS

at TA = 25°C

Logic Supply Voltage, VDD................... 7.0 V

Driver Supply Voltage, V
Continuous Output Current Range,

I

......................... -40 mA to +15 mA

OUT

Input Voltage Range,

VIN....................... -0.3 V to VDD + 0.3 V

Package Power Dissipation,

........................................ See Graph

P

D

Operating Temperature Range, T

(Suffix ‘E–’) .................. -40°C to +85°C

(Suffix ‘S–’) .................. -20

Storage Temperature Range,

TS............................... -55°C to +125°C

Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.

................... 60 V

BB

LOGIC

40

V

DD

SUPPLY

SERIAL

39

DATA IN

OUT

OUT

37

OUT

36

35

OUT

34

OUT

33

OUT

32

OUT

31

OUT

30

OUT

OUT

29

OUT

28

OUT

27

OUT

26

25

OUT

24

OUT

23

OUT

22

STROBE

ST

CLOCK

21

CLK

Dwg. PP-029-4

A

°C to +85°C

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

The A6818– devices combine a 32-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6818– features an increased data input rate (com­pared with the older UCN/UCQ5818–F) and a controlled output slew
rate.

The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
typical serial-data input rates are up to 33 MHz.

A CMOS serial data output permits cascade connections in applica­tions requiring additional drive lines. Similar devices are available as
the A6809– and A6810– (10 bits), A6811– (12 bits), and A6812– (20
bits).

The A6818– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro­magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK­ING input high. The pnp active pull-downs will sink at least 2.5 mA.

Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A) or minimum-area
surface-mount PLCC (suffix -EP). Copper lead frames, low logic­power dissipation, and low output-saturation voltages allow these
devices to drive most multiplexed vacuum-fluorescent displays over
the maximum operating temperature range.

FEATURES

■ Controlled Output Slew Rate

■ High-Speed Data Storage

■ 60 V Minimum

Output Breakdown

■ High Data Input Rate

■ PNP Active Pull-Downs

Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A or -EP). Always
order by complete part number, e.g., A6818SEP .

■ Low Output-Saturation Voltages

■ Low-Power CMOS Logic

and Latches

■ Improved Replacements
for SN75518N, SN75518NF,
UCN5818–, and UCQ5818–

6818

32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

TYPICAL INPUT CIRCUIT

V

DD

IN

Dwg. EP-010-5

OUT

OUT

OUT

A6818xEP

SERIAL

SUPPLY

43

25

16

OUT

OUT

DATA IN

42

26

OUT

1

2

OUT

41

2

LATCHES

REGISTER

OUT

8

27

15

14

OUT

OUT

40

28

NC

3

39

OUT

4

38

37

36

35

34

33

19

32

31

30

OUT

13

29

NC

Dwg. PP-059-2

30

32

31

OUT

OUT

OUT

NC

6

5

4

7

29

8

9

10

11

12

13

14

15

16

17

19

LATCHES

REGISTER

19

18

OUT

20

17

OUT

18

NC

SERIAL

3

2

BLNK

21

22

GROUND

BLANKING

LOAD

SUPPLY

DATA OUT

1

BB

V

CLK

23

CLOCK

LOGIC

44

DD

V

ST

24

STROBE

TYPICAL OUTPUT DRIVER

V

BB

OUT

N

Dwg. EP-021-19

3.0

2.5

SUFFIX 'A', R = 36°C/W

θJA

2.0

1.5

SUFFIX 'EP', R = 46°C/W

θJA

1.0

0.5

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

0

25

50 75 100 125 150

AMBIENT TEMPERATURE IN °C

Dwg. GP-025A

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Copyright © 1998, 2000 Allegro MicroSystems, Inc.

LATCHED SOURCE DRIVER

FUNCTIONAL BLOCK DIAGRAM

6818

32-BIT SERIAL-INPUT,

CLOCK

SERIAL

DATA IN

STROBE

BLANKING

GROUND

OUT1OUT

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

OUT

2

3

OUT

N

V

DD

MOS

BIPOLAR

V

BB

LOGIC
SUPPLY

SERIAL
DATA OUT

LOAD
SUPPLY

Dwg. FP-013-1

TRUTH TABLE

Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe
Input Input I

1I2I3

HHR

LLR

XR

1R2R3

XXX...X X X L R1R2R3... R

P1P2P3... P

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

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1R2

1R2

... I

... R

... R

... R

N-1IN

N-2RN-1

N-2RN-1

N-1RN

N-1PN

Output Input I1I2I3... I

R

N-1

R

N-1

R

N

P

N

HP1P2P3... P

X X X ... X X H L L L ... L L

N-1IN

N-1 RN

N-1 PN

Blanklng I1I2I3... I

LP1P2P3... P

N-1

N-1 PN

I

N

6818

32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature

range (A6818E- and A6818K-), VBB = 60 V unless otherwise noted.

Limits @ VDD = 3.3 V Limits @ VDD = 5 V

Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units

V

Output Leakage Current I

Output Voltage V

Output Pull-Down Current I

OUT(1)IOUT

V

OUT(0)IOUT

OUT(0)

Input Voltage V

V

Input Current I

I

Input Clamp Voltage V

Serial Data Output Voltage V

OUT(1)IOUT

V

OUT(0)IOUT

Maximum Clock Frequency f

Logic Supply Current I

Load Supply Current I

-to-

Blanking

Strobe

Output Delay t

-to-

Output Delay t

DD(1)

I

DD(0)

BB(1)

I

BB(0)

dis(BQ)

t

en(BQ)

p(STH-QL)RL

t

p(STH-QH)RL

Output Fall Time t

Output Rise Time t

CEX

IN(1)

IN(0)

IN(1)

IN(0)

IK

c

f

r

= 0 V — <-0.1 -15 — <-0.1 -15 µA

OUT

= -25 mA 57.5 58.3 — 57.5 58.3 — V

= 1 mA — 1.0 1.5 — 1.0 1.5 V

V

= 5 V to V

OUT

BB

2.5 5.0 — 2.5 5.0 — mA

2.2 ——3.3 —— V

——1.1 ——1.7 V

VIN = V

DD

— <0.01 1.0 — <0.01 1.0 µA

VIN = 0.8 V — <-0.01 -1.0 — <-0.01 -1.0 µA

IIN = -200 µA — -0.8 -1.5 — -0.8 -1.5 V

= -200 µA 2.8 3.05 — 4.5 4.75 — V

= 200 µA — 0.15 0.3 — 0.15 0.3 V

10 33 — 10 33 — MHz

All Outputs High — 0.25 0.75 — 0.3 1.0 mA

All Outputs Low — 0.25 0.75 — 0.3 1.0 mA

All Outputs High, No Load — 4.5 9.0 — 4.5 9.0 mA

All Outputs Low — 0.2 20 — 0.2 20 µA

CL = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 µs

CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 µs

= 2.3 kΩ, CL ≤ 30 pF — 0.7 2.0 — 0.7 2.0 µs

= 2.3 kΩ, CL ≤ 30 pF — 1.8 3.0 — 1.8 3.0 µs

RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs

RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs

Output Slew Rate dV/dt RL = 2.3 kΩ, CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/µs

Clock

-to-

Serial Data Out Delay t

p(CH-SQX)IOUT

= ±200 µA — 50 ——50 — ns

Negative current is defined as coming out of (sourcing) the specified device terminal.

Typical data is is for design information only and is at TA = +25°C.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

32-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVER

TIMING REQUIREMENTS and SPECIFICATIONS

(Logic Levels are VDD and Ground)

C

6818

CLOCK

SERIAL

DATA IN

SERIAL

DATA OUT

STROBE

BLANKING

OUT

BLANKING

OUT

50%

A B

DATA

N

N

50%

t

p(CH-SQX)

t

p(STH-QH)

t

p(STH-QL)

10%

DATA

90%

t

dis(BQ)

50%

D E

50%

LOW = ALL OUTPUTS ENABLED

HIGH = ALL OUTPUTS BLANKED (DISABLED)

50%

t

en(BQ)

t

r

DATA

10%

Dwg. WP-029

90%

DATA

t

f

A. Data Active Time Before Clock Pulse

(Data Set-Up Time), t

......................................... 25 ns

su(D)

B. Data Active Time After Clock Pulse

(Data Hold Time), t

C. Clock Pulse Width, t

D. Time Between Clock Activation and Strobe, t

E. Strobe Pulse Width, t

............................................... 25 ns

h(D)

............................................... 50 ns

w(CH)

....... 100 ns

su(C)

............................................. 50 ns

w(STH)

NOTE – Timing is representative of a 10 MHz clock. Signifi­cantly higher speeds are attainable.

Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.

www.allegromicro.com

Dwg. WP-030

Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.

When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.

6818

32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

40

0.580

0.485

A6818EA & A6811SA

Dimensions in Inches

(controlling dimensions)

21

0.015

0.008

0.600

BSC

0.700

MAX

0.250

MAX

14.73

12.32

0.015

MIN

12

0.070

0.030

0.022

0.014

40

12

1.77

0.77

4

3

2.095

1.980

0.100

BSC

20

0.005

MIN

0.200

0.115

Dwg. MA-003-40 in

Dimensions in Millimeters

(for reference only)

0.381

21

4

3

53.2

50.3

2.54

BSC

20

0.13

MIN

0.204

15.24

BSC

17.78

MAX

6.35

MAX

0.39

MIN

0.558

0.356

5.08

2.93

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Dwg. MA-003-40 mm

LATCHED SOURCE DRIVER

A6818EEP & A6818SEP

Dimensions in Inches

(controlling dimensions)

6818

32-BIT SERIAL-INPUT,

0.319

0.291

0.319

0.291

0.021

0.013

0.050

BSC

0.020

MIN

0.180

0.165

28

29

0.032

0.026

0.695

0.685

0.656

0.650

39

40

Dimensions in Millimeters

(for reference only)

28

0.656

0.650

144

0.695

0.685

INDEX AREA

2

18

17

7

6

Dwg. MA-005-44A in

18

29

17.65

17.40

16.662

16.510

0.812

0.661

39

16.662

16.510

144

17.65

17.40

40

8.10

7.39

8.10

7.39

0.533

0.331

1.27

BSC

0.51

MIN

4.57

4.20

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

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INDEX AREA

2

17

7

6

Dwg. MA-005-44A mm

6818

32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to

time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components

in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and

reliable. However, Allegro MicroSystems, Inc. assumes no responsi­bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]