Datasheet A6812SLW, A6812SEP, A6812SA, A6812ELW, A6812EEP Datasheet (Allegro)

A6812xA

LOAD

1

V

SUPPLY

SERIAL

DATA OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BLANKING

GROUND

BB

2

326

20

4

19

5

18

6

17

7

16

BLNK

LATCHES

REGISTER

8

15

9

14

10

13

11

12

12

11

13

14 27

LATCHES

REGISTER

ABSOLUTE MAXIMUM RATINGS

at TA = 25°C

Logic Supply Voltage, VDD................... 7.0 V

Driver Supply Voltage, V
Continuous Output Current Range,

I

......................... -40 mA to +15 mA

OUT

Input Voltage Range,

V

....................... -0.3 V to VDD + 0.3 V

IN

Package Power Dissipation,

P

........................................ See Graph

D

Operating Temperature Range, T

(Suffix ‘E–’) .................. -40°C to +85°C

(Suffix ‘S–’) .................. -20

Storage Temperature Range,

T

............................... -55°C to +125°C

S

Caution: These CMOS devices have input static
protection (Class 2) but are still susceptible to
damage if exposed to extremely high static
electrical charges.

................... 60 V

BB

LOGIC

28

V

DD

SUPPLY

SERIAL

27

DATA IN

OUT

OUT

25

OUT

24

OUT

23

22

OUT

21

OUT

20

OUT

19

OUT

18

OUT

17

OUT

28

16

STROBE

ST

15

CLOCK

CLK

Dwg. PP-029-7

A

°C to +85°C

26182.126A

Data Sheet

6812

DABiC-IV, 20-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVER

The A6812– devices combine a 20-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6812– features an increased data input rate (com-

1

2

3

4

5

6

7

8

9

10

pared with the older UCN/UCQ5812-F) and a controlled output slew
rate.

The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply, they
will operate to at least 10 MHz.

A CMOS serial data output permits cascade connections in applica­tions requiring additional drive lines. Similar devices are available as
the A6809– and A6810– (10 bits), A6811– (12 bits), and A6818– (32
bits).

The A6812– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro­magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK­ING input high. The pnp active pull-downs will sink at least 2.5 mA.

Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A), surface-mount
SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix

-EP). Copper lead frames, low logic-power dissipation, and low
output-saturation voltages allow these drivers to source 25 mA from all
outputs continuously to more than +43°C (suffix -LW), +61°C (suffix

-EP), or +77°C (suffix -A).

FEATURES

■ Controlled Output Slew Rate

■ High-Speed Data Storage

■ 60 V Minimum

Output Breakdown

■ High Data Input Rate

■ PNP Active Pull-Downs

Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6812SLW .

■ Low Output-Saturation Voltages

■ Low-Power CMOS Logic

and Latches

■ Improved Replacements
for TL5812–, UCN5812–,
and UCQ5812–

6812

20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

A6812xEP A6812xLW

OUT

OUT

LOAD

1

V

BB

2

326

4

19

5

18

6

17

7

16

8

9

10

13

11

12

13

BLNK

14 27

LATCHES

REGISTER

SERIAL

DATA IN

27

LATCHES

17

10

OUT

1

OUT

26

18

9

OUT

25

OUT

24

23

22

21

20

19

OUT

Dwg. PP-059-1

SUPPLY

SERIAL

DATA OUT

OUT

20

2

8

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BLANKING

GROUND

15

14

12

11

20

19

OUT

4

5

18

6

7

8

9

10

11

12

12

11

OUT

SERIAL

DATA OUT

OUT

3

2

LATCHES

REGISTER

14

13

GROUND

BLANKING

LOAD

SUPPLY

1

BB

V

CLK

15

CLOCK

LOGIC

SUPPLY

28

DD

V

REGISTER

ST

16

STROBE

LATCHES

REGISTER

V

ST

CLK

TYPICAL INPUT CIRCUIT

V

DD

DD

LOGIC

28

SUPPLY

SERIAL

27

DATA IN

OUT

OUT

25

OUT

24

OUT

23

22

OUT

21

OUT

20

OUT

19

OUT

18

OUT

17

OUT

28

16

STROBE

15

CLOCK

Dwg. PP-029-8

1

2

3

4

5

6

7

8

9

10

IN

Dwg. EP-010-5

TYPICAL OUTPUT DRIVER

V

BB

OUT

Dwg. EP-021-19

2.5

SUFFIX 'EP', R = 55

SUFFIX 'A', R = 45

2.0

θJA

1.5

S

U

F

F

IX

'LW

1.0

0.5

N

0

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

25

50 75 100 125 150

AMBIENT TEMPERATURE IN °C

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 2000, Allegro MicroSystems, Inc.

°C/W

', R

= 66

θJA

θ

J

A

°C/W

°C

/W

Dwg. GP-024-2

20-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVER

FUNCTIONAL BLOCK DIAGRAM

6812

CLOCK

SERIAL

DATA IN

STROBE

BLANKING

GROUND

OUT1OUT

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

OUT

2

3

OUT

N

V

DD

MOS

BIPOLAR

V

BB

LOGIC
SUPPLY

SERIAL
DATA OUT

LOAD
SUPPLY

Dwg. FP-013-1

TRUTH TABLE

Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe
Input Input I

1I2I3

HHR

LLR

XR

1R2R3

XXX...X X X L R1R2R3... R

P1P2P3... P

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

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1R2

1R2

... I

... R

... R

... R

N-1IN

N-2RN-1

N-2RN-1

N-1RN

N-1PN

Output Input I1I2I3... I

R

N-1

R

N-1

R

N

P

N

HP1P2P3... P

X X X ... X X H L L L ... L L

N-1IN

N-1 RN

N-1 PN

Blanklng I1I2I3... I

LP1P2P3... P

N-1

N-1 PN

I

N

6812

20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperature

range (A6812E-), VBB = 60 V unless otherwise noted.

Limits @ VDD = 3.3 V Limits @ VDD = 5 V

Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units

V

Output Leakage Current I

Output Voltage V

Output Pull-Down Current I

OUT(1)IOUT

V

OUT(0)IOUT

OUT(0)

Input Voltage V

V

Input Current I

I

Input Clamp Voltage V

Serial Data Output Voltage V

OUT(1)IOUT

V

OUT(0)IOUT

Maximum Clock Frequency f

Logic Supply Current I

Load Supply Current I

-to-

Blanking

Strobe

Output Delay t

-to-

Output Delay t

DD(1)

I

DD(0)

BB(1)

I

BB(0)

dis(BQ)

t

en(BQ)

p(STH-QL)RL

t

p(STH-QH)RL

Output Fall Time t

Output Rise Time t

CEX

IN(1)

IN(0)

IN(1)

IN(0)

IK

c

f

r

= 0 V — <-0.1 -15 — <-0.1 -15 µA

OUT

= -25 mA 57.5 58.3 — 57.5 58.3 — V

= 1 mA — 1.0 1.5 — 1.0 1.5 V

V

= 5 V to V

OUT

BB

2.5 5.0 — 2.5 5.0 — mA

2.2 ——3.3 —— V

——1.1 ——1.7 V

VIN = V

DD

— <0.01 1.0 — <0.01 1.0 µA

VIN = 0 V — <-0.01 -1.0 — <-0.01 -1.0 µA

IIN = -200 µA — -0.8 -1.5 — -0.8 -1.5 V

= -200 µA 2.8 3.05 — 4.5 4.75 — V

= 200 µA — 0.15 0.3 — 0.15 0.3 V

10* ——10* ——MHz

All Outputs High — 0.25 0.75 — 0.3 1.0 mA

All Outputs Low — 0.25 0.75 — 0.3 1.0 mA

All Outputs High, No Load — 3.0 6.0 — 3.0 6.0 mA

All Outputs Low — 0.2 20 — 0.2 20 µA

CL = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 µs

CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 µs

= 2.3 kΩ, CL ≤ 30 pF — 0.7 2.0 — 0.7 2.0 µs

= 2.3 kΩ, CL ≤ 30 pF — 1.8 3.0 — 1.8 3.0 µs

RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs

RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs

Output Slew Rate dV/dt RL = 2.3 kΩ, CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/µs

Clock

-to-

Serial Data Out Delay t

p(CH-SQX)IOUT

= ±200 µA — 50 ——50 — ns

Negative current is defined as coming out of (sourcing) the specified device terminal.

Typical data is is for design information only and is at TA = +25°C.

* Operation at a clock frequency greater than the specified minimum is possible but not warranteed.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

20-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVER

TIMING REQUIREMENTS and SPECIFICATIONS

(Logic Levels are VDD and Ground)

C

6812

CLOCK

SERIAL

DATA IN

SERIAL

DATA OUT

STROBE

BLANKING

OUT

BLANKING

OUT

50%

A B

DATA

N

N

50%

t

p(CH-SQX)

t

p(STH-QH)

t

p(STH-QL)

10%

DATA

t

dis(BQ)

90%

50%

D E

50%

LOW = ALL OUTPUTS ENABLED

HIGH = ALL OUTPUTS BLANKED (DISABLED)

50%

t

en(BQ)

t

r

DATA

10%

Dwg. WP-029

90%

DATA

t

f

A. Data Active Time Before Clock Pulse

(Data Set-Up Time), t

...................................... 25 ns

su(D)

B. Data Active Time After Clock Pulse

(Data Hold Time), t

C. Clock Pulse Width, t

D. Time Between Clock Activation and Strobe, t

E. Strobe Pulse Width, t

............................................ 25 ns

h(D)

............................................ 50 ns

w(CH)

su(C)

.......................................... 50 ns

w(STH)

.... 100 ns

NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable with increased supply voltage;
operation at high temperatures will reduce the specified
maximum clock frequency.

Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift

www.allegromicro.com

Dwg. WP-030

data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.

Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.

When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.

6812

20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

A6812EA & A6812SA

Dimensions in Inches

(controlling dimensions)

28

0.580

0.485

0.015

15

0.008

0.600

BSC

0.700

MAX

0.250

MAX

14.73

12.32

6.35

MAX

0.015

MIN

1 2

0.070

0.030

28

1 2

0.022

0.014

1.77

0.77

3

4

1.565

1.380

Dimensions in Millimeters

(for reference only)

3

4

39.7

35.1

0.100

BSC

2.54

BSC

14

0.005

MIN

0.200

0.115

Dwg. MA-003-28 in

0.381

15

14

0.13

MIN

0.204

15.24

BSC

17.78

MAX

0.39

MIN

0.558

0.356

5.08

2.93

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

4. Supplied in standard sticks/tubes of 12 devices.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Dwg. MA-003-28 mm

20-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVER

A6812EEP & A6812SEP

(add “TR” to part number for tape and reel)

Dimensions in Inches

(controlling dimensions)

18 12

6812

0.219

0.191

0.219

0.191

5.56

4.85

5.56

4.85

0.013

0.021

0.050

BSC

0.331

0.533

1.27

BSC

19

0.026

0.032

0.456

0.450

0.495

0.485

25

0.020

MIN

0.165

0.180

Dimensions in Millimeters

(for reference only))

19

0.812

0.661

11.58

11.43

12.57

12.32

25

INDEX AREA

0.495

0.485

128

0.456

0.450

INDEX AREA

26

18 12

11

5

4

Dwg. MA-005-28A in

11

5

12.57

12.32

128

11.582

11.430

0.51

MIN

4.57

4.20

26

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel.

www.allegromicro.com

4

Dwg. MA-005-28A mm

6812

20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

A6812ELW & A6812SLW

(add “TR” to part number for tape and reel)

Dimensions in Inches

(for reference only)

28 15

0.0125

0.0091

0.2992

0.2914

0.020

0.013

0.0926

0.1043

7.60

7.40

1

0.0040

28

0.419

0.394

0.050

0.016

2

3

0.7125

0.6969

MIN.

0.050

BSC

0° TO 8°

Dwg. MA-008-28A in

Dimensions in Millimeters

(controlling dimensions)

15

10.65

10.00

0.32

0.23

0.51

0.33

2.65

2.35

1

0.10

2

MIN.

3

18.10

17.70

1.27

BSC

0° TO 8°

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

1.27

0.40

Dwg. MA-008-28A mm

6812

20-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVER

www.allegromicro.com

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi­bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

6812

20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

POWER

INTERFACE DRIVERS

Function Output Ratings* Part Number

SERIAL-INPUT LATCHED DRIVERS

8-Bit (saturated drivers) -120 mA 50 V‡ 5895
8-Bit 350 mA 50 V 5821
8-Bit 350 mA 80 V 5822
8-Bit 350 mA 50 V‡ 5841
8-Bit 350 mA 80 V‡ 5842
8-Bit (constant-current LED driver) 75 mA 17 V 6275
8-Bit (DMOS drivers) 250 mA 50 V 6595
8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595
8-Bit (DMOS drivers) 100 mA 50 V 6B595

10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10

12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811

16-Bit (constant-current LED driver) 75 mA 17 V 6276

20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812

32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818
32-Bit 100 mA 30 V 5833
32-Bit (saturated drivers) 100 mA 40 V 5832

PARALLEL-INPUT LATCHED DRIVERS

4-Bit 350 mA 50 V‡ 5800

†

8-Bit -25 mA 60 V 5815
8-Bit 350 mA 50 V‡ 5801
8-Bit (DMOS drivers) 100 mA 50 V 6B273
8-Bit (DMOS drivers) 250 mA 50 V 6273

SPECIAL-PURPOSE DEVICES

Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804
Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259
Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259
Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259
Addressable 28-Line Decoder/Driver 450 mA 30 V 6817

* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.

Negative current is defined as coming out of (sourcing) the output.

† Complete part number includes additional characters to indicate operating temperature range and package style.

‡ Internal transient-suppression diodes included for inductive-load protection.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]