Datasheet A67L8316E-6, A67L8316E-5, A67L8316E, A67L7336E-6, A67L7336E-5 Datasheet (AMICC)
...Page 1
A67L8316/A67L8318/
A67L7332/A67L7336 Series
256K X 16/18, 128K X 32/36
Preliminary LVTTL, Pipelined DBATM SRAM
Document Title
256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue March 11, 1999 Preliminary
0.1 Change fast access time from 4.0/4.2/4.5/5.0 ns to December 29, 1999
4.5/5.0/6.0 ns
PRELIMINARY (December, 1999, Version 0.1) AMIC Technology, Inc.
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc
Page 2
A67L8316/A67L8318/
BW1,BW2
BW4
BW1
BW2
BW4
A67L7332/A67L7336 Series
256K X 16/18, 128K X 32/36
Preliminary LVTTL, Pipelined DBATM SRAM
Features
n Fast access time: 4.5/5.0/6.0 ns (117/100/83MHz)
n Direct Bus Alternation between READ and WRITE
cycles allows 100% bus utilization
n Signal +3.3V ± 5% power supply
n Individual Byte Write control capability
n Clock enable (
operations
) pin to enable clock and suspend
CEN
General Description
The AMIC Direct Bus Alternation™ (DBA™) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
The A67L8316, A67L8318, A67L7332, A67L7336
SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or
128K X 36 SRAM core with advanced synchronous
peripheral circuitry and a 2-bit burst counter. These
SRAMs are optimized for 100 percent bus utilization
without the insertion of any wait cycles during WriteRead alternation. The positive edge triggered single
clock input (CLK) controls all synchronous inputs
passing through the registers. The synchronous inputs
include all address, all data inputs, active low chip
enable (CE), two additional chip enables for easy depth
expansion (CE2,
synchronous clock enable (
(
Asynchronous inputs include the output enable (OE),
clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and
burst mode (MODE). Burst Mode can provide either
interleaved or linear operation, burst operation can be
initiated by synchronous address Advance/Load
(ADV/LD) pin in Low state. Subsequent burst address
can be internally generated by the chip and controlled by
the same input pin ADV/LD in High state.
,
BW3
), cycle start input (ADV/LD),
CE2
), byte write enables
CEN
,
) and read/write (R/W).
n Clock-controlled and registered address, data and
control signals
n Registered output for pipelined applications
n Three separate chip enables allow wide range of
options for CE control, address pipelining
n Internally self-timed write cycle
n Selectable BURST mode (Linear or Interleaved)
n SLEEP mode (ZZ pin) provided
n Available in 100 pin LQFP package
Write cycles are internally self-time and synchronous
with the rising edge of the clock input and when R/W is
Low. The feature simplified the write interface. Individual
Byte enables allow individual bytes to be written.
controls I/Oa pins;
controls I/Oc pins; and
types can only be defined when an address is loaded,
i.e., when ADV/LD is LOW. Parity/ECC bits are only
available on the X18/36 version.
The SRAM operates from a +3.3V power supply, and all
inputs and outputs are LVTTL-compatible. The device is
ideally suited for high bandwidth utilization systems.
controls I/Ob pins;
controls I/Od pins. Cycle
BW3
PRELIMINARY (December, 1999, Version 0.1) 1 AMIC Technology, Inc.
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc
Page 3
Pin Configuration
A67L8316/A67L8318/
A67L7332/A67L7336 Series
128K X 36/32
I/Oc0/NC
I/Oc1
I/Oc2
VCCQ
VSSQ
I/Oc3
I/Oc4
I/Oc5
I/Oc6
VSSQ
VCCQ
I/Oc7
I/Oc8
VCC
VCC
VCC
VSS
I/Od0
I/Od1
VCCQ
VSSQ
I/Od2
I/Od3
I/Ob8/NC
I/Od4
I/Od5
VSSQ
VCCQ
I/Od
6
I/Od7
I/Od
8
/NC
256K X 18/16
NC
NC
NC
VCCQ
VSSQ
NC
NC
I/Ob0
I/Ob1
VSSQ
VCCQ
I/Ob2
I/Ob3
VCC
VCC
VCC
VSS
I/Ob4
I/Ob5
VCCQ
VSSQ
I/Ob6
I/Ob7
NC
VSSQ
VCCQ
NC
NC
NC
LD
NC
A7
A6
A6
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A7
99
32
CE2
CECE
CE2NCNC
97
98
34
33
BW4
96
35
BW3
95
36
BW2BW2
94
37
BW1BW1
93
38
CE2 CE2
92
A67L8316E
A67L8318E
A67L7332E
A67L7336E
39
VCC
VCC
91
VSS
VSS
90
CLK
CLK
89
424041
R/W R/W
88
43
CENCEN
87
44
OEOE
86
45
ADV/
ADV/
85
46
NC
A9
A8
LD
NC
NC
A8
A9
81
82
83
84
47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
A17
NC
NC
VCCQ
VSSQ
NC
I/Oa8/NC
I/Oa7
I/Oa6
VSSQ
VCCQ
I/Oa5
I/Oa4
VSS
VCC
VCC
ZZ
I/Oa3
I/Oa2
VCCQ
VSSQ
I/Oa1
I/Oa0
NC
NC
VSSQ
VCCQ
NC
NC
NC
I/Ob8/NC
I/Ob7
I/Ob6
VCCQ
VSSQ
I/Ob5
I/Ob4
I/Ob3
I/Ob2
VSSQ
VCCQ
I/Ob1
I/Ob0
VSS
VCC
VCC
ZZ
I/Oa8
I/Oa7
VCCQ
VSSQ
I/Oa6
I/Oa5
I/Oa4
I/Oa3
VSSQ
VCCQ
I/Oa2
I/Oa1
I/Oa0/NC
MODE
MODE
A5
A1
A2
A3
A4
A5
NC
NC
VSS
A0
NC
NC
VSS
VCC
VCC
NC
NC
A10
NC
NC
A10
A11
A11
A12
A12
A13
A13
A14
A14
A15
A15
A16
A16
A0
A1
A2
A3
A4
PRELIMINARY (December, 1999, Version 0.1) 2 AMIC Technology, Inc.
Page 4
Block Diagram (128K X 32/36)
A67L8316/A67L8318/
A67L7332/A67L7336 Series
CEN
CLK
ZZ
MODE
ADV/LD
LOGIC
A0-A16
CLK
MODE
LOGIC
ADDRESS
REGISTERS
WRITE
ADDRESS
REGISTER
BURST
LOGIC
ADDRESS
COUNTER
CLR
REGISTER
WRITE
ADDRESS
CE2
CE2
8/9
BYTEa
WRITE
DRIVER
8/9
BYTEb
ADV/LD
R/W
BWE
BW1
BW2
BW3
BW4
CE
OE
WRITE
REGISTRY
&
CONTROL
LOGIC
CHIP
ENABLE
LOGIC
WRITE
DRIVER
8/9
BYTEc
WRITE
DRIVER
8/9
BYTEd
WRITE
DRIVER
PIPELINED
ENABLE
LOGIC
8/9
8/9
8/9
8/9
128KX8/X9X4
MEMORY
ARRAY
OUTPUT
ENABLE
LOGIC
SENSE
DATA-IN
REGISTERS
AMPS
OUTPUT
REGISTERS
&
OUTPUT
BUFFERS
DATA-IN
REGISTERS
I/O
s
PRELIMINARY (December, 1999, Version 0.1) 3 AMIC Technology, Inc.
Page 5
Block Diagram (256K X 16/18)
A67L8316/A67L8318/
A67L7332/A67L7336 Series
CEN
CLK
ZZ
MODE
ADV/LD
LOGIC
A0-A17
CLK
MODE
LOGIC
ADDRESS
REGISTERS
WRITE
ADDRESS
REGISTER
BURST
LOGIC
ADDRESS
COUNTER
CLR
ADDRESS
REGISTER
WRITE
8/9
CE2
CE2
BYTEa
8/9
WRITE
DRIVER
BYTEb
WRITE
DRIVER
PIPELINED
ENABLE
LOGIC
ADV/LD
R/W
BWE
BW1
BW2
CE
OE
WRITE
REGISTRY
&
CONTROL
LOGIC
CHIP
ENABLE
LOGIC
8/9
8/9
256KX8/X9X2
MEMORY
ARRAY
OUTPUT
ENABLE
LOGIC
SENSE
AMPS
DATA-IN
REGISTERS
OUTPUT
REGISTERS
&
OUTPUT
BUFFERS
DATA-IN
REGISTERS
I/O
S
PRELIMINARY (December, 1999, Version 0.1) 4 AMIC Technology, Inc.
Page 6
Pin Description
BW1
BW2
BW1
BW2
BW4)BW1
BW2
BW4
BW1
BW2
BW4
LD
Pin No. Symbol Description
LQFP (X16/X18) LQFP (X32/X36)
A67L8316/A67L8318/
A67L7332/A67L7336 Series
37
36
35,34,33,32,
100,99,82,81,
44,45,46,47,
48,49,50
80
93 (
94 (
)
)
89 89
98 98 CE Synchronous Chip Enable : This active low input is used to
37
36
35,34,33,32,
100,99,82,81,
44,45,46,47,
48,49,50
93 (
94 (
95 (
96 (
BW3
)
)
)
A0
A1
A2 - A16
A17
BW3
CLK
Synchronous Address Inputs : These inputs are registered
and must meet the setup and hold times around the rising
edge of CLK. Pins 83 and 84 are reserved as address bits
for higher-density 9Mb and 18Mb DBA SRAMs, respectively.
A0 and A1 are the two lest significant bits (LSB) of the
address field and set the internal burst counter if burst is
desired.
Synchronous Byte Write Enables : These active low inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK. BYTE WRITEs need to be asserted on
the same cycle as the address, BWs are associated with
addresses and apply to subsequent data.
pins;
Clock: This signal registers the address, data, chip enables,
byte write enables and burst control inputs on its rising
edge. All synchronous inputs must meet setup and hold
times around the clock are rising edge.
enable the device. This input is sampled only when a new
external address is loaded (ADV/LD LOW).
controls I/Ob pins;
controls I/Od pins.
controls I/Oc pins;
BW3
controls I/Oa
92 92 CE2 Synchronous Chip Enable : This active low input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used
for memory depth expansion.
97 97 CE2 Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used
for memory depth expansion.
86 86
85 85 ADV/
PRELIMINARY (December, 1999, Version 0.1) 5 AMIC Technology, Inc.
OE
Output Enable : This active low asynchronous input enables
the data I/O output drivers.
Synchronous Address Advance/Load : When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is loaded.
When HIGH, R/W is ignored. A LOW on this pin permits a
new address to be loaded at CLK rising edge.
Page 7
Pin Description (continued)
W
Pin No. Symbol Description
LQFP (X16/X18) LQFP (X32/X36)
87 87 CEN Synchronous Clock Enable : This active low input permits
64 64 ZZ Snooze Enable : This active high asynchronous input
A67L8316/A67L8318/
A67L7332/A67L7336 Series
CLK to propagate throughout the device. When HIGH, the
device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup
and hold times around the rising edge of CLK.
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active,
all other inputs are ignored.
88 88 R/
(a) 58, 59, 62, 63,
68, 69, 72, 73
(b) 8,9,12,13, 18,
19, 22,23
74
24
31 31 MODE Mode : This input selects the burst sequence. A LOW on
(a) 52, 53, 56, 57,
58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9,
12, 13,
(d) 18, 19, 22, 23,
24, 25, 28, 29
51
80
1
30
I/Oa
I/Ob
I/Oc
I/Od
NC/I/Oa
NC/I/Ob
NC/I/Oc
NC/I/Od
Read/Write : This active input determines the cycle type
when ADV/LD is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be
converted into WRITEs (and vice versa) other than by
loading a new address. A LOW on this pin permits BYTE
WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins;
Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must
meet setup and hold times around CLK rising edge.
No Connect/Data Bits : On the X16/32 version, these pins
are no connect (NC) and can be left floating or connected to
GND to minimize thermal impedance. On the X18/36
version, these bits are I/Os.
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating.
1, 2, 3, 6, 7, 25,
28, 29, 30, 38, 39,
42, 43, 51, 52, 53,
56, 57, 75, 78, 79,
83, 84, 95, 96
PRELIMINARY (December, 1999, Version 0.1) 6 AMIC Technology, Inc.
38,39,42,43
83,84
NC No Connect : These pins can be left floating or connected to
GND to minimize thermal impedance.
Page 8
A67L8316/A67L8318/
A67L7332/A67L7336 Series
Pin Description (continued)
Pin No. Symbol Description
LQFP (X16/X18) LQFP (X32/X36)
15, 41, 65, 91 15, 41, 65, 91 VCC Power Supply : See DC Electrical Characteristics and
Operating Conditions for range.
14, 16, 66 14, 16, 66 VCC These pins do not have to be connected directly to VCC as
long as the input voltage is ≥ VIH. This input is not
connected to VCC bus internally.
4, 11, 20, 27,
54, 61, 70, 77
17, 40, 90 17, 40, 90 VSS Ground : GND.
5,10,21,26,
55,60,71,76
4, 11, 20, 27,
54, 61, 70, 77
5,10,21,26,
55,60,71,76
VCCQ Isolated Output Buffer Supply : See DC Electrical
Characteristics and Operating Conditions for range.
VSSQ Isolated Output Buffer Ground
PRELIMINARY (December, 1999, Version 0.1) 7 AMIC Technology, Inc.
Page 9
Truth Table (Notes 5 - 7)
CE
CE2
W
BWxOECEN
BWx
BW1,BW2
BW4
BWx
BW1
BW2
BW4
A67L8316/A67L8318/
A67L7332/A67L7336 Series
Operation
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Continue Deselect
Cycle
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/Dummy READ
(Begin Burst)
Dummy READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE Abort
(Begin Burst)
WRITE Abort
(Continue Burst)
IGNORE Clock Edge
(Stall)
SLEEP Mode None X X X H X X X X X X High-Z
Notes:
1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is
executed first.
2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE
Abort means a WRITE command is given, but no operation is performed.
3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off
the output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not
meet their requirements.
4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock
Edge cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
(
6.
Byte “c” (I/Oc pins);
7. The address counter is incremented for all Continue Burst cycles.
,
BW3
enables WRITEs to Byte “a” (I/Oa pins);
Address
Used
None H X X L L X X X L L→H High-Z
None X H X L L X X X L L→H High-Z
None X X L L L X X X L L→H High-Z
None X X X L H X X X L L→H High-Z 1
External L L H L L H X L L L→H Q
Next X X X L H X X L L L→H Q 1,7
External L L H L L H X H L L→H High-Z 2
Next X X X L H X X H L L→H High-Z 1,2,7
External L L H L L L L X L L→H D 3
Next X X X L H X L X L L→H D 1,3,7
None L L H L L L H X L L→H High-Z 2,3
Next X X X L H X H X L L→H High-Z 1,2,3,7
Current X X X L X X X X H L→H - 4
and
) are HIGH.
enables WRITEs to Byte “d” (I/Od pins).
CE2 ZZ ADV/LDR/
= H means all byte write signals
= L means one or more byte write signals are LOW.
enables WRITEs to Byte “b” (I/Ob pins);
BW3
CLK I/O Notes
enables WRITEs to
PRELIMINARY (December, 1999, Version 0.1) 8 AMIC Technology, Inc.
Page 10
A67L8316/A67L8318/
W
BW1
BW2
W
BW1
BW2
BW4
A67L7332/A67L7336 Series
Partial Truth Table for READ/WRITE Commands (X16/X18)
Operation R/
READ H X X
WRITE Byte “a” L L H
WRITE Byte “b” L H L
WRITE all bytes L L L
WRITE Abort/NOP L H H
Note : Using and BYTE WRITE(s), any one or more bytes may be written.
Partial Truth Table for READ/WRITE Commands (X32/X36)
Operation R/
READ H X X X X
WRITE Byte “a” L L H H H
WRITE Byte “b” L H L H H
WRITE Byte “c” L H H L H
WRITE Byte “d” L H H H L
WRITE all bytes L L L L L
WRITE Abort/NOP L H H H H
Note : Using R/W and BYTE WRITE(s), any one or more bytes may be written.
BW3
Linear Burst Address Table (MODE = LOW)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00
PRELIMINARY (December, 1999, Version 0.1) 9 AMIC Technology, Inc.
Page 11
A67L8316/A67L8318/
A67L7332/A67L7336 Series
Absolute Maximum Ratings*
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC
+0.5V
Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C
Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C
Storage Temperature (Tstg) . . . . . . . . . . -55°C to 125°C
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics and Operating Conditions
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = +3.3V± 5% unless otherwise noted)
Symbol Parameter Conditions Min. Max. Unit Note
VIH Input High Voltage 2.0 VCC+0.3 V 1,2
VIL Input Low Voltage -0.3 0.8 V 1,2
ILI Input Leakage Current 0V ≤ VIH ≤ VCC -1.0 1.0 µA 3
ILO Output Leakage Current Output(s) disabled,
0V ≤ VIN≤ VCC
VOH Output High Voltage IOH = -4.0mA 2.4 V 1,4
-1.0 1.0 µA
VOL Output Low Voltage IOL = 8.0mA 0.4 V 1,4
VCC Supply Voltage 3.135 3.465 V 1
VCCQ Isolated Output Buffer Supply 3.135 VCC V 1,5
Capacitance
Symbol Parameter Conditions Typ. Max. Unit Note
CI Control Input Capacitance 3 4 pF 6
CO Input/Output Capacitance (I/O) 4 5 pF 6
CA Address Capacitance
Note : 1. All voltages referenced to VSS (GND).
2. Overshoot : VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA
Undershoot : VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA
Power-up : VIH ≤ +3.456V and VCC ≤ 3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up and exhibits an input leakage current of ±10µA.
4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values.
AC I/O curves are available upon request.
5. VCC and VCCQ can be externally wired together to the same power supply.
6. This parameter is sampled.
TA = 25°C; f = 1MHz
VCC = 3.3V
3 3.5 pF 6
PRELIMINARY (December, 1999, Version 0.1) 10 AMIC Technology, Inc.
Page 12
ICC Operating Condition and Maximum Limits
Max.
Symbol Parameter
ICC Power Supply Current : Operating 300 250 230 mA
ICC1 Power Supply Current : Idle 12 10 8 mA
ISB2
CMOS Standby
-4.5 -5 -6
10 10 10 mA
A67L8316/A67L8318/
A67L7332/A67L7336 Series
Unit Conditions
Device selected; All inputs ≤ VIL
or ≥ VIH; Cycle time ≥ tKC (MIN);
VCC = MAX; Outputs open
Device selected; VCC = MAX;
≥ VIH;
CEN
All inputs ≤ VSS+0.2 or ≥VCC-0.2;
Cycle time ≥ tKC (MIN)
Device deselected; VCC = MAX;
All inputs ≤VSS+0.2 or ≥ VCC-0.2;
All inputs static; CLK frequency=0
ISB3 TTL Standby 25 25 25
ISB4 Clock Running 65 60 60
ISB2Z SLEEP Mode 10 10 10 mA ZZ ≥ VIH
mA
mA
Device deselected; VCC = MAX;
All inputs ≤ VIL; or ≥ VIH;
All inputs static; CLK frequency=0
Device deselected; VCC = MAX;
All inputs ≤ VSS+0.2 or ≥ VCC-0.2;
Cycle time ≥ tKC (MIN)
PRELIMINARY (December, 1999, Version 0.1) 11 AMIC Technology, Inc.
Page 13
A67L8316/A67L8318/
A67L7332/A67L7336 Series
AC Characteristics (Note 4)
(0°C ≤ TA ≤ 70°C, VCC = 3.3V± 5%)
-4.5 -5 -6
Symbol Parameter
Clock
tKHKH Clock cycle time 8.5 - 10 - 12 - ns
tKF Clock frequency - 117 - 100 - 83 MHz
tKHKL Clock HIGH time 3.4 - 3.5 - 4.0 - ns
tKLKH Clock LOW time 3.4 - 3.5 - 4.0 - ns
Output Times
tKHQV Clock to output valid - 4.5 - 5.0 - 6.0 ns
tKHQX Clock to output invalid 1.5 - 1.5 - 1.5 - ns
tKHQX1 Clock to output in Low-Z 1.5 - 1.5 - 1.5 - ns 1,2,3
tKHQZ Clock to output in High-Z 1.5 4.5 1.5 5.0 1.5 6.0 ns 1,2,3
Min. Max. Min. Max. Min. Max.
Unit Note
tGLQV
tGLQX
tGHQZ
Setup Times
tAVKH Address 2.0 - 2.2 - 2.5 - ns 5
tEVKH
tCVKH Control signals 2.0 - 2.2 - 2.5 - ns 5
tDVKH Data-in 1.7 - 2.0 - 2.5 - ns 5
Hold Times
tKHAX Address 0.5 - 0.5 - 1.0 - ns 5
tKHEX
tKHCX Control signals 0.5 - 0.5 - 1.0 - ns 5
tKHDX Data-in 0.5 - 0.5 - 1.0 - ns 5
Notes: 1. This parameter is sampled.
OE to output valid
OE to output in Low-Z
OE to output in High-Z
Clock enable (
Clock enable (
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured ±200mV from steady state voltage.
4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of
CLK when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK (when ADV/LD is LOW) to remain enabled.
CEN
CEN
)
)
- 4.5 - 5.0 - 6.0 ns 4
0 - 0 - 0 - ns 1,2,3
- 4.5 - 5.0 - 6.0 ns 1,2,3
2.0 - 2.2 - 2.5 - ns 5
0.5 - 0.5 - 1.0 - ns 5
PRELIMINARY (December, 1999, Version 0.1) 12 AMIC Technology, Inc.
Page 14
AC Test Conditions
Input Pulse Levels GND to 3V
Input Rise and Fall Times 1.5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figures 1 and 2
Q
ZO=50
Ω
50
Ω
A67L8316/A67L8318/
A67L7332/A67L7336 Series
+3.3V
317
Ω
Q
351
Ω
5pF
VT=1.5V
Figure 1
Output Load Equivalent
Figure 2
Output Load Equivalent
PRELIMINARY (December, 1999, Version 0.1) 13 AMIC Technology, Inc.
Page 15
SLEEP Mode
A67L8316/A67L8318/
A67L7332/A67L7336 Series
SLEEP Mode is a low current “Power-down” mode in
which the device is deselected and current is reduced to
ISB2Z. This duration of SLEEP Mode is dictated by the
length of time the ZZ is in a HIGH state. After entering
SLEEP Mode, all inputs except ZZ become disabled and
all outputs go to High-Z.
The ZZ pin is asynchronous, active high input that causes
the device to enter SLEEP Mode. When the ZZ pin
becomes logic HIGH, ISB2Z is guaranteed after the time
tZZI is met, Any operation pending when entering SLEEP
Mode is not guaranteed to successfully complete.
Therefore, SLEEP Mode (READ or WRITE) must not be
initiated until valid pending operations are completed.
Similarly, when exiting SLEEP Mode during tRZZ, only a
DESELECT or READ cycle should be given while the
SRAM is transitioning out of SLEEP Mode.
SLEEP Mode Electrical Characteristics
(VCC, VCCQ = +3.3V±5%)
Symbol Parameter Conditions Min. Max. Unit Note
ISB2Z Current during SLEEP Mode ZZ ≥ VIH - 10 mA
tZZ ZZ active to input ignored 0 2(tKHKH) ns 1
tRZZ ZZ inactive to input sampled 0 2(tKHKH) ns 1
tZZI ZZ active to snooze current - 2(tKHKH) ns 1
tRZZI ZZ inactive to exit snooze current 0 ns 1
Note : 1. This parameter is sampled.
SLEEP Mode Waveform
CLK
ZZ
I
SUPPLY
ALL INPUTS
(except ZZ)
Output
(Q)
t
ZZ
t
ZZI
I
ISB2Z
RZZI
t
DESELECT or READ Only
t
RZZ
High-Z
: Don't Care
PRELIMINARY (December, 1999, Version 0.1) 14 AMIC Technology, Inc.
Page 16
READ/WRITE Timing
A67L8316/A67L8318/
A67L7332/A67L7336 Series
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
I/O
OE
1 2 3 4 5
tKHCXtCVKH
A1
tKHAXtAVKH
tKHKL
tKHKH
D(A1)
tKLKHtEVKH tKHEX
A3A2
tKHDXtDVKH
D(A2) D(A2+1) Q(A6)D(A5)
6 7 8 9 10
A4 A5
tKHQV
tKHQX1
tKHQX
Q(A4)Q(A3)
tGHQZ
tGLQV
A6 A7
tKHQZ
Q(A4+1)
tKHQX
tGLQX
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
Note : 1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.
3. CE represents three signals. When CE = 0, it represents CE = 0,
4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The
most recent data may be from the input data register.
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
= 0, CE2 = 1.
CE2
READ
Q(A6)
: Don't Care : Undefined
WRITE
D(A7)
DESELECT
PRELIMINARY (December, 1999, Version 0.1) 15 AMIC Technology, Inc.
Page 17
NOP, STALL and Deselect Cycles
A67L8316/A67L8318/
A67L7332/A67L7336 Series
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
I/O
COMMAND
1 2 3 4 5
A3A2A1 A4 A5
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
6 7 8 9 10
t
KHQZ
t
KHQX
STALL NOP
READ
Q(A5)
: Don't Care : Undefined
DESELECT
Q(A5)D(A4)Q(A3)Q(A2)D(A1)
CONTINUE
DESELECT
Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates
being used to create a “pause.” A WRITE
CEN
is not performed during this cycle.
2. For this waveform, ZZ and OE are tied LOW.
3. CE represents three signals. When CE = 0, it represents CE = 0,
= 0, CE2 = 1.
2CE
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The
most recent data may be from the input data register.
PRELIMINARY (December, 1999, Version 0.1) 16 AMIC Technology, Inc.
Page 18
Ordering Information
Part No. Configure Cycle Time / Access Time Package
A67L8316E-4.5 8.5ns / 4.5ns
A67L8316/A67L8318/
A67L7332/A67L7336 Series
A67L8316E-5 10ns / 5ns
A67L8316E-6
A67L8318E-4.5 8.5ns / 4.5ns
A67L8318E-5 10ns / 5ns
A67L8318E-6
A67L7332E-4.5 8.5ns / 4.5ns
A67L7332E-5 10ns / 5ns
A67L7332E-6
A67L7336E-4.5 8.5ns / 4.5ns
A67L7336E-5 10ns / 5ns
A67L7336E-6
256K X 16
12ns / 6ns
256K X 18
12ns / 6ns
128K X 32
12ns / 6ns
128K X 36
12ns / 6ns
100L LQFP
100L LQFP
100L LQFP
100L LQFP
PRELIMINARY (December, 1999, Version 0.1) 17 AMIC Technology, Inc.
Page 19
A67L8316/A67L8318/
A67L7332/A67L7336 Series
Package Information
LQFP 100L Outline Dimensions unit: inches/mm
HE
E
e
51
50
31
b
Dimensions in inches Dimensions in mm
HD
θ
80
81
D
100
1 30
Symbol
Min. Nom. Max. Min. Nom. Max.
A1 0.002 - - 0.05 - A2 0.053 0.055 0.057 1.35 1.40 1.45
b 0.011 0.013 0.015 0.27 0.32 0.37
c 0.005 - 0.008 0.12 - 0.20
HE 0.860 0.866 0.872 21.85 22.00 22.15
E 0.783 0.787 0.791 19.90 20.00 20.10
HD 0.624 0.630 0.636 15.85 16.00 16.15
D 0.547 0.551 0.555 13.90 14.00 14.10
e 0.026 BSC 0.65 BSC
L 0.018 0.024 0.030 0.45 0.60 0.75
L1 0.039 REF 1.00 REF
y - - 0.004 - - 0.1
θ 0° 3.5° 7° 0° 3.5° 7°
A1A2
y
D
L1
L
c
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY (December, 1999, Version 0.1) 18 AMIC Technology, Inc.
Loading...