Page 1
6595
Data Sheet
26185.120
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
POWER
GROUND
SUPPLY
SERIAL
DATA IN
REGISTER
OUTPUT
ENABLE
POWER
GROUND
Note that the A6595KA (DIP) and the A6595KLW (SOIC)
are electrically identical and share a common terminal
number assignment.
LOGIC
OUT
OUT
OUT
OUT
CLEAR
1
2
V
DD
3
4
0
5
1
6
2
7
3
8
9
10
CLR
OE
LATCHES
REGISTER
LATCHES
REGISTER
ST
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO............................... 50 V
Output Drain Current,
Continuous, IO.......................... 250 mA*
Peak, IOM................................. 750 mA*†
Peak, IOM....................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS................................................. 75 mJ
Logic Supply Voltage, VDD.................. 7.0 V
Input Voltage Range,
VI................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD........................................... See Graph
Operating Temperature Range,
TA................................. -40°C to +125°C
Storage Temperature Range,
TS................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
20
19
18
17
16
15
14
13
12
11
POWER
GROUND
LOGIC
GROUND
SERIAL
DATA OUT
OUT
7
OUT
6
OUT
5
OUT
4
CLOCKCLK
STROBE
POWER
GROUND
Dwg. PP-029-13
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
The A6595KA and A6595KLW combine an 8-bit CMOS shift
register and accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power
loads.
The serial-data input, CMOS shift register and latches allow direct
interfacing with microprocessor-based systems. Serial-data input rates
are over 5 MHz. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. Similar devices with reduced
r
are available as the A6A595.
DS(on)
The A6595 DMOS open-drain outputs are capable of sinking up to
750 mA. All of the output drivers are disabled (the DMOS sink drivers
turned off) by the OUTPUT ENABLE input high.
The A6595KA is furnished in a 20-pin dual in-line plastic package.
The A6595KLW is furnished in a wide-body, small-outline plastic
package (SOIC) with gull-wing leads. Copper lead frames, reduced
supply current requirements, and low on-state resistance allow both
devices to sink 150 mA from all outputs continuously, to ambient
temperatures over 85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 250 mA Output Current (all outputs simultaneously)
■ 1.3 Ω Typical
■ Low Power Consumption
■ Replacements for TPIC6595N and TPIC6595DW
Always order by complete part number:
Part Number Package R
A6595KA 20-pin DIP 55°C/W 25°C/W
A6595KLW 20-lead SOIC 70°C/W 17°C/W
r
DS(on)
θJA
R
θJC
Page 2
6595
g
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
2.5
2.0
SUFFIX 'A', R = 55
1.5
1.0
SUFFIX 'LW
θ
J
A
', R = 70
θ
J
A
°C/W
°C/W
0.5
0
25
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
50 75 100 125 150
AMBIENT TEMPERATURE IN °C
Dwg. GS-004A
FUNCTIONAL BLOCK DIAGRAM
REGISTER
CLEAR
(ACTIVE LOW)
CLOCK
LOGIC SYMBOL
9
12
8
13
3
G3
R
1D
C2
SRG8
C1
2
2
V
DD
Dw
4
5
6
7
14
15
16
17
18
. FP-043
LOGIC
SUPPLY
SERIAL
DATA IN
STROBE
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
SERIAL
DATA OUT
OUTPUT
ENABLE
(ACTIVE LOW)
LOGIC
GROUND
POWER
GROUND
OUT
0
OUT
N
POWER
GROUND
Dwg. FP-013-5
Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
Page 3
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
V
DD
IN
Dwg. EP-010-15
LOGIC INPUTS
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH............................ ≥ 0.85V
Low-level input voltage, VIL................................. ≤0.15V
DD
DD
OUT
Dwg. EP-063-3
DMOS POWER DRIVER OUTPUT
V
DD
OUT
Dwg. EP-063-2
SERIAL DATA OUT
TRUTH TABLE
Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Output
Input Input I0I1I
HHR
LLR
XR
0R1
0R1
0R1R2
XXX … XX X — R0R1R2…R6R
P0P1P2…P6P
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
... I6I7Output Strobe I0I1I2... I6I7Enable I0I1I2…I6I
2
…R5R
…R5R
…R6R
R
6
6
R
6
6
R
7
7
7
P
7
7
P0P1P2…P6P
LP0P1P2…P6P
7
XXX … XX H HHH … HH
7
7
Page 4
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Breakdown V
Voltage
(BR)DSXIO
= 1 mA 50 — — V
Off-State Output I
Current
Static Drain-Source r
On-State Resistance
Nominal Output I
Current
Logic Input Current I
Logic Input Hysteresis V
SERIAL-DATA V
Output Voltage
Prop. Delay Time t
DSX
DS(on)
ON
IH
I
IL
I(hys)
OH
V
OL
PLH
t
PHL
VO = 40 V — 0.05 1.0 µA
V
= 40 V, TA = 125°C — 0.15 5.0 µA
O
IO = 250 mA, VDD = 4.5 V — 1.3 2.0 Ω
IO = 250 mA, VDD = 4.5 V, TA = 125°C— 2.0 3.2 Ω
IO = 500 mA, VDD = 4.5 V (see note) — 1.3 2.0 Ω
V
= 0.5 V, TA = 85°C — 250 — mA
DS(on)
VI = VDD = 5.5 V — — 1.0 µA
VI = 0, VDD = 5.5 V — — -1.0 µA
—1.3— V
IOH = -20 µA, VDD = 4.5 V 4.4 4.49 — V
IOH = -4 mA, VDD = 4.5 V 4.1 4.3 — V
IOL = 20 µA, VDD = 4.5 V — 0.002 0.1 V
IOL = 4 mA, VDD = 4.5 V — 0.2 0.4 V
IO = 250 mA, CL = 30 pF — 650 — ns
IO = 250 mA, CL = 30 pF — 150 — ns
Output Rise Time t
Output Fall Time t
Supply Current I
DD(OFF)
I
DD(ON)
I
DD(fclk)
r
f
IO = 250 mA, CL = 30 pF — 7500 — ns
IO = 250 mA, CL = 30 pF — 425 — ns
All inputs low — 15 100 µA
VDD = 5.5 V, Outputs on — 150 300 µA
f
= 5 MHz, CL = 30 pF, Outputs off — 0.6 5.0 mA
clk
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Page 5
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
6595
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
STROBE
OUTPUT
ENABLE
OUT
OUTPUT
ENABLE
OUT
50%
A B
DATA
N
N
50%
t
p
50%
D E
50%
LOW = ALL OUTPUTS ENABLED
HIGH = ALL OUTPUTS DISABLED
50%
t
PHL
DATA
t
p
t
PLH
HIGH = OUTPUT OFF
50%
LOW = OUTPUT ON
t
f
90%
DATA
DATA
Dwg. WP-029-2
t
r
10%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t
.......................................... 10 ns
su(D)
B. Data Active Time After Clock Pulse
(Data Hold Time), t
C. Clock Pulse Width, t
.............................................. 10 ns
h(D)
............................................. 20 ns
w(CLK)
D. Time Between Clock Activation
and Strobe, t
E. Strobe Pulse Width, t
F. Output Enable Pulse Width, t
....................................................... 50 ns
su(ST)
.............................................. 50 ns
w(ST)
................................ 4.5 µs
w(OE)
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
www.allegromicro.com
Dwg. WP-030-2
Serial data present at the input is transferred to the shift
register on the rising edge of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information
towards the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
Page 6
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
TEST CIRCUITS
INPUT
I
O
V
O
t
av
IAS = 1.0 A
V
(BR)DSX
V
O(ON)
EAS = IAS x V
(BR)DSX
DUT
x tAV/2
+15 V
0.11 Ω
100 mH
OUT
Dwg. EP-066-1
Single-Pulse Avalanche Energy Test Circuit
and Waveforms
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Page 7
TERMINAL DESCRIPTIONS
Terminal No. Terminal Name Function
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
1 POWER GROUND Reference terminal for output voltage measurements (OUT
2 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).
3 SERIAL DATA IN Serial-data input to the shift-register.
4-7 OUT
0-3
Current-sinking, open-drain DMOS output terminals.
8 CLEAR When (active) low, the registers are cleared (set low).
9 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
10 POWER GROUND Reference terminal for output voltage measurements (OUT
11 POWER GROUND Reference terminal for output voltage measurements (OUT
12 STROBE Data strobe input terminal; shift register data is latched on rising edge.
13 CLOCK Clock input terminal for data shift on rising edge.
14-17 OUT
4-7
Current-sinking, open-drain DMOS output terminals.
18 SERIAL DATA OUT CMOS serial-data output to the following shift register.
19 LOGIC GROUND Reference terminal for input voltage measurements.
20 POWER GROUND Reference terminal for output voltage measurements (OUT
NOTE — Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
0-3
0-3
0-7
4-7
).
).
).
).
www.allegromicro.com
Page 8
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
20
0.280
0.240
A6595KA
Dimensions in Inches
(controlling dimensions)
11
0.014
0.008
0.300
BSC
0.430
MAX
0.210
MAX
7.11
6.10
0.015
MIN
1
0.070
0.045
0.022
0.014
1.060
0.980
0.100
BSC
10
0.005
MIN
0.150
0.115
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
0.355
20
1
1.77
1.15
26.92
24.89
2.54
BSC
11
10
0.13
MIN
0.204
7.62
BSC
10.92
MAX
5.33
MAX
0.39
MIN
0.558
0.356
3.81
2.93
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Dwg. MA-001-20 mm
Page 9
A6595KLW
Dimensions in Inches
(for reference only)
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
20 11
0.2992
0.2914
0.020
1 2
0.013
0.0926
0.1043
0.0040
3
MIN.
20
0.050
0.5118
0.4961
BSC
Dimensions in Millimeters
(controlling dimensions)
11
0.419
0.394
0° TO 8°
0.0125
0.0091
0.050
0.016
Dwg. MA-008-20 in
0.32
0.23
7.60
7.40
0.51
0.33
2.65
2.35
1
0.10
2
MIN.
3
13.00
12.60
1.27
BSC
10.65
10.00
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
0° TO 8°
Dwg. MA-008-20 mm
1.27
0.40
Page 10
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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