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A64S0616
Preliminary 1M X 16 Bit Low Voltage Super RAMTM
Document Title
1M X 16 Bit Low Voltage Super RAMTM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue November 30, 2001 Preliminary
0.1 Add tASC, tAHC, tCEH, tWEH July 31, 2002
PRELIMINARY (July, 2002, Version 0.1) AMIC Technology, Inc.
Page 2
A64S0616
HB
A64S0616G
Preliminary 1M X 16 Bit Low Voltage Super RAMTM
Features
n Operating voltage: 2.7V to 3.1V
n Access times: 70 ns (max.)
n Current:
A64S0616 series: Operating: 35mA (max.)
Power Down Standby: 10µA (max.)
n Fully SRAM compatible operation
n Full static operation, no clock or refreshing required
General Description
The A64S0616 is a low operating current 16,777,216-bit
Super RAM organized as 1,048,576 words by 16 bits and
operates on low power supply voltage from 2.7V to 3.1V.
It is built using AMIC’s high performance CMOS DRAM
process.
Using hidden refresh technique, the A64S0616 provides
a 100% compatible asynchronous interface.
Pin Configuration
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Industrial operating temperature range: -25°C to +85°C
for -I
n Available in 48-ball Mini BGA (6X8) package.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output enable
input are included for easy interfacing.
This A64S0616 is suited for low power application such as
mobile phone and PDA or other battery-operated handheld
device.
n Mini BGA (6X8) Top View
1 2 3 4 5 6
A
B I/O8
C I/O9 I/O10 A5 A6 I/O1 I/O2
D VSS I/O11 A17 A7 I/O3 VCC
E VCC I/O12 GND A16 I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 A19 A12 A13
H A18 A8 A9 A10 A11 NC
LB OE
A0 A1 A2 CE2
A3 A4
CE1
WE
I/O0
I/O7
PRELIMINARY (July, 2002, Version 0.1) 1 AMIC Technology, Inc.
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A64S0616
Block Diagram
A0
A18
A19
I/O
0
7
I/O
CE1
CE2
LB
HB
OE
WE
CONTROL
Pin Description
CIRCUIT
DECODER
INPUT
DATA
CIRCUIT
16,777,216
MEMORY ARRAY
COLUMN I/O
VCC
VSS
GND
INPUT
DATA
CIRCUIT
I/O
I/O
8
15
Symbol Description
A0 - A19 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
I/O0 - I/O15 Data Input/Outputs
WE Write Enable Input
LB Byte Enable Input (I/O0 to I/O7)
HB Byte Enable Input (I/O8 to I/O15)
OE Output Enable Input
VCC Power
VSS Ground
GND Ground
NC No Connection
PRELIMINARY (July, 2002, Version 0.1) 2 AMIC Technology, Inc.
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A64S0616
Recommended DC Operating Conditions
(TA = 0°C to + 70°C or -25°C to 85°C)
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.1 V
VSS Ground 0 0 V
GND Ground 0 0 V
VIH Input High Voltage 2.4 VCC + 0.3 V
VIL Input Low Voltage -0.3 +0.6 V
CL Output Load - 30 pF
TTL Output Load - 1 -
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.1V, GND = 0V)
Symbol Parameter
ILI
ILO
ICC1 - 35 - 30 mA
ICC2
Input Leakage
Current
Output Leakage
Current
Dynamic Operating
Current
-70 -85
Min. Max. Min. Max.
- 1 - 1
- 1 - 1
- 5 - 5 mA
Unit Conditions
VIN = GND to VCC
µA
CE1 = VIH or CE2 = VIL or
µA
OE = VIH or WE = VIL
VI/O = GND to VCC
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V,
f = 1MHz, II/O = 0mA
PRELIMINARY (July, 2002, Version 0.1) 3 AMIC Technology, Inc.
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A64S0616
CE1
OE WE LB HB
DC Electrical Characteristics (continued)
Symbol Parameter -70 -85 Unit Conditions
Min. Max. Min. Max.
ISB1
ISB2
VOL Output Low Voltage - 0.4 - 0.4 V IOL = 2.1mA
VOH Output High Voltage 2.4 - 2.4 - V IOH = -1.0mA
Standby Power
Supply Current
Power Down Mode
Standby Current
- 100 - 100
- 10 - 10
µA
µA CE2 ≤ 0.2V
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ 0V
Truth Table
CE2
H H X X X X Not selected Not selected ISB1, ISB
X H X X H H Not selected Not selected ISB1, ISB
X L X X X X Not selected Not selected ISB2
L L Read Read ICC1, ICC2
L H L H L H Read High - Z ICC1, ICC2
H L High - Z Read ICC1, ICC2
L L Write Write ICC1, ICC2
I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current
L H X L L H Write Not Write/Hi - Z ICC1, ICC2
H L Not Write/Hi - Z Write ICC1, ICC2
L H H H X X
Note: X = H or L
High - Z High - Z ICC1, ICC2
High - Z High - Z ICC1, ICC2
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 10 pF VIN = 0V
CI/O* Input/Output Capacitance - 10 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY (July, 2002, Version 0.1) 4 AMIC Technology, Inc.
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A64S0616
Initialization
The A64S0616 is initialized in the power-on sequence according to the following.
1. To stabilize internal circuits, after turning on the power, a 350µs or longer wait time must precede any signal toggling.
2. After the wait time, it can be normal operation.
Power on Chart
VCC(min)
VCC
CE1
CE2
50ns
(min)
350us
Wait Time Normal Operation
Notes: 1. Following power application, make CE2 and CE1 high level during the wait time interval.
2. After power on sequence, the normal operating CE2 must keep at high.
Power on / Depower down State Machine
CE1=VIH,
CE2=V
IH
CE1=VIH,
CE2=V
IH
Standby
Mode
Power on
Initial State
CE1=VIL,
CE2=V
CE1=V
CE2=VIL,
Active
IH
IH
CE1=VIH,
CE2=V
IH
Wait 350us
CE1=VIL,
CE2=V
IH
CE1=V
CE2=VIL,
CE1=V
CE2=VIH,
IH
Power Down
Mode
IH
Standby Mode Characteristics
Standby Mode Memory Cell Data Hold
Standby Valid 100 (ISB1)
Power down Invalid 10 (ISB2)
Standby Supply Current (µA)
PRELIMINARY (July, 2002, Version 0.1) 5 AMIC Technology, Inc.
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A64S0616
Avoid Timing
Following figures are show you an abnormal timing which
is not supported on Super RAM and their solution.
At normal operation, if your system have a timing which
sustain invalid states over 10µs at normal mode like
Figure 1. There are some guide line for proper operation
of Super RAM.
CE1
Over 10us
When your system have multiple invalid address signal
shorter than tRC on the timing which showed in Figure 1,
Super RAM need toggle the CE1 to “high” about “tRC”
(Figure 2).
Address
Address
CE1
Less than t
RC
Figure 1
toggle CE1 to high every 10us
10us
Figure 2
70ns
PRELIMINARY (July, 2002, Version 0.1) 6 AMIC Technology, Inc.
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A64S0616
AC Characteristics (TA = 0°C to +70°C or -25°C to 85°C, VCC = 2.7V to 3.1V)
Symbol Parameter -70 -85 Unit
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 70 - 85 - ns
tSKEW Address Skew - 10 - 10 ns
tAA Address Access Time - 70 - 85 ns
tACE Chip Enable Access Time - 70 - 85 ns
tBE Byte Enable Access Time - 70 - 85 ns
tOE Output Enable to Output Valid - 35 - 45 ns
tCLZ Chip Enable to Output in Low Z 10 - 10 - ns
tBLZ Byte Enable to Output in Low Z 5 - 5 - ns
tOLZ Output Enable to Output in Low Z 5 - 5 - ns
tCHZ Chip Disable to Output in High Z 0 25 0 35 ns
tBHZ Byte Disable to Output in High Z 0 25 0 35 ns
tOHZ Output Disable to Output in High Z 0 25 0 35 ns
tOH Output Hold from Address Change 10 - 10 - ns
tASC
tAHC
tCEH
Write Cycle
tWC Write Cycle Time 70 - 85 - ns
tSKEW Address Skew - 10 - 10 ns
tCW Chip Enable to End of Write 60 - 70 - ns
tBW Byte Enable to End of Write 60 - 70 - ns
tAS Address Setup Time 0 - 0 - ns
tAW Address Valid to End of Write 60 - 70 - ns
tWP Write Pulse Width 50 - 55 - ns
tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z - 20 - 20 ns
tDW Data to Write Time Overlap 30 - 35 - ns
tDH Data Hold from Write Time 0 - 0 - ns
tOW Output Active from End of Write 5 - 5 - ns
tASC
tAHC
tCEH
tWEH
Address Setup to CE1 Low
Address Hold Time from CE1 High
CE1 High Pulse With
Address Setup to CE1 Low
Address Hold Time from CE1 High
CE1 High Pulse With
WE High Pulse With
0 - 0 - ns
0 - 0 - ns
10 - 10 - ns
0 - 0 - ns
0 - 0 - ns
10 - 10 - ns
10 - 10 - ns
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY (July, 2002, Version 0.1) 7 AMIC Technology, Inc.
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A64S0616
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4, 6)
tSKEW tRC tSKEW tRC
tAA tOH tAA tOH
tASC
CE1
PRELIMINARY (July, 2002, Version 0.1) 8 AMIC Technology, Inc.
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A64S0616
HB
LB
HB
LB
Read Cycle 2-1
Address
CE1
,
OE
DOUT
Read Cycle 2-2
(1, 3, 6)
SKEW
t
(1, 3, 6)
t
SKEW
t
ASC
t
t
t
AHC
OHZ
t
BHZ
t
5
CHZ
SKEW
5
5
t
RC
t
AHC
t
AA
t
ACE
5
t
CLZ
t
BE
5
t
BLZ
t
OE
5
t
OLZ
t
OHZ
t
CHZ
t
BHZ
5
CEH
t
5
5
t
ASC
t
CLZ
t
RC
t
AA
BE
t
t
ACE
5
t
BE
5
t
BLZ
t
OE
5
t
OLZ
t
t
RC
SKEW
t
RC
t
SKEW
Address
t
ASC
t
AA
t
AA
CE1
t
ACE
5
t
CLZ
t
,
BE
5
t
BLZ
5
t
BHZ
t
BE
5
t
BLZ
OE
t
t
OLZ
OE
5
t
OHZ
5
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled
= VIL, HB = VIL and, or LB = VIL.
1CE
3. Address valid prior to or coincident with CE1 and (HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high for Read Cycle.
t
OLZ
t
OE
5
t
t
AHC
OHZ
t
BHZ
t
5
CHZ
5
5
PRELIMINARY (July, 2002, Version 0.1) 9 AMIC Technology, Inc.
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A64S0616
HB
LB
WE
HB
LB
WE
Timing Waveforms (continued)
Write Cycle 1-1
(Write Enable Controlled)
Address
(6)
t
SKEW
t
ASC
t
WC
t
t
AW
t
CW
AHC
t
CEH
t
ASC
t
WC
t
AW
t
CW
t
AHC
t
SKEW
CE1
,
Data In
Data Out
Write Cycle 1-2
(Write Enable Controlled)
Address
CE1
(6)
t
SKEW
t
ASC
t
BW
1
t
AS
4
t
WHZ
2
t
WP
t
DW
3
t
WR
t
DH
t
OW
1
t
AS
4
t
WHZ
t
BW
3
t
2
t
WP
t
DW
WR
t
DH
t
OW
t
AHC
t
SKEW
t
t
WC
SKEW
t
WC
t
BW
t
BW
,
1
t
AS
2
t
WP
t
DW
3
t
WR
t
WEH
t
DH
1
t
AS
2
t
WP
t
DW
Data In
t
WHZ
4
t
OW
t
WHZ
4
Data Out
PRELIMINARY (July, 2002, Version 0.1) 10 AMIC Technology, Inc.
3
t
WR
t
DH
t
OW
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A64S0616
HB
LB
WE
HB
LB
WE
Timing Waveforms (continued)
Write Cycle 2-1
(Chip Enable Controlled)
Address
(6)
t
SKEW
t
ASC
WC
t
t
t
AW
2
t
CW
AHC
t
CEH
t
ASC
t
WC
t
AW
2
t
CW
t
AHC
t
SKEW
CE1
3
t
t
BW
WR
t
BW
3
t
WR
,
t
Data In
Data Out
Write Cycle 2-2
(6)
(Chip Enable Controlled)
t
SKEW
t
WHZ
WP
t
DW
4
t
WC
t
DH
t
t
OW
t
SKEW
WHZ
t
WP
t
t
DW
4
t
WC
DH
t
OW
t
SKEW
Address
t
AHC
t
ASC
t
AW
CE1
3
t
t
BW
WR
t
BW
3
t
WR
,
t
WP
t
DW
t
DH
Data In
4
t
WHZ
t
OW
t
WHZ
Data Out
PRELIMINARY (July, 2002, Version 0.1) 11 AMIC Technology, Inc.
t
WP
t
DW
4
t
DH
t
OW
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A64S0616
HB
LB
WE
HB
LB
WE
Timing Waveforms (continued)
Write Cycle 3-1
(Byte Enable Controlled)
Address
(6)
t
SKEW
t
ASC
t
WC
AHC
AW
t
t
CW
t
t
t
CEH
ASC
t
WC
AW
t
t
CW
t
AHC
SKEW
t
CE1
3
t
1
t
AS
2
t
BW
WR
1
t
AS
2
t
BW
3
t
WR
,
t
Data In
Data Out
Write Cycle 3-2
(6)
(Byte Enable Controlled)
t
WHZ
WP
t
DW
4
t
DH
4
t
t
OW
WHZ
t
WP
t
t
DW
DH
t
OW
t
SKEW
t
WC
SKEW
t
Address
t
ASC
CE1
3
t
1
t
AS
2
t
BW
WR
,
t
WP
t
DW
Data In
4
WHZ
t
Data Out
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low
3. tWR is measured from the earliest of
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high for Write Cycle.
t
DH
t
OW
, WE and (HB and, or LB ).
1CE
or WE or (HB and, or LB ) going high to the end of the Write cycle.
1CE
t
WHZ
SKEW
t
t
AHC
WR
t
3
t
DH
t
OW
t
WC
t
AW
1
t
AS
4
2
t
BW
t
WP
t
DW
PRELIMINARY (July, 2002, Version 0.1) 12 AMIC Technology, Inc.
Page 14
A64S0616
AC Test Conditions
Input Pulse Levels 0.4V to 2.4V
Input Rise And Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 3 and 4
TTL
CL
30pF
* Including scope and jig. * Including scope and jig.
CL
TTL
5pF
Figure 3. Output Load Figure 4. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Ordering Information
Operating Current
Part No. Access Time (ns)
Max. (mA)
A64S0616G-70 70 35 10 48B Mini BGA
A64S0616G-85 85 30 10 48B Mini BGA
A64S0616G-70I 70 35 10 48B Mini BGA
Power Down Mode
Standby Current
Max. (µµA)
Package
A64S0616G-85I 85 30 10 48B Mini BGA
Note: -I is for industrial operating temperature range
PRELIMINARY (July, 2002, Version 0.1) 13 AMIC Technology, Inc.
Page 15
A64S0616
Symbol
Min
Typ
Max
Package Information
Mini BGA 6X8 (48 BALLS) Outline Dimensions unit : millimeter(mm)
C1
Bottom View
Pin A1 Index
123456
A
B
C
D
E
A
A
B1
D
0.10
E1
F
G
H
Diameter D
Solder Ball
Pin A1 Index
Top View
C
B
E2
E
A - 0.75 B 5.90 6.00 6.10
B1 - 3.75 -
C 7.90 8.00 8.10
C1 - 5.25 -
D 0.30 0.35 0.40
E 1.00 1.10 1.20
E1 - 0.36 E2 0.2 0.25 0.3
PRELIMINARY (July, 2002, Version 0.1) 14 AMIC Technology, Inc.
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