Page 1
A63L73321 Series
128K X 32 Bit Synchronous High Speed SRAM
Preliminary with Burst Counter and Flow-through Data Output
PRELIMINARY (December, 1998, Version 0.0) AMIC Technology, Inc.
Document Title
128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through
Data Output
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue December 14, 1998 Preliminary
0.1 Change fast access times from 8.5/9.5/10 ns to 9.5/10/12
June 9, 1999
Change ICC1 from 300mA to 350mA(max.)
Page 2
A63L73321 Series
128K X 32 Bit Synchronous High Speed SRAM
Preliminary with Burst Counter and Flow-through Data Output
PRELIMINARY (June, 1999, Version 0.1) 1 AMIC Technology, Inc.
Features
n Fast access times: 9.5/10/12 ns
n Single +3.3V+10% or +3.3V-5% power supply
n Synchronous burst function
n Individual Byte Write control and Global Write
n Three separate chip enables allow wide range of
options for CE control, address pipelining
n Selectable BURST mode
n SLEEP mode (ZZ pin) provided
n Available in 100-pin LQFP package
General Description
The A63L73321 is a high-speed, low-power SRAM
containing 4,194,304 bits of bit synchronous memory,
organized as 131,072 words by 32 bits.
The A63L73321 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output buffer and a 128K X 32 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 A16), all data inputs (I/O1 - I/O32), active LOW chip
enable ( CE ), two additional chip enables (CE2, CE2 ),
burst control inputs ( ADSC , ADSP , ADV ), byte write
enables ( BWE , BW1 , BW2, BW3, BW4 ) and Global
Write (GW ). Asynchronous inputs include output enable
(OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
(ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63L73321
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1
controls I/O1 - I/O8, BW2 controls I/O9 - I/O16, BW3
controls I/O17 - I/O24, and BW4 controls I/O25 - I/O32, all
on the condition that BWE is LOW. GW LOW causes
all bytes to be written.
Page 3
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 2 AMIC Technology, Inc.
Pin Configuration
NC
I/O17
I/O18
VCCQ
GNDQ
I/O19
I/O20
I/O21
I/O22
GNDQ
I/O23
I/O24
VCCQ
VCC
NC
I/O31
GND
I/O25
I/O26
VCCQ
GNDQ
I/O27
I/O28
I/O29
I/O30
GNDQ
VCCQ
I/O32
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
30
27
29
80
79
78
77
76
75
74
72
73
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O16
I/O15
VCCQ
GNDQ
I/O14
I/O13
I/O12
I/O11
GNDQ
VCCQ
I/O10
I/O9
GND
NC
VCC
ZZ
I/O8
I/O7
VCCQ
GNDQ
I/O6
I/O5
I/O4
I/O3
GNDQ
VCCQ
I/O2
I/O1
NC
50
49
48
47
46
45
44
43
424041
39
38
37
36
35
34
33
32
31
A16
A15
A14
A13
A12
A11
A10
NC
NC
VCC
GND
NC
NC
A0
A1
A2
A3
A4
A5
MODE
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CE2
A7
A6
CLK
GND
VCC
A9
A8
A63L73321
NC
ADV
ADSP
ADSC
OE
BWE
GW
CE2
BW1
BW2
BW3
BW4
CE
Page 4
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 3 AMIC Technology, Inc.
Block Diagram
MODE
LOGIC
CLK
LOGIC
ADDRESS
REGISTERS
BURST
LOGIC
ADDRESS
COUNTER
CLR
BYTE
WRITE
ENABLE
LOGIC
BYTE1
WRITE
DRIVER
BYTE2
WRITE
DRIVER
BYTE3
WRITE
DRIVER
BYTE4
WRITE
DRIVER
8
8
8
8
128KX8X4
MEMORY
ARRAY
8
8
8
8
32
OUTPUT
BUFFER
DATA-IN
REGISTERS
4
CHIP
ENABLE
LOGIC
OUTPUT
ENABLE
LOGIC
4
32
17
ZZ
MODE
ADV
CLK
ADSC
ADSP
A0-A16
GW
BWE
BW1
BW2
BW3
BW4
CE
CE2
CE2
OE
I/O1 - I/O
32
Page 5
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 4 AMIC Technology, Inc.
Pin Description
Pin No. Symbol Description
32 - 37, 44 - 50, 81, 82,
99, 100
A0 - A16 Address Inputs
89 CLK Clock
87, 93 - 96
BWE , BW1 - BW4
Byte Write Enables
88
GW
Global Write
86
OE
Output Enable
92, 97, 98
CE2 ,CE2, CE
Chip Enables
83
ADV
Burst Address Advance
84
ADSP
Processor Address Status
85
ADSC
Controller Address Status
31 MODE Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
64 ZZ Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
2, 3, 6 - 9, 12, 13, 18, 19,
22 - 25, 28, 29, 52, 53,
56 - 59, 62, 63, 68, 69,
72 - 75, 78, 79
I/O1- I/O32 Data Inputs/Outputs
1, 14, 16, 30, 38, 39, 42,
43, 51, 66, 80
NC No Connection
15, 41, 65, 91 VCC Power Supply
17, 40, 67, 90 GND Ground
4, 11, 20, 27,
54, 61, 70, 77
VCCQ Isolated Output Buffer Supply
5, 10, 21, 26,
55, 60, 71, 76
GNDQ Isolated Output Buffer Ground
Page 6
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 5 AMIC Technology, Inc.
Synchronous Truth Table (See Notes 1 Through 5)
Operation
Address
Used
CE
CE2
CE2
ADSP
ADSC
ADV
WRITE
OE
CLK
I/O
Operation
Deselected Cycle,
Power-down
NONE H X X X L X X X L-H High-Z
Deselected Cycle,
Power-down
NONE L X L L X X X X L-H High-Z
Deselected Cycle,
Power-down
NONE L H X L X X X X L-H High-Z
Deselected Cycle,
Power-down
NONE L X L H L X X X L-H High-Z
Deselected Cycle,
Power-down
NONE L H X H L X X X L-H High-Z
READ Cycle,
Begin Burst
External L L H L X X X L L-H Dout
READ Cycle,
Begin Burst
External L L H L X X X H L-H High-Z
WRITE Cycle,
Begin Burst
External L L H H L X L X L-H Din
READ Cycle,
Begin Burst
External L L H H L X H L L-H Dout
READ Cycle,
Begin Burst
External L L H H L X H H L-H High-Z
READ Cycle,
Continue Burst
Next X X X H H L H L L-H Dout
READ Cycle,
Continue Burst
Next X X X H H L H H L-H High-Z
READ Cycle,
Continue Burst
Next H X X X H L H L L-H Dout
READ Cycle,
Continue Burst
Next H X X X H L H H L-H High-Z
WRITE Cycle,
Continue Burst
Next X X X H H L L X L-H Din
WRITE Cycle,
Continue Burst
Next H X X X H L L X L-H Din
READ Cycle,
Suspend Burst
Current X X X H H H H L L-H Dout
READ Cycle,
Suspend Burst
Current X X X H H H H H L-H High-Z
READ Cycle,
Suspend Burst
Current H X X X H H H L L-H Dout
READ Cycle,
Suspend Burst
Current H X X X H H H H L-H High-Z
WRITE Cycle,
Suspend Burst
Current X X X H H H L X L-H Din
WRITE Cycle,
Suspend Burst
Current H X X X H H L X L-H Din
Page 7
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 6 AMIC Technology, Inc.
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2. WRITE = L means:
1) Any BWx (BW1,BW2 ,BW3 , or BW4) and BWE are low or
2) GW is low.
3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held
HIGH throughout the input data hold time.
5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to
the Write timing diagram for clarification.
Write Truth Table
Operation
GW
BWE
BW1
BW2
BW3
BW4
READ H H X X X X
READ H L H H H H
WRITE Byte 1 H L L H H H
WRITE all bytes H L L L L L
WRITE all bytes L X X X X X
Page 8
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 7 AMIC Technology, Inc.
Linear Burst Address Table (MODE = LOW)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00
Absolute Maximum Ratings*
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 2W
Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C
Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C
Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
Recommended DC Operating Conditions
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted)
Symbol Parameter Min. Typ. Max. Unit Note
VCC Supply Voltage (Operating Voltage Range) 3.135 3.3 3.6 V
VCCQ Isolated Input Buffer Supply 3.135 3.3 VCC V
GND Supply Voltage to GND 0.0 - 0.0 V
VIH Input High Voltage 2.0 - VCC+0.3 V 1, 2
VIHQ Input High Voltage (I/O Pins) 2.0 - VCC+0.3 V
VIL Input Low Voltage -0.3 - 0.8 V 1, 2
Page 9
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 8 AMIC Technology, Inc.
DC Electrical Characteristics
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted)
Symbol Parameter Min. Max. Unit Test Conditions Note
ILI Input Leakage Current - ±2.0 µA All inputs VIN = GND to VCC
ILO Output Leakage Current - ±2.0 µA
OE = VIH, Vout = GND to VCC
ICC1 Supply Current - 350 mA
Device selected; VCC = max.
Iout = 0mA, all inputs = VIH or VIL
Cycle time = tKC min.
3, 11
ISB1 Standby Current - 25 mA
Device deselected; VCC = max.
All inputs are fixed.
All inputs ≥ VCC - 0.2V
or ≤ GND + 0.2V
Cycle time = tKC min.
11
ISB2 - 10 mA ZZ ≥ VCC - 0.2V
VOL Output Low Voltage - 0.4 V IOL = 8 mA
VOH Output High Voltage 2.4 - V IOH = -4 mA
Capacitance
Symbol Parameter Typ. Max. Unit Conditions
CIN Input Capacitance 3 4 pF
TA = 25 C; f = 1MHz
CI/O Input/Output Capacitance 4 5 pF
VCC = 3.3V
* These parameters are sampled and not 100% tested.
Page 10
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 9 AMIC Technology, Inc.
AC Characteristics (0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%)
Symbol Parameter
-9.5 -10 -12
Unit Note
Min. Max. Min. Max. Min. Max.
tKC Clock Cycle Time 10 - 11 - 12 - ns
tKH Clock High Time 4.0 - 4.0 - 4.0 - ns
tKL Clock Low Time 4.0 - 4.0 - 4.0 - ns
tKQ Clock to Output Valid - 9.5 - 10 - 12 ns
tKQX Clock to Output Invalid 3.0 - 3.0 - 3.0 - ns
tKQLZ Clock to Output in Low-Z 4.0 - 4.0 - 4.0 - ns 5, 6
tKQHZ Clock to Output in High-Z - 5.0 - 5.0 - 5.0 ns 5, 6
tOEQ
OE to Output Valid
- 5.0 - 5.0 - 5.0 ns 8
tOELZ
OE to Output in Low-Z
0 - 0 - 0 - ns 5, 6
tOEHZ
OE to Output in High-Z
- 5.0 - 5.0 - 5.0 ns 5, 6
Setup Times
tAS Address 2.0 - 2.0 - 2.5 - ns 7, 9
tADSS Address Status
(ADSC , ADSP )
2.0 - 2.0 - 2.5 - ns 7, 9
tADVS
Address Advance (ADV )
2.0 - 2.0 - 2.5 - ns 7, 9
tWS Write Signals
(BW1 , BW2 , BW3,
BW4, BWE, GW )
2.0 - 2.0 - 2.5 - ns 7, 9
tDS Data-in 2.0 - 2.0 - 2.5 - ns 7, 9
tCES Chip Enable
(CE , CE2, CE2 )
2.0 - 2.0 - 2.5 - ns 7, 9
Page 11
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 10 AMIC Technology, Inc.
AC Characteristics (continued)
Symbol Parameter
-9.5 -10 -12
Unit Note
Min. Max. Min. Max. Min. Max.
Hold Times
tAH Address 0.5 - 0.5 - 0.5 - ns 7, 9
tADSH Address Status
(ADSC , ADSP )
0.5 - 0.5 - 0.5 - ns 7, 9
tAAH
Address Advance (ADV )
0.5 - 0.5 - 0.5 - ns 7, 9
tWH Write Signal
(BW1 , BW2 , BW3,
BW4, BWE, GW )
0.5 - 0.5 - 0.5 - ns 7, 9
tDH Data-in 0.5 - 0.5 - 0.5 - ns 7, 9
tCEH Chip Enable
(CE , CE2, CE2 )
0.5 - 0.5 - 0.5 - ns 7, 9
Notes:
1. All voltages refer to GND.
2. Overshoot: VIH ≤ +4.6V for t ≤ tKC/2.
Undershoot: VIH ≥ -0.7V for t ≤ tKC/2.
Power-up: VIH ≤ +3.6 and VCC ≤ 3.1V
for t ≤ 200ms
3. ICC1 is given with no output current. ICC1 increases with greater output loading and faster cycle times.
4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
5. For output loading, CL = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage.
6. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tQELZ.
7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and (ADSC or ADV LOW) or ADSP LOW for the
required setup and hold times.
8. OE has no effect when a Byte Write enable is sampled LOW.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be
valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.
10. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values.
AC I/O curves are available upon request.
11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means
device is active (not in POWER-DOWN mode).
12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage
current of 10µA.
13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to
emerge from SLEEP mode to ensure no data is lost.
Page 12
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 11 AMIC Technology, Inc.
Timing Waveforms
Read Timing
Notes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following
A2.
2. CE and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH.
WhenCE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not
cause Q to be driven until after the following clock rising edge.
4. Outputs are disabled tKQHZ after deselect.
CLK
ADSP
ADSC
ADDRESS
A1 A2
GW,BWE
BW1-BW4
CE
(NOTE 2)
ADV
OE
Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2)
Q(A2+1)
High-Z
DOUT
(NOTE 3)
tOEHZ
tKQX
tKQ
Burst wraps around
to its initial state
tKQHZ
BURST READ
Deselect cycle
(Note 4)
ADV suspends burst
tADVHtADVS
tCEHtCES
tWHtWS
tAHtAS
tADSHtADSS
tADSHtADSS
tKLtKH
tKC
Q(A2+2)
(NOTE *1)
tOEQ
tKQLZ
tKQ
tOELZ
Single READ
Don't Care
Undefined
Page 13
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 12 AMIC Technology, Inc.
Timing Waveforms (continued)
CLK
ADSP
ADSC
ADDRESS
A1 A2 A3
OE
D(A2) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1)High-Z
DIN
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
t
ADSH
t
ADSS
ADSC extends burst
GW
CE
(NOTE 2)
ADV
D(A1) D(A2+1)
D(A3+2)
DOUT
BURST READ Single WRITE Extended BURST WRITE
t
OEHZ
t
DH
t
DS
(NOTE 3)
(NOTE 4)
ADV suspends burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
BYTE WRITE signals are ignored
for first cycle when ADSP initiates burst
t
WH
t
WS
BWE,BW1-BW4
(NOTE 5)
(NOTE 1)
Don't Care
Undefined
Write Timing
Notes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
2. Timing for CE2 and CE2 is identical to that for CE. As shown in the above diagram, when CE is LOW, CE2
is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
4. ADV must be HIGH to permit a Write to the loaded address.
5. Byte Write enables are decided by means of a Write truth table.
Page 14
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 13 AMIC Technology, Inc.
Timing Waveforms (continued)
Read/Write Timing
Notes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following
A4.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE is LOW and CE2 is HIGH,
When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC , or ADV cycle is
performed.
4. Byte Write enables are decided by means of a Write truth table.
5. Back-to-back READs may be controlled by either ADSP or ADSC
CLK
ADSP
ADSC
ADDRESS
A1 A3
CE
(NOTE 2)
ADV
OE
D(A3)
D(A5)
D(A6)High-Z
DIN
t
CEH
t
CES
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
A2 A4 A5 A6
GW,BWE,
BW1-BW4
(NOTE 3)
Q(A1) Q(A2) Q(A4) Q(A4+1)
DOUT
Back-to-Back READs Single WRITE BURST READ
Back-to-Back
WRITEs
(NOTE 1)
t
KQ
t
OELZ
t
DH
t
DS
tWSt
WH
tASt
AH
Q(A4+2) Q(A4+3)
t
OEHZ
t
KQ
Don't Care
Undefined
Page 15
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 14 AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels GND to 3V
Input Rise and Fall Times 1.5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figures 1 and 2
ZO=50Ω
Q
RL=50Ω
VT=1.5V
Figure 1. Output Load Equivalent
350Ω
Q
+3.3V
320Ω
5pF
Figure 2. Output Load Equivalent
Page 16
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 15 AMIC Technology, Inc.
Ordering Information
Part No. Access Times (ns) Package
A63L73321E-9.5 9.5 100L LQFP
A63L73321E-10 10 100L LQFP
A63L73321E-12 12 100L LQFP
Page 17
A63L73321 Series
PRELIMINARY (June, 1999, Version 0.1) 16 AMIC Technology, Inc.
Package Information
LQFP 100L Outline Dimensions unit: inches/mm
Symbol
Dimensions in inches Dimensions in mm
Min. Nom. Max. Min. Nom. Max.
A1 0.002 - - 0.05 - A2 0.053 0.055 0.057 1.35 1.40 1.45
b 0.011 0.013 0.015 0.27 0.32 0.37
c 0.005 - 0.008 0.12 - 0.20
HE 0.860 0.866 0.872 21.85 22.00 22.15
E 0.783 0.787 0.791 19.90 20.00 20.10
HD 0.624 0.630 0.636 15.85 16.00 16.15
D 0.547 0.551 0.555 13.90 14.00 14.10
e 0.026 BSC 0.65 BSC
L 0.018 0.024 0.030 0.45 0.60 0.75
L1 0.039 REF 1.00 REF
y - - 0.004 - - 0.1
θ 0° 3.5° 7° 0° 3.5° 7°
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
31
50
51
80
81
100
HD
D
E
HE
1 30
b
D
y
A1A2
L1
c
e
θ
L
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