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A63L0636
1M X 36 Bit Synchronous High Speed SRAM with
Preliminary Burst Counter and Pipelined Data Output
Document Title
1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data
Output
Revision History
Rev. No.
0.0 Initial issue July 25, 2005 Preliminary
History Issue Date Remark
PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp.
Page 2
A63L0636
1M X 36 Bit Synchronous High Speed SRAM with
Preliminary Burst Counter and Pipelined Data Output
Features
Fast access times: 2.6/2.8/3.2/3.5/3.8/4.2 ns
(250/227/200/166/150/133 MH
Single +3.3V+10% or +3.3V-5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Registered output for pipelined applications
Z)
General Description
The A63L0636E is a high-speed SRAM containing 36M
bits of bit synchronous memory, organized as 1024K
words by 36 bits.
The A63L0636E combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 1MX36 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 A19), all data inputs (I/O
CE ), two additional chip enables (CE2, CE2 ), burst
(
control inputs (
BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write
(
GW ). Asynchronous inputs include output enable ( OE ),
(
clock (CLK), BURST mode (MODE) and SLEEP mode
(ZZ).
ADSC , ADSP , ADV ), byte write enables
1 - I/O36), active LOW chip enable
Three separate chip enables allow wide range of
options for CE control, address pipelining
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Available in 100-pin LQFP package
Burst operations can be initiated with either the address
status processor (
ADSC ) input pin. Subsequent burst sequence burst
(
addresses can be internally generated by the A63L0636E
and controlled by the burst advance (
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written.
1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls
I/O
19 - I/O27, and BW4 controls I/O28 - I/O36, all on the
I/O
condition that
to be written.
ADSP ) or address status controller
ADV ) pin. Write
BW1 controls
BWE is LOW. GW LOW causes all bytes
PRELIMINARY (July, 2005, Version 0.0) 1 AMIC Technology, Corp.
Page 3
A63L0636
Pin Configuration
CE2
A7
I/O19
I/O20
I/O21
VCCQ
GNDQ
I/O
I/O23
I/O24
I/O25
GNDQ
VCCQ
I/O
I/O27
NC
VCC
NC
GND
I/O
I/O29
VCCQ
GNDQ
I/O
I/O31
I/O32
I/O33
GNDQ
VCCQ
I/O
I/O
I/O36
A6
CE
98
99
100
1
BW3
BW4
95
96
97
CE2
BW1
BW2
92
93
94
2
3
4
5
22
6
7
8
9
10
11
26
12
13
14
15
16
A63L0636E
17
18
28
19
20
21
22
30
23
24
25
26
27
34
28
29
35
30
39
38
37
36
35
34
33
32
31
CLK
GND
VCC
90
91
BWE
GW
87
88
89
44
43
424041
OE
86
45
ADSP
ADSC
84
85
47
46
A9
A8
ADV
81
82
83
48
80
NC
17
I/O
79
I/O16
78
VCCQ
77
GNDQ
76
I/O
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
15
I/O14
I/O13
I/O12
GNDQ
VCCQ
11
I/O
I/O10
GND
NC
VCC
ZZ
8
I/O
I/O7
VCCQ
GNDQ
6
I/O
I/O5
I/O4
I/O3
GNDQ
VCCQ
2
I/O
I/O1
I/O9
A5
MODE
NC
A19
VCC
GND
A10
A18
A17
A16
A15
A14
A13
A12
A11
A0
A1
A2
A3
A4
PRELIMINARY (July, 2005, Version 0.0) 2 AMIC Technology, Corp.
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A63L0636
Block Diagram
CLK
ZZ
MODE
ADV
CLK
LOGIC
ADSC
ADSP
MODE
LOGIC
BURST
LOGIC
ADDRESS
COUNTER
CLR
A0-A19
GW
BWE
BW1
BW2
BW3
BW4
CE
CE2
CE2
OE
ADDRESS
REGISTERS
BYTE
WRITE
ENABLE
LOGIC
CHIP
ENABLE
LOGIC
8
BYTE1
WRITE
DRIVER
8
BYTE2
WRITE
DRIVER
8
BYTE3
WRITE
DRIVER
8
BYTE4
WRITE
DRIVER
PIPELINED
ENABLE
LOGIC
9
9
9
9
36
4
OUTPUT
ENABLE
LOGIC
4
20
1MX9X4
MEMORY
ARRAY
DATA-IN
REGISTERS
36
OUTPUT
REGISTERS
I/O1 - I/O36
PRELIMINARY (July, 2005, Version 0.0) 3 AMIC Technology, Corp.
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A63L0636
Pin Description
Pin No. Symbol Description
32 – 37,39, 44 - 50, 81,
82, 99, 100
89 CLK Clock
87, 93 - 96
88
86
92, 97, 98
83
84
85
31 MODE Burst Mode: HIGH or NC (Interleaved burst)
64 ZZ Asynchronous Power-Down (Snooze): HIGH (Sleep)
1,2, 3, 6 - 9, 12, 13, 18,
19, 22 - 25, 28, 29,
30,51,52, 53,
56 - 59, 62, 63, 68, 69, 72
- 75, 78, 79,80
A0 - A19 Address Inputs
BWE , BW1 - BW4
GW
OE
CE2 ,CE2, CE
ADV
ADSP
ADSC
I/O1- I/O36 Data Inputs/Outputs
Byte Write Enables
Global Write
Output Enable
Chip Enables
Burst Address Advance
Processor Address Status
Controller Address Status
LOW (Linear burst)
LOW or NC (Wake up)
15, 41, 65, 91 VCC Power Supply
17, 40, 67, 90 GND Ground
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
PRELIMINARY (July, 2005, Version 0.0) 4 AMIC Technology, Corp.
VCCQ Isolated Output Buffer Supply
GNDQ Isolated Output Buffer Ground
Page 6
A63L0636
ADSP
A
ADV
Synchronous Truth Table (See Notes 1 Through 5)
Operation
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
READ Cycle,
Begin Burst
READ Cycle,
Begin Burst
WRITE Cycle,
Begin Burst
READ Cycle,
Begin Burst
READ Cycle,
Begin Burst
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
WRITE Cycle,
Continue Burst
WRITE Cycle,
Continue Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
WRITE Cycle,
Suspend Burst
WRITE Cycle,
Suspend Burst
Address
Used
NONE H X X X L X X X L-H High-Z
NONE L X L L X X X X L-H High-Z
NONE L H X L X X X X L-H High-Z
NONE L X L H L X X X L-H High-Z
NONE L H X H L X X X L-H High-Z
External L L H L X X X L L-H Dout
External L L H L X X X H L-H High-Z
External L L H H L X L X L-H Din
External L L H H L X H L L-H Dout
External L L H H L X H H L-H High-Z
Next X X X H H L H L L-H Dout
Next X X X H H L H H L-H High-Z
Next H X X X H L H L L-H Dout
Next H X X X H L H H L-H High-Z
Next X X X H H L L X L-H Din
Next H X X X H L L X L-H Din
Current X X X H H H H L L-H Dout
Current X X X H H H H H L-H High-Z
Current H X X X H H H L L-H Dout
Current H X X X H H H H L-H High-Z
Current X X X H H H L X L-H Din
Current H X X X H H L X L-H Din
CE
CE2
CE2
DSC
WRITE
OE
CLK
I/O
Operation
PRELIMINARY (July, 2005, Version 0.0) 5 AMIC Technology, Corp.
Page 7
A63L0636
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2.
1) Any
2)
3. All inputs except
4. For write cycles that follow read cycles,
HIGH throughout the input data hold time.
5.
more byte write enable signals and
the Write timing diagram for clarification.
WRITE = L means:
BWx (BW1,BW2 ,BW3, or BW4 ) and BWE are low or
GW is low.
OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
OE must be HIGH before the input data request setup time and held
ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to
Write Truth Table
Operation
READ H H X X X X
READ H L H H H H
WRITE Byte 1 H L L H H H
WRITE all bytes H L L L L L
WRITE all bytes L X X X X X
GW BWE BW1 BW2 BW3 BW4
PRELIMINARY (July, 2005, Version 0.0) 6 AMIC Technology, Corp.
Page 8
A63L0636
Linear Burst Address Table (MODE = LOW)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00
Absolute Maximum Ratings*
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Power Dissipation (P
Operating Temperature (Topr) . . . . . . . . . . . 0
Storage Temperature (Tbias) . . . . . . . . . . -10
Storage Temperature (Tstg) . . . . . . . . . . . -55
D) . . . . . . . . . . . . . . . . . . . . . . . . 2W
°C to 70°C
°C to 85 °C
°C to 125°C
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
Recommended DC Operating Conditions
(0
°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted)
Symbol Parameter Min. Typ. Max. Unit Note
VCC Supply Voltage (Operating Voltage Range) 3.1 3.3 3.6 V
VCCQ Isolated Input Buffer Supply 3.1 3.3 VCC V
GND Supply Voltage to GND 0.0 - 0.0 V
VIH Input High Voltage 2.0 - VCC+0.3 V 1, 2
VIHQ Input High Voltage (I/O Pins) 2.0 - VCC+0.3 V
VIL Input Low Voltage -0.3 - 0.8 V 1, 2
PRELIMINARY (July, 2005, Version 0.0) 7 AMIC Technology, Corp.
Page 9
A63L0636
DC Electrical Characteristics
°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted)
(0
Symbol Parameter Min. Max. Unit Test Conditions Note
⏐ILI⏐ Input Leakage Current - ±2.0 µA All inputs VIN = GND to VCC
⏐ILO⏐ Output Leakage Current - ±2.0 µA
CC1
I
Supply Current
-
400
mA
OE = VIH, Vout = GND to VCC
Device selected; VCC = max.
Iout = 0mA, all inputs = VIH or VIL
Cycle time = t
KC min.
Device deselected; VCC = max.
3, 11
All inputs are fixed.
SB1
I
Standby Current
-
180
mA
All inputs ≥ VCC - 0.2V
≤ GND + 0.2V
or
Cycle time = t
KC min.
11
ISB2 - 150 mA ZZ ≥ VCC - 0.2V
VOL Output Low Voltage - 0.4 V IOL = 8 mA
VOH Output High Voltage 2.4 - V IOH = -4 mA
Capacitance
Symbol Parameter Typ. Max. Unit Conditions
CIN Input Capacitance 3 4 pF
CI/O Input/Output Capacitance 4 5 pF
T
A = 25 C; f = 1MHz
VCC = 3.3V
* These parameters are sampled and not 100% tested.
PRELIMINARY (July, 2005, Version 0.0) 8 AMIC Technology, Corp.
Page 10
A63L0636
AC Characteristics (0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%)
Symbo
Parameter -2.6 -2.8 -3.2 -3.5 -3.8 -4.2 Unit Note
l
tKC
tKH
tKL
tKQ
tKQX
tKQLZ
tKQHZ
tOEQ
tOELZ
tOEHZ
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock to Output in High-Z
OE to Output Valid
OE to Output in Low-Z
OE to Output in High-Z
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max
4.0 - 4.4 - 5.0 - 6.0 - 6.7 - 7.5 - ns
1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 - ns
1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 - ns
- 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns
1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns
1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns 5, 6
1.5 2.6 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.5 ns 5, 6
- 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns 8
0 - 0 - 0 - 0 - 0 - 0 - ns 5, 6
- 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns 5, 6
Setup Times
tAS Address 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 7, 9
tADSS
Address Status (
ADSC ,
1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 7, 9
ADSP )
tADVS Address Advance
(
ADV )
tWS Write Signals
BW1, BW2, BW3,
(
BW4 , BWE, GW )
1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 7, 9
1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 7, 9
tDS Data-in 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 7, 9
tCES
Chip Enable (
CE, CE2,
1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 7, 9
CE2 )
PRELIMINARY (July, 2005, Version 0.0) 9 AMIC Technology, Corp.
Page 11
A63L0636
AC Characteristics (continued)
Symbo
Parameter -2.6 -2.8 -3.2 -3.5 -3.8 -4.2 Unit Note
l
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max
Hold Times
tAH Address 0.3 - 0.4 - 0.5 - 0.5 - 0.5 - 0.5 - ns 7, 9
tADVH Address Status
(
ADSC , ADSP )
tAAH
Address Advance (
tWH Write Signal
BW1, BW2, BW3,
(
BW4 , BWE, GW )
ADV )
0.3 - 0.4 - 0.5 - 0.5 - 0.5 - 0.5 - ns 7, 9
0.3 - 0.4 - 0.5 - 0.5 - 0.5 - 0.5 - ns 7, 9
0.3 - 0.4 - 0.5 - 0.5 - 0.5 - 0.5 - ns 7, 9
tDH Data-in 0.3 - 0.4 - 0.5 - 0.5 - 0.5 - 0.5 - ns 7, 9
tCEH Chip Enable
CE, CE2, CE2 )
(
0.3 - 0.4 - 0.5 - 0.5 - 0.5 - 0.5 - ns 7, 9
Notes:
1. All voltages refer to GND.
2. Overshoot: V
Undershoot: V
Power-up: V
for t
CC is given with no output current. ICC increases with greater output loading and faster cycle times.
3. I
IH ≤ +4.6V for t ≤ tKC/2.
IH ≥ -0.7V for t ≤ tKC/2.
IH ≤ +3.6 and VCC ≤ 3.1V
≤ 200ms
4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
5. For output loading, C
6. At any given temperature and voltage condition, t
7. A WRITE cycle is defined by at least one Byte Write enable LOW and
times. A READ cycle is defined by all byte write enables HIGH and (
L = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage.
KQHZ is less than tKQLZ and tOEHZ is less than tQELZ.
ADSP HIGH for the required setup and hold
ADSC or ADV LOW) or ADSP LOW for the
required setup and hold times.
OE has no effect when a Byte Write enable is sampled LOW.
8.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either
ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be
valid at each rising edge of CLK when either
10. The load used for V
OH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values.
ADSP or ADSC is LOW to remain enabled.
AC I/O curves are available upon request.
11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means
device is active (not in POWER-DOWN mode).
12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage
current of 10
µA.
13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to
emerge from SLEEP mode to ensure no data is lost.
PRELIMINARY (July, 2005, Version 0.0) 10 AMIC Technology, Corp.
Page 12
A63L0636
Timing Waveforms
ADDRESS
GW,BWE
BW1-BW4
(NOTE *2)
CLK
ADSP
ADSC
ADV
DOUT
t
ADSS
t
AS
t
CE
OE
CES
t
KC
t
t
KH
A1 A2 A3
KL
t
ADSH
t
t
ADSS
t
AH
t
t
WS
t
CEH
(NOTE *3)
t
High-Z
WH
KQLZ
t
KQ
Single READ BURST READ
ADSH
t
t
ADVS
t
OEHZ
Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2)
ADVH
t
OELZ
(NOTE *1)
ADV suspends
burst
t
OEQ
t
KQ
t
KQX
Burst continued with
new base address
Q(A2+1)
Burst wraps around
to its initial state
Delselected
cycle
(NOTE *4)
t
Q(A3)
KQHZ
Read Timing
Notes:
*1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for
LOW and CE2 is HIGH. When
*3. Timing shown assumes that the device was not enabled before entering this sequence.
be driven until after the rising edge of the following clock.
CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
CE is HIGH, CE2 is HIGH and CE2 is LOW.
OE does not cause Q to
PRELIMINARY (July, 2005, Version 0.0) 11 AMIC Technology, Corp.
Page 13
A63L0636
Timing Waveforms (continued)
ADDRESS
BWE,BW 1-BW4
(NOTE *5)
(NOTE *2)
CLK
ADSP
ADSC
GW
ADV
DIN
DOUT
t
ADSS
t
AS
t
CE
OE
CES
BURST READ Single W RITE Extended BURST WRITE
t
KC
t
t
KH
A1 A2 A3
(NOTE *3)
t
KL
t
ADSH
t
t
ADSS
BYTE WRITE signals are ignored
for first cycle when ADSP initiates burst
t
CEH
OEHZ
ADSH
t
AH
(NOTE *4)
t
DH
t
DS
D(A1) D(A2+1)
D(A2) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1)High-Z
t
WS
(NOTE *1)
ADSC extends burst
t
WH
ADV suspends burst
t
t
ADSS
ADSH
t
ADVS
t
t
WH
WS
t
ADVH
D(A3+2)
Write Timing
Notes: *1. D(A2) refers to output from address A2. D(A2+ 1) refers to output from the internal burst address immediately
following A2.
*2. Timing for
is LOW and CE2 is HIGH. When
*3.
OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
*4.
ADV must be HIGH to permit a Writ e to the loaded address.
*5. Byte Write enables are decided by means of a Write trut h table.
CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2
CE is HIGH, CE2 is HIGH and CE2 is LOW.
PRELIMINARY (July, 2005, Version 0.0) 12 AMIC Technology, Corp.
Page 14
A63L0636
Timing Waveforms (continued)
ADSP
ADSC
ADDRESS
GW,BWE,
BW1-BW4
(NOTE *3)
(NOTE *2)
CLK
t
ADSS
A1 A3
t
CE
ADV
CES
t
KC
t
t
ADSH
KL
tWSt
WH
t
CEH
t
KH
tASt
AH
A2 A4 A5 A6
DIN
OE
t
KQ
t
OEHZ
t
KQLZ
High-Z Q(A1) Q(A2) Q(A3) Q(A4) Q(A4+1) Q(A4+2)
Back-to-Back READs Single WRITE
t
DH
t
DS
D(A3)
t
OELZ
t
KQ
Pass-through
READ
(NOTE *4)
(NOTE *1)
BURST READ
D(A5)
Q(A4+3)DOUT
D(A6)High-Z
Back-to-Back
WRITEs
Read/Write Timing
Notes:
*1. Q(A4) refers to output from address A4. Q(A4+1) ref ers t o output from the internal burst address immediately
following A4.
*2. Timing for
LOW and CE2 is HIGH. When
*3. Byte Write enables are decided by means of a Write trut h table.
*4. Pass-through occurs when data is first written, then Read in sequence.
CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
CE is HIGH, CE2 is HIGH and CE2 is LOW.
PRELIMINARY (July, 2005, Version 0.0) 13 AMIC Technology, Corp.
Page 15
A63L0636
AC Test Conditions
Input Pulse Levels GND to 3V
Input Rise and Fall Times 1.5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figures 1 and 2
Q
RL=50
ZO=50
Ω
VT=1.5V
Ω
Figure 1. Output Load Equivalent
+3.3V
Ω
320
Q
350
Ω
5pF
Figure 2. Output Load Equivalent
PRELIMINARY (July, 2005, Version 0.0) 14 AMIC Technology, Corp.
Page 16
A63L0636
Ordering Information
Part No. Access Times (ns) Frequency (MHz) Package
A63L0636E-2.6 2.6 250 100L LQFP
A63L0636E-2.6F 2.6 250 100L Pb-Free LQFP
A63L0636E-2.8 2.8 225 100L LQFP
A63L0636E-2.8F 2.8 225 100L Pb-Free LQFP
A63L0636E-3.2 3.2 200 100L LQFP
A63L0636E-3.2F 3.2 200 100L Pb-Free LQFP
A63L0636E-3.5 3.5 166 100L LQFP
A63L0636E-3.5F 3.5 166 100L Pb-Free LQFP
A63L0636E-3.8 3.8 150 100L LQFP
A63L0636E-3.8F 3.8 150 100L Pb-Free LQFP
A63L0636E-4.2 4.2 133 100L LQFP
A63L0636E-4.2F 4.2 133 100L Pb-Free LQFP
PRELIMINARY (July, 2005, Version 0.0) 15 AMIC Technology, Corp.
Page 17
A63L0636
Package Information
LQFP 100L Outline Dimensions
H
E
80
E
51
A
1
A
2
y
D
unit: inches/mm
81
D
HD
100
130
b
e
θ
50
31
c
Symbol
Min. Nom. Max. Min. Nom. Max.
A1 0.002 - - 0.05 - A2 0.053 0.055 0.057 1.35 1.40 1.45
b 0.011 0.013 0.015 0.27 0.32 0.37
c 0.005 - 0.008 0.12 - 0.20
HE 0.860 0.866 0.872 21.85 22.00 22.15
E 0.783 0.787 0.791 19.90 20.00 20.10
HD 0.624 0.630 0.636 15.85 16.00 16.15
D 0.547 0.551 0.555 13.90 14.00 14.10
e 0.026 BSC 0.65 BSC
L 0.018 0.024 0.030 0.45 0.60 0.75
L1 0.039 REF 1.00 REF
y - - 0.004 - - 0.1
θ 0° 3.5° 7° 0° 3.5° 7°
Dimensions in inches Dimensions in mm
L1
L
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY (July, 2005, Version 0.0) 16 AMIC Technology, Corp.
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