0.1 Modify VCCmax from 3.3V to 3.6V December 20, 2000
0.2 Add 55ns grade spec. for VCC = 3.0V to 3.6V March 23, 2001
PRELIMINARY (March, 2001, Version 0.2)AMIC Technology, Inc.
Page 2
A62S8308 Series
Preliminary 256K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.6V
n Access times: 55ns (max.): for VCC = 3.0V to 3.6V
70ns (max.): for VCC = 2.7V to 3.6V
n Current:
A62S8308-S series: Operating: 40mA (max.)
Standby: 10µA (max.)
A62S8308-SI series: Operating: 40mA (max.)
Standby: 15µA (max.)
n Extended operating temperature range:-25°C to 85°C
for –SI series
General Description
The A62S8308 is a low operating current 2,097,152-bit
static random access memory organized as 262,144
words by 8 bits and operates on a low power supply
voltage from 2.7V to 3.6V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2V (min.)
n Available in 32-pin SOP, TSOP, sTSOP (8X
13.4mm) forward type and 36-ball Mini BGA (6X8)
packages
Two chip enable inputs are provided for power down and
a device enable and an output enable input are included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
nn SOP nn TSOP/(sTSOP) nn Mini BGA (6X8) Top View
(forward type)
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
1
2
3
4
5
6
A62S8308M
7
8
9
10
11
12
13
14
15
1617
VCC
32
A15
31
CE2
30
WE
29
A13
28
A8
27
A9
26
A11
25
OE
24
A10
23
22
CE1
I/O7
21
I/O6
20
I/O5
19
I/O4
18
I/O3GND
A11
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
~
~
A62S8308V
(A62S8308X)
~
~
123456
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AA0A1CE2A3A6A8
A10
CE1
BI/O4A2
7
I/O
6
I/O
5
CI/O5NCA5I/O1
I/O
4
I/O
3
I/O
DVSSVCC
GND
2
I/O
EVCCVSS
1
I/O
0
I/O
FI/O6NCA17I/O2
A0
A1
A2
A3
GI/O
7
OECE1
A4A7I/O
WE
A16A15I/O
HA9A10A11A12A13A14
0
3
PRELIMINARY (March, 2001, Version 0.2) 1 AMIC Technology, Inc.
Page 3
A62S8308 Series
Block Diagram
A0
A15
A16
A17
I/O0
I/O7
CE2
CE1
OE
WE
Pin Descriptions - SOP
CONTROL
CIRCUIT
ROW
DECODER
INPUT DATA
CIRCUIT
VCC
GND
1024 X 2048
MEMORY ARRAY
COLUMN I/O
Pin Description - TSOP/sTSOP
Pin No. Symbol Description
1 - 12, 23,
25 - 28, 31
13 - 15,
17 - 21
A0 - A17 Address Inputs
I/O0 - I/O7Data Inputs/Outputs
16 GND Ground
22
24
29
CE1
OE
WE
Chip Enable 1
Output Enable
Write Enable
30 CE2 Chip Enable 2
32 VCC Power Supply
Pin No. Symbol Description
1 - 4, 7,
9 - 20, 31
5
A0 - A17 Address Inputs
WE
Write Enable
6 CE2 Chip Enable 2
8 VCC Power Supply
21 - 23,
25 - 29
I/O0 - I/O7Data Inputs/Outputs
24 GND Ground
30
32
CE1
OE
Chip Enable 1
Output Enable
PRELIMINARY (March, 2001, Version 0.2) 2 AMIC Technology, Inc.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol Parameter
ILI
ILO
ICC
ICC1- 40 - 40 mA
ICC2
Input Leakage
Current
Output Leakage
Current
Active Power
Supply Current
Dynamic Operating
Current
A62S8308-55S/70S A62S8308-55SI/70SI
Min. Max. Min. Max.
- 1 - 1
- 1 - 1
- 3 - 3 mA
- 10 - 10 mA
Unit Conditions
VIN = GND to VCC
µA
CE1 = VIH or CE2 = VIL or
µA
OE = VIH or WE = VIL
VI/O = GND to VCC
CE1 = VIL, CE2 = VIH
II/O = 0mA
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V,
f = 1MHz, II/O = 0mA
PRELIMINARY (March, 2001, Version 0.2) 3 AMIC Technology, Inc.
Page 5
A62S8308 Series
CE1
OE WE
DC Electrical Characteristics (continued)
Symbol Parameter
Min. Max. Min. Max.
ISB- 0.5 - 0.5 mA
ISB1
ISB2- 10 - 15
VOLOutput Low Voltage - 0.4 - 0.4 V IOL = 2.1mA
VOHOutput High Voltage 2.4 - 2.4 - V IOH = -1.0mA
Standby Power
Supply Current
A62S8308-55S/70S A62S8308-55SI/70SI
- 10 - 15
Unit Conditions
CE1 = VIH or
CE2 = VIL
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
µA
VIN≥ 0V
CE2 ≤ 0.2V
µA
VIN≥ 0V
Truth Table
Mode
Standby
H X X X High Z ISB, ISB1
CE2
I/O Operation Supply Current
Output Disable L H H H High Z ICC, ICC1, ICC2
Read L H L H DOUTICC, ICC1, ICC2
Write L H X L DINICC, ICC1, ICC2
Note: X = H or L
X L X X High Z ISB, ISB2
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY (March, 2001, Version 0.2) 4 AMIC Technology, Inc.
Page 6
A62S8308 Series
AC Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.6V)
Symbol Parameter A62S8308-55S/SI
(VCC = 3.0V to 3.6V)
Min. Max. Min. Max.
Read Cycle
tRCRead Cycle Time 55 - 70 - ns
tAAAddress Access Time - 55 - 70 ns
tACE1Chip Enable Access Time
tACE2
tOEOutput Enable to Output Valid - 30 - 35 ns
tCLZ1Chip Enable to Output in Low Z
tCLZ2CE2 10 - 10 - ns
tOLZOutput Enable to Output in Low Z 5 - 5 - ns
tCHZ1Chip Disable to Output in High Z
tCHZ2CE2 0 20 0 25 ns
tOHZOutput Disable to Output in High Z 0 20 0 25 ns
CE1
CE2
CE1
CE1
- 55 - 70 ns
-
10
0 20 0 25 ns
55 - 70 ns
-
A62S8308-70S/SI
(VCC = 2.7V to 3.6V)
10 - ns
Unit
tOHOutput Hold from Address Change 5 - 10 - ns
Read Cycle
tWCWrite Cycle Time 55 - 70 - ns
tCWChip Enable to End of Write 50 - 60 - ns
tASAddress Setup Time 0 - 0 - ns
tAWAddress Valid to End of Write 50 - 60 - ns
tWPWrite Pulse Width 40 - 50 - ns
tWRWrite Recovery Time 0 - 0 - ns
tWHZWrite to Output in High Z 0 25 0 25 ns
tDWData to Write Time Overlap 25 - 30 - ns
tDHData Hold from Write Time 0 - 0 - ns
tOWOutput Active from End of Write 5 - 5 - ns
Notes: tCHZ1, tCHZ2, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY (March, 2001, Version 0.2) 5 AMIC Technology, Inc.
Page 7
A62S8308 Series
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 2
CE1
DOUT
Read Cycle 3
CE2
(1, 3, 4, 6)
(1, 4, 7 ,8)
tACE1
5
tCLZ1
tCHZ1
5
tACE2
5
tCHZ2
DOUT
tCLZ2
5
PRELIMINARY (March, 2001, Version 0.2) 6 AMIC Technology, Inc.
Page 8
A62S8308 Series
Timing Waveforms (continued)
Read Cycle 4
Address
(1)
tRC
tAA
OE
CE1
CE2
DOUT
tCLZ1
tCLZ2
tOE
5
tOLZ
tACE1
5
tACE2
5
tCHZ2
tOH
tCHZ1
5
5
tOHZ
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
PRELIMINARY (March, 2001, Version 0.2) 7 AMIC Technology, Inc.
Page 9
A62S8308 Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
Address
(6)
tWC
CE1
CE2
WE
DIN
DOUT
tAW
5
tCW
(4)
(4)
1
tAS
tWHZ
tWP
2
tWR
tDHtDW
3
tOW
PRELIMINARY (March, 2001, Version 0.2) 8 AMIC Technology, Inc.
Page 10
A62S8308 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
3
CE1
tAWtWR
5
tCW
(4)
1
tAS
CE2
WE
DIN
DOUT
(4)
tWHZ
5
tCW
2
tWP
tDW
7
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1 , a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (March, 2001, Version 0.2) 9 AMIC Technology, Inc.
Page 11
A62S8308 Series
AC Test Conditions
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
TTL
CL
30pF
* Including scope and jig.* Including scope and jig.
CL
TTL
5pF
Figure 1. Output Load Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to + 70°C or -25°C to 85°C)
Symbol Parameter Min. Max. Unit Conditions
VDR12.0 3.6 V
VCC for Data Retention
VDR2
ICCDR1
S-Version - 5*
SI-Version - 10**
2.0 3.6 V
µA
Data Retention Current
CE1 ≥ VCC - 0.2V
CE2 ≤ 0.2V
CE1 ≥ VCC - 0.2V or
CE1 ≤ 0.2V
VCC = 2.0V
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN≥ 0V
ICCDR2
tCDRChip Disable to Data Retention Time 0 - ns
S-Version - 5*
SI-Version - 10**
µA
VCC = 2.0V
CE2 ≤ 0.2V
VIN≥ 0V
See Retention Waveform
tROperation Recovery Time tRC- ns
* A62S8308-55S/70S ICCDR: Max. 1µA at TA = 0°C + 40°C
** A62S8308-55SI/70SI ICCDR: Max. 1µA at TA = 0°C + 40°C
PRELIMINARY (March, 2001, Version 0.2) 10 AMIC Technology, Inc.
Page 12
A62S8308 Series
CE1
Low VCC Data Retention Waveform (1) (
Controlled)
DATA RETENTION MODE
VCC
CE1
2.7V
tCDR
VIH
VDR ≥ 2V
CE1 ≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
2.7V
tCDR
VIL
CE2
VDR ≥ 2V
<
0.2V
2.7V
tR
VIH
2.7V
tR
VIL
PRELIMINARY (March, 2001, Version 0.2) 11 AMIC Technology, Inc.
Page 13
A62S8308 Series
Ordering Information
Part No. Access Time
(ns)
A62S8308M-55S 40 10 32L SOP
A62S8308M-55SI
A62S8308V-55S 40 10 32L TSOP
A62S8308V-55SI
A62S8308X-55S 40 10 32L sTSOP
A62S8308X-55SI 40 15 32L sTSOP
A62S8308G-55S 40 10 36B Mini BGA
A62S8308G-55SI 40 15 36B Mini BGA
A62S8308M-70S 40 10 32L SOP
A62S8308M-70SI
A62S8308V-70S 40 10 32L TSOP
55
Operating Current
Max. (mA)
40 15 32L SOP
40 15 32L TSOP
40 15 32L SOP
Standby Current
Max. (µµA)
Package
A62S8308V-70SI
A62S8308X-70S 40 10 32L sTSOP
A62S8308X-70SI 40 15 32L sTSOP
A62S8308G-70S 40 10 36B Mini BGA
A62S8308G-70SI 40 15 36B Mini BGA
70
40 15 32L TSOP
PRELIMINARY (March, 2001, Version 0.2) 12 AMIC Technology, Inc.
Page 14
A62S8308 Series
D
Package Information
SOP (W.B.) 32L Outline Dimensions unit: inches/mm