1.1 Modify 28-pin DIP, SOP and TSOP packages outline January 20, 1998 dimensions.
1.2 Modify 28-pin SOP and TSOP packages outline drawings June 17, 1998 and dimensions
1.3 Add -LLU type April 11, 2001 Change operating voltage Vccmax from 3.3V to 3.6V
1.4 Add Product Family in page 1 November 30, 2001 Delete ICC item Add ICC2(typ.) ICCDR(typ.) Change ISB1(typ.) ICCDR(max.) Change ordering information from ICC1 to ICC2
PRELIMINARY (November, 2001, Version 1.4) AMIC Technology, Inc.
A62L256 Series
Preliminary32K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n External Operating Voltage: 2.7V to 3.6V
n Access times: 55ns (max.): for VCC = 3.0V to 3.6V
70ns (max.): for VCC = 2.7V to 3.6V
n Current: Operating (ICC1): -55 series 18mA (typ.)
-70 series 12mA (typ.)
Standby (ISB1): 0.05µA (typ.)
n Extended operating temperature range: -40ºC to
+85ºC for -LLU series
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
General Description
The A62L256 is a low operating current 262,144-bit static
random access memory organized as 32,768 words by 8
bits and operates on a low power voltage: 2.7V to 3.6V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when
CE is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
n Data retention voltage: 2.0V (min.)
n Available in 28-pin DIP, SOP and TSOP (forward and
reverse type) packages
Product Family
Power Dissipation
Product Family
A62L256
Operating
Temperature
-40°C ~ +85°C
VCC
Range
Speed
2.7V~3.6V 55ns / 70ns
Data Retention
(ICCDR, Typ.)
0.02µA 0.05µA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
DC Electrical Characteristics (TA = 0°C to + 70°C or -40ºC to +85ºC, VCC = 2.7V to 3.6V, GND = 0V)
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Symbol Parameter
Min. Typ. Max. Min. Typ. Max.
ILI
ILO
ICC1
ICC2
Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
* Testing condition : TA = 25°C, VCC = 3.0V, Cycle Time = 55 ns
** Testing condition : TA = 25°C, VCC = 3.0V, Cycle Time = 70 ns
Input Leakage
Current
Output Leakage
Current
Dynamic
Operating Current
Dynamic
Operating Current
A62L256-55LL/55LLU A62L256-70LL/70LLU
- - 1 - - 1
- - 1 - - 1
- *18 25 - **12 20 mA
-
1
3
-
1
3
Unit Conditions
VIN = GND to VCC
µA
µA
VI/O = GND to VCC
Min. Cycle, Duty = 100%
mA
VIL = 0V, f = 1 MHz
II/O = 0 mA
CE = VIH or WE = VIL
CE = VIL, II/O = 0mA
CE = VIL, VIH = VCC
PRELIMINARY (November, 2001, Version 1.4) 4AMIC Technology, Inc.
A62L256 Series
CE OE WE
DC Electrical Characteristics (continued)
Symbol Parameter
Min. Typ. Max. Min. Typ. Max.
ISB
ISB1
VOLOutput Low
VOHOutput High
Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
Supply Current
Standby Power
Voltage
Voltage
A62L256-55LL/70LL A62L256-55LLU/70LLU
- - 50 - - 50
- 0.05 2 - 0.05 5
- - 0.3 - - 0.3 V IOL = 2.1mA
VCC - 0.3 - - VCC - 0.3 - - V IOH = -1.0mA
Unit Conditions
µA
µA
CE = VIH
CE ≥ VCC - 0.2V
VIN≥ 0V
Truth Table
Mode
Standby H X X High Z ISB, ISB1
Output Disable L H H High Z ICC, ICC1, ICC2
I/O Operation Supply Current
Read L L H DOUTICC, ICC1, ICC2
Write L X L DINICC, ICC1, ICC2
Note: X: H or L
Capacitance (TA = 25°C, f = 1.0 MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
These parameters are sampled and not 100% tested.
PRELIMINARY (November, 2001, Version 1.4) 5AMIC Technology, Inc.
A62L256 Series
AC Characteristics (TA = 0°C to +70°C or -40ºC to +85ºC)
A62L256-55LL/LLU
Symbol Parameter
Min. Max. Min. Max.
Read Cycle
tRCRead Cycle Time 55 - 70 - ns
tAAAddress Access Time - 55 - 70 ns
tACEChip Enable Access Time - 55 - 70 ns
tOEOutput Enable to Output Valid - 30 - 35 ns
tCLZChip Enable to Output in Low Z 10 - 10 - ns
tOLZOutput Enable to Output in Low Z 5 - 5 - ns
tCHZChip Disable to Output in High Z - 20 - 25 ns
tOHZOutput Disable to Output in High Z - 20 - 25 ns
tOHOutput Hold from Address Change 5 - 10 - ns
(VCC = 3.0V to 3.6V)
A62L256-70LL/LLU
(VCC = 2.7V to 3.6V)
Unit
Write Cycle
tWCWrite Cycle Time 55 - 70 - ns
tCWChip Enable to End of Write 50 - 60 - ns
tASAddress Set up Time 0 - 0 - ns
tAWAddress Valid to End of Write 50 - 60 - ns
tWPWrite Pulse Width 40 - 50 - ns
tWRWrite Recovery Time 0 - 0 - ns
tWHZWrite to Output in High Z - 25 - 25 ns
tDWData to Write Time Overlap 25 - 30 - ns
tDHData Hold from Write Time 0 - 0 - ns
tOWOutput Active from End of Write 5 - 5 - ns
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
PRELIMINARY (November, 2001, Version 1.4) 6AMIC Technology, Inc.
A62L256 Series
Timing Waveforms
Read Cycle 1
(1)
tRC
Address
tAA
OE
DOUT
Read Cycle 2
Address
DOUT
CE
(1, 2, 4)
tCLZ
tOE
5
OLZ
t
tACE
5
tCHZ
tOH
5
tOHZ
5
tRC
tAA
tOH
tOH
PRELIMINARY (November, 2001, Version 1.4) 7AMIC Technology, Inc.
A62L256 Series
Timing Waveforms (continued)
Read Cycle 3
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Write Cycle 1
(Write Enable Controlled)
CE
DOUT
(1, 3, 4)
(6)
tCLZ
tACE
5
tCHZ
5
Address
CE
WE
DOUT
DIN
tWC
tAW
5
tCW
(4)
1
tAS
tWHZ
2
tWP
7
tWR
3
tDHtDW
7
tOW
PRELIMINARY (November, 2001, Version 1.4) 8AMIC Technology, Inc.
A62L256 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
Address
CE
WE
(6)
tWC
tAWtWR
5
tCW
(4)
1
tAS
2
tWP
3
DIN
DOUT
tWHZ
tDW
7
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE.
3. tWR is measured form the earliest of CE or WE going high to the end of the Write cycle.
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE level is high or low.
7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested.
PRELIMINARY (November, 2001, Version 1.4) 9AMIC Technology, Inc.
A62L256 Series
AC Test Conditions
Input Pulse Levels 0V, VCC
Input Rise And Fall Time 5 ns
Input and Output Timing Reference Levels VCC/2
Output Load See Figure 1
CL
30pF
* Including scope and jig.
Figure 1. Output Load
Data Retention Characteristics (TA = 0°C to 70°C or -40ºC to +85ºC)
Symbol Parameter Min. Typ. Max. Unit Conditions
VDRVCC for Data Retention 2.0 - 3.6 V
ICCDR Data Retention Current
LL-version
-
0.02 0.5
µA
LLU-version - 0.02 2
tCDRChip Disable to Data Retention Time 0 - ns
CE ≥ VCC - 0.2V
VCC = 2V,
CE ≥ VCC - 0.2V
VIN≥ 0V
See Retention Waveform
tROperation Recovery Time tRC- ns
Typical values are measured at TA = 25°C.
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
tCDR
VCC ≥ 2.0V
3.0V
tR
CE
VIH
CE ≥ VCC - 0.2V
VIH
PRELIMINARY (November, 2001, Version 1.4) 10AMIC Technology, Inc.
A62L256 Series
Ordering Information
Part No. Access Time (ns)
A62L256-55LL 3 2 28L DIP
A62L256M-55LL
A62L256V-55LL 3 2 28L TSOP (Forward)
A62L256R-55LL 3 2 28L TSOP (Reverse)
A62L256-70LL 3 2 28L DIP
A62L256M-70LL
A62L256V-70LL 3 2 28L TSOP (Forward)
A62L256R-70LL 3 2 28L TSOP (Reverse)
A62L256-55LLU 3 5 28L DIP
A62L256M-55LLU
A62L256V-55LLU 3 5 28L TSOP (Forward)
A62L256R-55LLU 3 5 28L TSOP (Reverse)
55
70
55
Operating Current (ICC2)
Max. (mA)
3 2 28L SOP
3 2 28L SOP
3 5 28L SOP
Standby Current (ISB1)
Max. (µA)
Package
A62L256-70LLU 3 5 28L DIP
A62L256M-70LLU
A62L256V-70LLU 3 5 28L TSOP (Forward)
A62L256R-70LLU 3 5 28L TSOP (Reverse)
70
3 5 28L SOP
PRELIMINARY (November, 2001, Version 1.4) 11AMIC Technology, Inc.