Datasheet A6273KLW, A6273KA Datasheet (Allegro)

6273

Data Sheet

26180.120

ADVANCE INFORMATION

(Subject to change without notice)

January 24, 2000

LOGIC

1

CLEAR

2

IN

1

3

IN

2

OUT

4

1

OUT

5

2

6

OUT

OUT

IN

IN

GROUND

3

7

4

8

3

9

4

10

LATCHES

Note that the A6273KA (DIP) and the A6273KLW
(SOIC) are electrically identical and share a com­mon terminal number assignment.

V

DD

LATCHES

20

19

18

17

16

15

14

13

12

11

SUPPLY

IN

8

IN

7

OUT

8

OUT

7

OUT

6

OUT

5

IN

6

IN

5

STROBE

Dwg. PP-015-2

8-BIT LATCHED

DMOS POWER DRIVER

The A6273KA and A6273KLW combine eight (positive-edge­triggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, sole­noids, and other medium-current or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with microproces­sor-based systems. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.

The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6273KA/KLW DMOS open-drain outputs are
capable of sinking up to 750 mA. Similar devices with reduced r
will be available as the A6A273.

The A6273KA is furnished in a 20-pin dual in-line plastic package.
The A6273KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applica­tions. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85°C.

DS(on)

ABSOLUTE MAXIMUM RATINGS

at TA = 25°C

Output Voltage, VO............................. 50 V

Output Drain Current,

Continuous, IO....................... 250 mA*

Peak, IOM.............................. 750 mA*†

Peak, IOM..................................... 2.0 A†

Single-Pulse Avalanche Energy,

EAS.............................................. 75 mJ

Logic Supply Voltage, VDD................ 7.0 V

Input Voltage Range,

VI................................. -0.3 V to +7.0 V

Package Power Dissipation,

PD........................................ See Graph

Operating Temperature Range,

TA.............................. -40°C to +125°C

Storage Temperature Range,

TS.............................. -55°C to +150°C

* Each output, all outputs on.

† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.

Caution: These CMOS devices have input
static protection (Class 3) but are still
susceptible to damage if exposed to extremely
high static electrical charges.

FEATURES

■ 50 V Minimum Output Clamp Voltage

■ 250 mA Output Current (all outputs simultaneously)

■ 1.3 Ω Typical

■ Low Power Consumption

■ Replacements for TPIC6273N and TPIC6273DW

Always order by complete part number:

Part Number Package R

A6273KA 20-pin DIP 55°C/W 25°C/W

A6273KLW 20-lead SOIC 70°C/W 17°C/W

r

DS(on)

θJA

R

θJC

6273

g

8-BIT LATCHED
DMOS POWER DRIVER

2.5

2.0

S

U

F

F

IX

'A

', R

θJA

=

θJA

5

5

°C/W

°C

/W

Dwg. GS-004A

V

DD

1.5

1.0

0.5

0

25

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

SUFFIX 'LW', R = 70

50 75 100 125 150

AMBIENT TEMPERATURE IN °C

IN

LOGIC SYMBOL

1

11

2

3

18

R

C1

1D 4

1D

1D8

1D9

1D12

1D13

1D

1D19

. FP-046-1

Dw

5

6

7

14

15

16

17

OUT

Dwg. EP-010-16

Dwg. EP-063

DMOS POWER DRIVER OUTPUTLOGIC INPUTS

FUNCTION TABLE

Inputs

CLEAR STROBE IN

X

LXXH

HHL

HLH
HLXR

L = Low Logic Level
H = High Logic Level
X = Irrelevant
R = Previous State

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 2000, Allegro MicroSystems, Inc.

OUT

X

FUNCTIONAL BLOCK DIAGRAM

6273

8-BIT LATCHED

DMOS POWER DRIVER

IN

STROBE

IN

LOGIC

SUPPLY

IN

IN

IN

1

D

OUT

1

C1

CLR

2

D

OUT

2

C1

V

DD

3

CLR

D

OUT

3

C1

CLR

4

D

OUT

4

C1

CLR

5

D

OUT

5

C1

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IN

IN

IN

CLEAR

(ACTIVE LOW)

CLR

6

D

OUT

6

C1

CLR

7

D

OUT

7

C1

CLR

8

D

OUT

8

C1

CLR

GROUND

Dwg. FP-016-2

6273

8-BIT LATCHED
DMOS POWER DRIVER

RECOMMENDED OPERATING CONDITIONS

over operating temperature range

Logic Supply Voltage Range, VDD............... 4.5 V to 5.5 V

High-Level Input Voltage, VIH............................ ≥ 0.85V

Low-level input voltage, VIL................................. ≤0.15V

ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).

Characteristic Symbol Test Conditions Min. Typ. Max. Units

Logic Supply Voltage V

DD

Operating 4.5 5.0 5.5 V

DD

DD

Limits

Output Breakdown V

(BR)DSXIO

Voltage

Off-State Output I
Current

Static Drain-Source r

DS(on)

On-State Resistance

Nominal Output I

O(nom)

Current

Logic Input Current I

Prop. Delay Time t

t

Output Rise Time t

Output Fall Time t

Supply Current I

DD(off)

DSX

IH

I

IL

PLH

PHL

r

f

= 1 mA 50 — — V

VO = 40 V — 0.05 1.0 µA

VO = 40 V TA = 125°C — 0.15 5.0 µA

IO = 250 mA, VDD = 4.5 V — 1.3 2.0 Ω

IO = 250 mA, VDD = 4.5 V, TA = 125°C— 2.0 3.2 Ω

IO = 500 mA, VDD = 4.5 V (see note) — 1.3 2.0 Ω

V

= 0.5 V, TA = 85°C — 250 — mA

DS(on)

VI = VDD = 5.5 V — — 1.0 µA

VI = 0, VDD = 5.5 V — — -1.0 µA

IO = 250 mA, CL = 30 pF — 625 — ns

IO = 250 mA, CL = 30 pF — 150 — ns

IO = 250 mA, CL = 30 pF — 675 — ns

IO = 250 mA, CL = 30 pF — 400 — ns

VDD = 5.5 V, Outputs OFF — 15 100 µA

I

DD(on)

VDD = 5.5 V, Outputs ON — 150 300 µA

Typical Data is at VDD = 5 V and is for design information only.

NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

TIMING REQUIREMENTS

6273

8-BIT LATCHED

DMOS POWER DRIVER

INx

STROBE

OUTPUTx

t

t

PHL

50%

su(D)

t

su(D)

50%

t

50%

t

PLH

h(D)

10%

t

r

Input Active Time Before Strobe

(Data Set-Up Time), t

.............................................. 20 ns

su(D)

Input Active Time After Strobe

(Data Hold Time), t

Input Pulse Width, t

................................................... 20 ns

h(D)

...................................................... 40 ns

w(D)

Input Logic High, VIH................................................ ≥ 0.85V

Input Logic Low, VIL................................................. ≤ 0.15V

DD

DD

t

h(D)

90%

t

f

Dwg. WP-036-1

www.allegromicro.com

6273

8-BIT LATCHED
DMOS POWER DRIVER

TEST CIRCUITS

INPUT

I

O

V

O

t

av

IAS = 1.0 A

V

(BR)DSX

V

O(ON)

EAS = IAS x V

(BR)DSX

DUT

x tAV/2

+15 V

0.11 Ω

100 mH

OUT

Dwg. EP-066-1

Single-Pulse Avalanche Energy Test Circuit

and Waveforms

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

TERMINAL DESCRIPTIONS

Terminal No. Terminal Name Function

6273

8-BIT LATCHED

DMOS POWER DRIVER

1 CLEAR

2 IN

1

When (active) LOW, all latches are reset and all outputs go HIGH (turn OFF).

CMOS data input to a latch. When strobed, the output then inverts the data
input (IN1 = HIGH, OUT1 = LOW).

3

IN

2

CMOS data input to a latch. When strobed, the output then inverts the data
input (IN2 = HIGH, OUT2 = LOW).

4 OUT

5 OUT

6 OUT

7 OUT

8

IN

1

2

3

4

3

Current-sinking, open-drain DMOS output.

Current-sinking, open-drain DMOS output.

Current-sinking, open-drain DMOS output.

Current-sinking, open-drain DMOS output.

CMOS data input to a latch. When strobed, the output then inverts the data
input (IN3 = HIGH, OUT3 = LOW).

9

IN

4

CMOS data input to a latch. When strobed, the output then inverts the data
input (IN4 = HIGH, OUT4 = LOW).

10 GROUND Reference terminal for all voltage measurements.

11 STROBE A CMOS dynamic input to all latches. Data on each INx terminal is loaded

into its associated latch on a low-to-high STROBE transition.

12

IN

5

CMOS data input to a latch. When strobed, the output then inverts the data
input (IN5 = HIGH, OUT5 = LOW).

13

IN

6

CMOS data input to a latch. When strobed, the output then inverts the data
input (IN6 = HIGH, OUT6 = LOW).

14 OUT

15 OUT

16 OUT

17 OUT

18

IN

5

6

7

8

7

Current-sinking, open-drain DMOS output.

Current-sinking, open-drain DMOS output.

Current-sinking, open-drain DMOS output.

Current-sinking, open-drain DMOS output.

CMOS data input to a latch. When strobed, the output then inverts the data
input (IN7 = HIGH, OUT7 = LOW).

19

IN

8

CMOS data input to a latch. When strobed, the output then inverts the data
input (IN8 = HIGH, OUT8 = LOW).

20 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).

www.allegromicro.com

6273

8-BIT LATCHED
DMOS POWER DRIVER

20

0.280

0.240

A6273KA

Dimensions in Inches

(controlling dimensions)

11

0.014

0.008

0.300

BSC

0.430

MAX

0.210

MAX

7.11

6.10

0.015

MIN

1

0.070

0.045

0.022

0.014

1.060

0.980

0.100

BSC

10

0.005

MIN

0.150

0.115

Dwg. MA-001-20 in

Dimensions in Millimeters

(for reference only)

0.355

20

1

1.77

1.15

26.92

24.89

2.54

BSC

11

10

0.13

MIN

0.204

7.62

BSC

10.92

MAX

5.33

MAX

0.39

MIN

0.558

0.356

3.81

2.93

NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Dwg. MA-001-20 mm

A6273KLW

Dimensions in Inches

(for reference only)

6273

8-BIT LATCHED

DMOS POWER DRIVER

20 11

0.2992

0.2914

0.020

1 2

0.013

0.0926

0.1043

0.0040

3

MIN.

20

0.050

0.5118

0.4961

BSC

Dimensions in Millimeters

(controlling dimensions)

11

0.419

0.394

0° TO 8°

0.0125

0.0091

0.050

0.016

Dwg. MA-008-20 in

0.32

0.23

7.60

7.40

0.51

0.33

2.65

2.35

1

0.10

2

MIN.

3

13.00

12.60

1.27

BSC

10.65

10.00

0° TO 8°

NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

www.allegromicro.com

1.27

0.40

Dwg. MA-008-20 mm

6273

8-BIT LATCHED
DMOS POWER DRIVER

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi­bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]