The A625308A is a low operating current 262,144-bit
static random access memory organized as 32,768
words by 8 bits and operates on a voltage from 4.5V to
5.5V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
n DIP / SOP n TSOP
n Extended operating temperature range: 0°C to 70°C
for -S series, -25°C to 85°C for -SI series, -40°C to
85°C for -SU series.
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2.0V (min.)
n Available in 28-pin, DIP/SOP and TSOP
Minimum standby power is drawn by this device when
CE is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
A14
A12
I/O0
I/O1
I/O
GND
A7
A6
A5
A4
A3
A2
A1
A0
2
1
2
3
4
A625308A(M)
5
6
7
8
9
10
11
12
13
1415
~
VCC
28
WE
27
A13
26
A8
25
A9
24
A11
23
OE
22
A10
21
CE
20
I/O7
19
I/O6
18
I/O5
17
I/O4
16
3
I/O
A11
A13
WE
VCC
A14
A12
1
OE
2
3
A9
4
A8
5
6
7
8
9
10
A7
11
A6
12
A5
13
A4
14
A3
~
A625308AV
~
~
28
A10
CE
27
26
I/O7
25
I/O6
I/O5
24
23
I/O4
22
I/O3
21
VSS
20
19
18
17
16
15
2
I/O
1
I/O
0
I/O
A0
A1
A2
PRELIMINARY (July, 2002, Version 0.2) 1 AMIC Technology, Inc.
DC Electrical Characteristics (TA = 0°C to +70°C, -25°C to +85°C or -40°C to +85°C, VCC = 5.0V ± 10%, GND = 0V)
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Symbol Parameter
Min. Max.
ILI
ILO
ICCActive Power Supply Current - 5 mA
ICC1Dynamic Operating Current - 35 mA
ICC2
Input Leakage Current - 1
Output Leakage Current - 1
Dynamic Operating Current
A625308A-70S/SI/SU
-
Unit Conditions
µA
µA
5
mA
VIN = GND to VCC
CE = VIH
VI/O = GND to VCC
CE = VIL, II/O = 0mA
Min. Cycle, Duty = 100%
CE = VIL, II/O = 0mA
CE = VIL, VIH = VCC
VIL = 0V, f = 1 MHz
II/O = 0 mA
PRELIMINARY (July, 2002, Version 0.2) 3 AMIC Technology, Inc.
Page 5
A625308A Series
CE OE WE
DC Electrical Characteristics (continued)
Symbol Parameter
Min. Max. Min. Max.
ISB
ISB1
VOLOutput Low Voltage - 0.4 - 0.4 V IOL = 2.1 mA
VOHOutput High Voltage 2.4 - 2.4 - V IOH = -1.0 mA
Supply Current
Standby Power
A625308A-70S A625308A-70SI/SU
- 0.5 - 0.5 mA
- 10 - 15
Unit Conditions
CE = VIH
µA
CE ≥ VCC - 0.2V
VIN≥ 0V
Truth Table
Mode
Standby H X X High Z ISB, ISB1
Output Disable L H H High Z ICC, ICC1, ICC2
Read L L H DOUTICC, ICC1, ICC2
Write L X L DINICC, ICC1, ICC2
I/O Operation Supply Current
Note: X: H or L
Capacitance (TA = 25°C, f = 1.0 MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 6 pF VIN = 0V
CI/O* Input/Output Capacitance - 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY (July, 2002, Version 0.2) 4 AMIC Technology, Inc.
Page 6
A625308A Series
AC Characteristics (TA = 0°C to +70°C, -25°C to +85°C or -40°C to +85°C, VCC = 5.0V ± 10%)
Symbol Parameter
Min. Max.
Read Cycle
tRCRead Cycle Time 70 - ns
tAAAddress Access Time - 70 ns
tACEChip Enable Access Time - 70 ns
tOEOutput Enable to Output Valid - 35 ns
tCLZChip Enable to Output in Low Z 10 - ns
tOLZOutput Enable to Output in Low Z 5 - ns
tCHZChip Disable to Output in High Z - 25 ns
tOHZOutput Disable to Output in High Z - 25 ns
tOHOutput Hold from Address Change 10 - ns
Write Cycle
A625308A-70S/SI/SU
Unit
tWCWrite Cycle Time 70 - ns
tCWChip Enable to End of Write 60 - ns
tASAddress Set up Time 0 - ns
tAWAddress Valid to End of Write 60 - ns
tWPWrite Pulse Width 50 - ns
tWRWrite Recovery Time 0 - ns
tWHZWrite to Output in High Z - 25 ns
tDWData to Write Time Overlap 30 - ns
tDHData Hold from Write Time 0 - ns
tOWOutput Active from End of Write 5 - ns
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
PRELIMINARY (July, 2002, Version 0.2) 5 AMIC Technology, Inc.
Page 7
A625308A Series
Timing Waveforms
Read Cycle 1
(1)
tRC
Address
tAA
OE
DOUT
Read Cycle 2
Address
DOUT
CE
(1, 2, 4)
tCLZ
tOE
5
OLZ
t
tACE
5
tCHZ
tOH
5
tOHZ
5
tRC
tAA
tOH
tOH
PRELIMINARY (July, 2002, Version 0.2) 6 AMIC Technology, Inc.
Page 8
A625308A Series
Timing Waveforms (continued)
Read Cycle 3
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Write Cycle 1
(Write Enable Controlled)
CE
DOUT
(1, 3, 4)
(6)
tCLZ
tACE
5
tCHZ
5
Address
CE
WE
DOUT
DIN
tWC
tAW
5
tCW
(4)
1
tAS
tWHZ
2
tWP
7
tWR
3
tDHtDW
7
tOW
PRELIMINARY (July, 2002, Version 0.2) 7 AMIC Technology, Inc.
Page 9
A625308A Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
Address
CE
WE
(6)
tWC
tAWtWR
5
tCW
(4)
1
tAS
2
tWP
3
DOUT
DIN
tWHZ
tDW
7
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE.
3. tWR is measured form the earliest of CE or WE going high to the end of the Write cycle.
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE level is high or low.
7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested.
PRELIMINARY (July, 2002, Version 0.2) 8 AMIC Technology, Inc.
Page 10
A625308A Series
AC Test Conditions
Input Pulse Levels 0V, 3V
Input Rise And Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figure 1 and 2
TTL
CL
30pF
* Including scope and jig.* Including scope and jig.
CL
TTL
5pF
Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to +70°C, -25°C to +85°C or -40°C to +85°C)
Symbol Parameter Min. Max. Unit Conditions
VDRVCC for Data Retention 2.0 5.5 V
ICCDR
Data Retention Current
-
3
tCDRChip Disable to Data Retention Time 0 - ns
tROperation Recovery Time tRC- ns
CE ≥ VCC - 0.2V
VCC = 2.0V,
µA
CE ≥ VCC - 0.2V
VIN≥ 0V
See Retention Waveform
PRELIMINARY (July, 2002, Version 0.2) 9 AMIC Technology, Inc.
Page 11
A625308A Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
tCDR
VDR ≥ 2.0V
4.5V
tR
CE
VIH
CE ≥ VDR - 0.2V
VIH
Ordering Information
Part No. Access Time (ns)
Operating Current
Max. (mA)
A625308A-70S 35 10 28L DIP
A625308AM-70S 35 10 28L SOP
A625308AV-70S 35 10 28L TSOP (Forward)
A625308A-70SI 35 15 28L DIP
A625308AM-70SI 35 15 28L SOP
70
A625308AV-70SI 35 15 28L TSOP (Forward)
A625308A-70SU 35 15 28L DIP
Standby Current
Max. (µA)
Package
A625308AM-70SU 35 15 28L SOP
A625308AV-70SU
35 15 28L TSOP (Forward)
PRELIMINARY (July, 2002, Version 0.2) 10 AMIC Technology, Inc.