The A623308A is a low operating current 65,536-bit static
random access memory organized as 8,192 words by 8 bits
and operates on a voltage from 4.5V to 5.5V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
DIP / SOP TSOP
Extended operating temperature range: 0°C to 70°C for -
S series, -25°C to 85°C for -SI series, -40°C to 85°C for
-SU series.
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Data retention voltage: 2.0V (min.)
Available in 28-pin, DIP/SOP and TSOP
Pb-Free package only
All Pb-free (Lead-free) products are RoHS compliant
Minimum standby power is drawn by this device when
is at a high level, independent of the other input levels.
Data retention is guaranteed at a power supply voltage as
low as 2.0V.
CE
A12
I/O
I/O1
I/O2
GND
NC
A7
A6
A5
A4
A3
A2
A1
A0
0
1
2
3
4
5
A623308A(M)
6
7
8
9
10
11
12
13
1415
~
VCC
28
WE
27
NC
26
A8
25
A9
24
A11
23
OE
22
A10
21
CE
20
I/O7
19
18
I/O6
I/O5
17
16
I/O4
3
I/O
A11
VCC
A12
WE
1
OE
2
3
A9
4
A8
5
NC
6
7
8
NC
9
10
A7
11
A6
12
A5
13
A4
A3
14
~
A623308AV
~
~
A10
28
CE
27
I/O
26
25
24
23
22
21
20
19
18
17
16
15
I/O
I/O5
I/O4
I/O3
VSS
I/O
I/O1
I/O0
A0
A1
A2
7
6
2
(July, 2006, Version 1.0) 1 AMIC Technology, Corp.
Page 3
A623308A Series
Block Diagram
A0
A10
A11
A12
I/O0
I/O7
CE
OE
WE
CONTROL
CIRCUIT
Pin Descriptions – DIP / SOP
VCC
GND
ROW
DECODER
INPUT DATA
CIRCUIT
128 X 512
MEMORY ARRAY
COLUMN I/O
Pin Description-TSOP
Pin No. Symbol Description
1, 26 NC No Connection
2-10, 21, 23-25 A0 - A12 Address Input
11-13, 15-19 I/O0 - I/O7 Data Input/Output
20
22
27
CE
OE
WE
Chip Enable
Output Enable
Write Enable
28 VCC Power Supply
14 GND Ground
Pin No. Symbol Description
5, 8 NC No Connection
2-4, 9-17, 28 A0 - A12 Address Input
18-20, 22-26 I/O0 - I/O7 Data Input/Output
27
1
6
CE
OE
WE
Chip Enable
Output Enable
Write Enable
7 VCC Power Supply
21 GND Ground
(July, 2006, Version 1.0) 2 AMIC Technology, Corp.
Page 4
A623308A Series
Recommended DC Operating Conditions
A = 0°C to +70°C, -25°C to +85°C or -40°C to +85°C)
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied and exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DC Electrical Characteristics (TA = 0°C to +70°C, -25°C to +85°C or -40°C to +85°C, VCC = 5.0V ± 10%, GND = 0V)
Symbol Parameter
Min. Max. Min. Max.
⏐ILI⏐
⏐ILO⏐
Input Leakage Current - 1 - 1
Output Leakage Current - 1 - 1
ICCActive Power Supply
Current
ICC1
CC2
I
ISB
Dynamic Operating
Current
Dynamic Operating
Current
Supply Current
Standby Power
ISB1
A623308A-70S A623308A-70SI/SU
Unit Conditions
µA
µA
- 5 - 5 mA
- 35 - 35 mA
-
5
-
5
mA
- 0.5 - 0.5 mA
- 10 - 15
µA
IN = GND to VCC
V
CE
V
IH
= V
I/O = GND to VCC
CE = VIL, II/O = 0mA
Min. Cycle, Duty = 100%
CE
CE
V
I
IL, II/O = 0mA
= V
IL, VIH = VCC
= V
IL = 0V, f = 1 MHz
I/O = 0 mA
CE = VIH
CE ≥ VCC - 0.2V
IN ≥ 0V
V
VOLOutput Low Voltage - 0.4 - 0.4 V IOL = 2.1 mA
VOHOutput High Voltage 2.4 - 2.4 - V IOH = -1.0 mA
(July, 2006, Version 1.0) 3 AMIC Technology, Corp.
Page 5
A623308A Series
Truth Table
Mode
Standby H X X High Z ISB, ISB1
Output Disable L H H High Z ICC, ICC1, ICC2
Read L L H DOUT ICC, ICC1, ICC2
Write L X L DIN ICC, ICC1, ICC2
Note: X: H or L
CE OE WE
I/O Operation Supply Current
Capacitance (TA = 25°C, f = 1.0 MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 6 pF VIN = 0V
CI/O* Input/Output Capacitance - 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
(July, 2006, Version 1.0) 4 AMIC Technology, Corp.
Page 6
A623308A Series
AC Characteristics (TA = 0°C to +70°C, -25°C to +85°C or -40°C to +85°C, VCC = 5.0V ± 10%)
Symbol Parameter
Min. Max.
Read Cycle
tRCRead Cycle Time 70 - ns
tAAAddress Access Time - 70 ns
tACEChip Enable Access Time - 70 ns
tOEOutput Enable to Output Valid - 35 ns
tCLZChip Enable to Output in Low Z 10 - ns
tOLZOutput Enable to Output in Low Z 5 - ns
tCHZChip Disable to Output in High Z - 25 ns
tOHZOutput Disable to Output in High Z - 25 ns
tOHOutput Hold from Address Change 10 - ns
Write Cycle
A623308A-70S/SI/SU
Unit
tWCWrite Cycle Time 70 - ns
tCWChip Enable to End of Write 60 - ns
tASAddress Set up Time 0 - ns
tAWAddress Valid to End of Write 60 - ns
tWPWrite Pulse Width 50 - ns
tWRWrite Recovery Time 0 - ns
tWHZWrite to Output in High Z - 25 ns
tDWData to Write Time Overlap 30 - ns
tDHData Hold from Write Time 0 - ns
tOWOutput Active from End of Write 5 - ns
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
(July, 2006, Version 1.0) 5 AMIC Technology, Corp.
Page 7
A623308A Series
Timing Waveforms
Read Cycle 1
Address
OE
CE
D
OUT
(1)
t
RC
t
AA
t
OE
5
t
OLZ
t
ACE
5
t
CLZ
t
OH
5
t
OHZ
5
t
CHZ
Read Cycle 2
Address
OUT
D
(1, 2, 4)
t
RC
t
AA
t
t
OH
OH
(July, 2006, Version 1.0) 6 AMIC Technology, Corp.
Page 8
A623308A Series
Timing Waveforms (continued)
Read Cycle 3
Notes: 1.
2. Device is continuously enabled,
3. Address valid prior to or coincident with
4.
5. Transition is measured
Write Cycle 1
(Write Enable Controlled)
(1, 3, 4)
CE
t
D
OUT
WE is high for Read Cycle.
OE = VIL.
±500mV from steady state. This parameter is sampled and not 100% tested.
(6)
CLZ
5
t
ACE
CE = VIL.
CE transition low.
5
t
CHZ
Address
WE
D
CE
D
OUT
t
WC
t
AW
5
t
CW
(4)
1
t
AS
IN
t
WHZ
2
t
WP
t
DW
7
3
t
WR
t
DH
7
t
OW
(July, 2006, Version 1.0) 7 AMIC Technology, Corp.
Page 9
A623308A Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
Address
CE
WE
D
D
OUT
Notes: 1. t
2. A Write occurs during the overlap (t
3. t
4. If the
remain in a high impedance state.
5. t
6.
7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested.
(6)
t
WC
t
AW
5
t
CW
(4)
1
t
AS
2
t
WP
t
DW
IN
7
t
WHZ
AS is measured from the address valid to the beginning of Write.
WP) of a low CE and a low WE.
WR is measured form the earliest of CE or WE going high to the end of the Write cycle.
CE
low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
CW is measured from the later of
CE
going low to the end of Write.
3
t
WR
t
DH
OE level is high or low.
(July, 2006, Version 1.0) 8 AMIC Technology, Corp.
Page 10
A623308A Series
AC Test Conditions
Input Pulse Levels 0V, 3V
Input Rise And Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figure 1 and 2
TTL
C
L
30pF
* Including scope and jig.
C
TTL
L
5pF
* Including scope and jig.
Figure 1. Output Load Figure 2. Output Load for t
t
t
CLZ2, tOHZ, tOLZ, tCHZ1,
CHZ2, tWHZ, and tOW
CLZ1,
Data Retention Characteristics
Symbol Parameter Min. Max. UnitConditions
VDRVCC for Data Retention 2.0 5.5 V
CCDR
I
tCDRChip Disable to Data Retention Time 0 - ns
tROperation Recovery Time tRC - ns
Data Retention Current
(TA = 0°C to +70°C, -25°C to +85°C or -40°C to +85°C)
-
3
A
µ
CE ≥ VCC - 0.2V
VCC = 2.0V,
CE
≥ VCC - 0.2V
VIN≥ 0V
See Retention Waveform
(July, 2006, Version 1.0) 9 AMIC Technology, Corp.
Page 11
A623308A Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
CE
4.5V
t
CDR
V
IH
V
DR
≥ 2.0V
4.5V
t
R
V
IH
CE ≥ VDR - 0.2V
Ordering Information
Part No. Access Time (ns)
A623308A-70SF 35 10 28L Pb-Free DIP
A623308AM-70SF 35 10 28L Pb-Free SOP
A623308AV-70SF 35 10 28L Pb-Free TSOP (Forward)
A623308A-70SIF 35 15 28L Pb-Free DIP
A623308AM-70SIF 35 15 28L Pb-Free SOP
A623308AV-70SIF 35 15 28L Pb-Free TSOP (Forward)
A623308A-70SUF 35 15 28L Pb-Free DIP
A623308AM-70SUF 35 15 28L Pb-Free SOP
Operating Current
Max. (mA)
Standby Current
Max. (
µA)
Package
70
A623308AV-70SUF
35 15 28L Pb-Free TSOP (Forward)
(July, 2006, Version 1.0) 10 AMIC Technology, Corp.